On Mon, Jul 01, 2019 at 08:05:51PM +, Vineet Gupta wrote:
> On 5/31/19 1:21 AM, Peter Zijlstra wrote:
> > On Thu, May 30, 2019 at 11:22:42AM -0700, Vineet Gupta wrote:
> >> Had an interesting lunch time discussion with our hardware architects
> >> pertinent to
> >> "minimal guarantees expected
On 5/31/19 1:21 AM, Peter Zijlstra wrote:
> On Thu, May 30, 2019 at 11:22:42AM -0700, Vineet Gupta wrote:
>> Hi Peter,
>>
>> Had an interesting lunch time discussion with our hardware architects
>> pertinent to
>> "minimal guarantees expected of a CPU" section of memory-barriers.txt
>>
>>
>> | (*
On Thu, Jun 06, 2019 at 04:34:52PM +, David Laight wrote:
> From: Paul E. McKenney
> > Sent: 06 June 2019 10:44
> ...
> > But m68k is !SMP-only, correct? If so, the only issues would be
> > interactions with interrupt handlers and the like, and doesn't current
> > m68k hardware use exact inter
From: Paul E. McKenney
> Sent: 06 June 2019 10:44
...
> But m68k is !SMP-only, correct? If so, the only issues would be
> interactions with interrupt handlers and the like, and doesn't current
> m68k hardware use exact interrupts? Or is it still possible to interrupt
> an m68k in the middle of an
Hi Paul,
On Thu, Jun 6, 2019 at 11:43 AM Paul E. McKenney wrote:
> On Tue, Jun 04, 2019 at 09:41:04AM +0200, Geert Uytterhoeven wrote:
> > On Mon, Jun 3, 2019 at 10:14 PM Paul E. McKenney
> > wrote:
> > > On Mon, Jun 03, 2019 at 06:08:35PM +, Vineet Gupta wrote:
> > > > On 5/31/19 1:21 AM,
On Tue, Jun 04, 2019 at 09:41:04AM +0200, Geert Uytterhoeven wrote:
> Hi Paul,
>
> On Mon, Jun 3, 2019 at 10:14 PM Paul E. McKenney
> wrote:
> > On Mon, Jun 03, 2019 at 06:08:35PM +, Vineet Gupta wrote:
> > > On 5/31/19 1:21 AM, Peter Zijlstra wrote:
> > > >> I'm not sure how to interpret "n
Hi Paul,
On Mon, Jun 3, 2019 at 10:14 PM Paul E. McKenney wrote:
> On Mon, Jun 03, 2019 at 06:08:35PM +, Vineet Gupta wrote:
> > On 5/31/19 1:21 AM, Peter Zijlstra wrote:
> > >> I'm not sure how to interpret "natural alignment" for the case of double
> > >> load/stores on 32-bit systems where
On 6/3/19 1:13 PM, Paul E. McKenney wrote:
> On Mon, Jun 03, 2019 at 06:08:35PM +, Vineet Gupta wrote:
>> On 5/31/19 1:21 AM, Peter Zijlstra wrote:
I'm not sure how to interpret "natural alignment" for the case of double
load/stores on 32-bit systems where the hardware and ABI allow f
On Mon, Jun 03, 2019 at 06:08:35PM +, Vineet Gupta wrote:
> On 5/31/19 1:21 AM, Peter Zijlstra wrote:
> >> I'm not sure how to interpret "natural alignment" for the case of double
> >> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte
> >> alignment (ARCv2 LDD/STD, ARM L
On 5/31/19 2:41 AM, David Laight wrote:
>> While it seems reasonable form hardware pov to not implement such atomicity
>> by
>> default it seems there's an additional burden on application writers. They
>> could
>> be happily using a lockless algorithm with just a shared flag between 2
>> thread
On 5/31/19 1:21 AM, Peter Zijlstra wrote:
> And I'll stand by my earlier conviction that any architecture that has a
> native u64 (be it a 64bit arch or a 32bit with double-width
> instructions) but has an ABI that allows u32 alignment on them is daft.
Why ? For 64-bit data on 32-bit systems, hard
On 5/31/19 1:21 AM, Peter Zijlstra wrote:
>> I'm not sure how to interpret "natural alignment" for the case of double
>> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte
>> alignment (ARCv2 LDD/STD, ARM LDRD/STRD )
> Natural alignment: !((uintptr_t)ptr % sizeof(*ptr))
>
On Fri, May 31, 2019 at 09:41:17AM +, David Laight wrote:
> From: Vineet Gupta
> > Sent: 30 May 2019 19:23
> ...
> > While it seems reasonable form hardware pov to not implement such atomicity
> > by
> > default it seems there's an additional burden on application writers. They
> > could
> >
From: Vineet Gupta
> Sent: 30 May 2019 19:23
...
> While it seems reasonable form hardware pov to not implement such atomicity by
> default it seems there's an additional burden on application writers. They
> could
> be happily using a lockless algorithm with just a shared flag between 2
> thread
On Thu, May 30, 2019 at 11:53:58AM -0700, Paul E. McKenney wrote:
> On Thu, May 30, 2019 at 11:22:42AM -0700, Vineet Gupta wrote:
> > Hi Peter,
> >
> > Had an interesting lunch time discussion with our hardware architects
> > pertinent to
> > "minimal guarantees expected of a CPU" section of memo
On Thu, May 30, 2019 at 07:16:36PM +, Vineet Gupta wrote:
> On 5/30/19 11:55 AM, Paul E. McKenney wrote:
> >
> >> I'm not sure how to interpret "natural alignment" for the case of double
> >> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte
> >> alignment (ARCv2 LDD/STD
On Thu, May 30, 2019 at 11:22:42AM -0700, Vineet Gupta wrote:
> Hi Peter,
>
> Had an interesting lunch time discussion with our hardware architects
> pertinent to
> "minimal guarantees expected of a CPU" section of memory-barriers.txt
>
>
> | (*) These guarantees apply only to properly aligned
On 5/30/19 11:55 AM, Paul E. McKenney wrote:
>
>> I'm not sure how to interpret "natural alignment" for the case of double
>> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte
>> alignment (ARCv2 LDD/STD, ARM LDRD/STRD )
>>
>> I presume (and the question) that lkmm doesn
On Thu, May 30, 2019 at 11:22:42AM -0700, Vineet Gupta wrote:
> Hi Peter,
>
> Had an interesting lunch time discussion with our hardware architects
> pertinent to
> "minimal guarantees expected of a CPU" section of memory-barriers.txt
>
>
> | (*) These guarantees apply only to properly aligned
Hi Peter,
Had an interesting lunch time discussion with our hardware architects pertinent
to
"minimal guarantees expected of a CPU" section of memory-barriers.txt
| (*) These guarantees apply only to properly aligned and sized scalar
| variables. "Properly sized" currently means variables
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