On Tue, 2015-12-15 at 22:51 +0100, Arnd Bergmann wrote:
> On Wednesday 16 December 2015 00:04:45 Sergei Ianovich wrote:
> > index 000..5f9a4c1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/serial/lp8x4x-serial.txt
> > @@ -0,0 +1,35 @@
> > +UART ports on ICP DAS LP-8x4x
> > +
> >
No need to use use continuous memory, it may be fail
when memory deeply fragmented.
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
---
drivers/base/firmware_class.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/base/firmware_class.c b/drivers/base/firmwa
On 12/16/2015 04:18 AM, Baolin Wang wrote:
> From the dm-crypt performance report, we found it shows low efficiency
> with crypto engine for some mode (like ecb or xts mode). Because in dm
> crypt, it will map the IO data buffer with scatterlist, and send the
> scatterlist of one bio to the encrypt
On 12/15/2015 05:25 PM, Xiao Guangrong wrote:
On 12/15/2015 04:43 PM, Kai Huang wrote:
On 12/01/2015 02:26 AM, Xiao Guangrong wrote:
Now, all non-leaf shadow page are page tracked, if gfn is not tracked
there is no non-leaf shadow page of gfn is existed, we can directly
make the shadow pa
Hi!
> > Rusty, does the switcher need to be W+X?
> >
> > And yes, I have lguest enabled, not sure why.
>
> No. The layout is " ..." and I lazily
> did that as a single
> map_vm_area(switcher_vma, PAGE_KERNEL_EXEC, lg_switcher_pages);
>
> This boots, does it solve the problem?
Let me s
Hi Boris,
On 12/16/2015 12:03 PM, Boris Brezillon wrote:
Hi Archit,
Sorry for the late review, but there are a few things I think should be
addressed.
On Wed, 19 Aug 2015 10:19:04 +0530
Archit Taneja wrote:
Add DT bindings document for the Qualcomm NAND controller driver.
Cc: devicet...@vg
Hi Magnus,
On Tue, Dec 15, 2015 at 2:05 PM, Magnus Damm wrote:
> From: Magnus Damm
>
> Introduce struct ipmmu_features to track various hardware
> and software implementation changes inside the driver for
> various kinds of IPMMU hardware. Add use_ns_alias_offset
> as a first example of a featur
Add RK3036-specific configuration for Kylin board.
Signed-off-by: Caesar Wang
---
arch/arm/configs/rk3036_kylin_defconfig | 230
1 file changed, 230 insertions(+)
create mode 100644 arch/arm/configs/rk3036_kylin_defconfig
diff --git a/arch/arm/configs/rk3036_
From: Yakir Yang
ACLK_VIO is the noc bus clock for display module, display cann't
read data from ddr without this clock enabled.
Due to it shouldn't belong to any driver, but we need it enabled,
so just mark it as the CLK_IGNORE_UNUSED flag.
Signed-off-by: Yakir Yang
Signed-off-by: Caesar Wang
Use the newly introduced possibility to combine the fractional dividers
with their downstream muxes for all fractional dividers on currently
supported RK3036 SoCs.
Signed-off-by: Xing Zheng
Signed-off-by: Caesar Wang
---
drivers/clk/rockchip/clk-rk3036.c | 35 ++
This patchset is the initiation version to try work
for kylin board.
Signed-off-by: Caesar Wang
---
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3036-kylin.dts | 302 ++
version for working.
This series pacthes have the following decriptions:
PATCH[1/5]:
clk: rockchip: rk3036: include downstream muxes into fractional dividers
This patch is depend on Heiko's series pacthes.
a8a1de6 clk: rockchip: include downstream muxes into fractional dividers
(https://patchwo
Update the core dts for rk3036 SoCs.
1) Add the display (lcdc, hdmi, vop...) device node.
2) modify the i2s name to i2s0 and i2s1.
Although there is only one i2s IP inside the rk3036,
we need use all of the gpios of i2s0 and i2s1.
So, we add the i2s1 IP is the same with i2s0 to support th
On 12/16/2015 03:31 PM, Kai Huang wrote:
On 12/15/2015 05:03 PM, Xiao Guangrong wrote:
On 12/15/2015 04:11 PM, Kai Huang wrote:
On 12/01/2015 02:26 AM, Xiao Guangrong wrote:
The page fault caused by write access on the write tracked page can not
be fixed, it always need to be emulated.
On 16 December 2015 at 16:08, Milan Broz wrote:
> On 12/16/2015 04:18 AM, Baolin Wang wrote:
>> From the dm-crypt performance report, we found it shows low efficiency
>> with crypto engine for some mode (like ecb or xts mode). Because in dm
>> crypt, it will map the IO data buffer with scatterlist
On Tue, Dec 15, 2015 at 05:25:56PM -0500, Lyude wrote:
> We currently call drm_helper_hpd_irq_event() to handle reprobing
> displays on resume, however drm_helper_hpd_irq_event() only checks the
> status of hpd. HPD doesn't update if the displays connected changed
> before resuming the system, and
On Wed, Dec 16, 2015 at 11:59 AM, Dawei Chien wrote:
>
> This adds thermal zone node to Mediatek MT8173 dtsi file.
>
> Signed-off-by: Dawei Chien
> ---
> This patch is base on patchset:
> https://lkml.org/lkml/2015/11/30/239
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 43
>
Op 15-12-15 om 18:19 schreef Dmitry Torokhov:
> On Tue, Dec 15, 2015 at 2:01 AM, Maarten Lankhorst
> wrote:
>> Op 15-12-15 om 02:29 schreef Dmitry Torokhov:
>>> Userspace can close the sync device while there are still active fence
>>> points, in which case kernel produces the following warning:
>
On 12/16/2015 03:51 PM, Kai Huang wrote:
On 12/15/2015 05:10 PM, Xiao Guangrong wrote:
On 12/15/2015 03:52 PM, Kai Huang wrote:
static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
@@ -2140,12 +2150,18 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct
kvm_vcpu *vcpu,
On 12/16/2015 04:05 PM, Kai Huang wrote:
On 12/15/2015 05:25 PM, Xiao Guangrong wrote:
On 12/15/2015 04:43 PM, Kai Huang wrote:
On 12/01/2015 02:26 AM, Xiao Guangrong wrote:
Now, all non-leaf shadow page are page tracked, if gfn is not tracked
there is no non-leaf shadow page of gfn is
On Tue, Dec 15, 2015 at 04:54:24PM -0800, Andi Kleen wrote:
> +ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute
> *attr,
> + char *page)
> +{
> + struct perf_pmu_events_ht_attr *pmu_attr =
> + container_of(attr, struct perf_pmu_events_
On Tue, 2015-12-15 at 04:01PM +0100, Michal Simek wrote:
> Hi,
>
> On 15.12.2015 10:14, Sören Brinkmann wrote:
> > On Mon, 2015-12-14 at 05:01PM +, Marc Zyngier wrote:
> >> Mark,
> >>
> >> On 14/12/15 16:46, Mark Rutland wrote:
> >>> On Mon, Dec 14, 2015 at 08:31:40AM -0800, Soren Brinkmann wr
On 12/16/2015 08:28 AM, Jisheng Zhang wrote:
On Wed, 16 Dec 2015 15:11:25 +0800
Jisheng Zhang wrote:
Dear Daniel,
On Tue, 15 Dec 2015 21:59:30 +0100 Daniel Lezcano wrote:
On 11/25/2015 04:42 PM, Jisheng Zhang wrote:
Let's assume the counter value is 0xf00, the pistachio clocksource
o
On 12/16/2015 08:11 AM, Jisheng Zhang wrote:
Dear Daniel,
On Tue, 15 Dec 2015 21:59:30 +0100 Daniel Lezcano wrote:
On 11/25/2015 04:42 PM, Jisheng Zhang wrote:
Let's assume the counter value is 0xf00, the pistachio clocksource
read cycles function would return 0x0fff, but it s
On Tue, 2015-12-15 at 03:26PM -0800, Peter Hurley wrote:
> On 12/15/2015 07:41 AM, Sören Brinkmann wrote:
> > On Thu, 2015-12-10 at 01:41PM -0800, Peter Hurley wrote:
> >> On 12/05/2015 08:39 PM, Soren Brinkmann wrote:
> >>> Request_irq() should be _after_ h/w programming, otherwise an
> >>> interr
On 16/12/15 09:01, Sören Brinkmann wrote:
> On Tue, 2015-12-15 at 04:01PM +0100, Michal Simek wrote:
>> Hi,
>>
>> On 15.12.2015 10:14, Sören Brinkmann wrote:
>>> On Mon, 2015-12-14 at 05:01PM +, Marc Zyngier wrote:
Mark,
On 14/12/15 16:46, Mark Rutland wrote:
> On Mon, Dec 14
No need to use use continuous memory, it may be fail
when memory deeply fragmented.
Signed-off-by: Chen Feng
Signed-off-by: Xia Qing
---
drivers/base/firmware_class.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/base/firmware_class.c b/drivers/base/firmwa
Hi Archit,
Again, sorry for the late review. It's probably not exhaustive but
points a few things that should be fixed.
On Wed, 19 Aug 2015 10:19:03 +0530
Archit Taneja wrote:
> The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
> MDM9x15 series.
>
> It exists as a sub block
On Tue, Dec 15, 2015 at 08:14:34PM -0600, Suravee Suthikulpanit wrote:
> Hi Mika,
>
> On 12/15/15 15:55, Suravee Suthikulpanit wrote:
> >Add device HID AMDI0510 to match the I2C controlers on AMD Seattle platform
> >
> >Signed-off-by: Suravee Suthikulpanit
> >---
> > drivers/i2c/busses/i2c-desig
Xishi Qiu writes:
> On 2015/12/16 2:05, Vitaly Kuznetsov wrote:
>
>> Currently, all newly added memory blocks remain in 'offline' state unless
>> someone onlines them, some linux distributions carry special udev rules
>> like:
>>
>> SUBSYSTEM=="memory", ACTION=="add", ATTR{state}=="offline",
>>
On 12/16/2015 08:36 AM, Jisheng Zhang wrote:
On Wed, 16 Dec 2015 15:28:07 +0800 wrote:
On Wed, 16 Dec 2015 15:11:25 +0800
Jisheng Zhang wrote:
Dear Daniel,
On Tue, 15 Dec 2015 21:59:30 +0100 Daniel Lezcano wrote:
On 11/25/2015 04:42 PM, Jisheng Zhang wrote:
Let's assume the counter value
Daniel Kiper writes:
> Hey Vitaly,
>
> On Tue, Dec 15, 2015 at 07:05:53PM +0100, Vitaly Kuznetsov wrote:
>> Currently, all newly added memory blocks remain in 'offline' state unless
>> someone onlines them, some linux distributions carry special udev rules
>> like:
>>
>> SUBSYSTEM=="memory", ACTI
Hi Luca,
On 15/12/15 22:24, Luca Abeni wrote:
> On Tue, 15 Dec 2015 14:42:29 +0100
> Peter Zijlstra wrote:
> > On Tue, Dec 15, 2015 at 02:30:07PM +0100, Luca Abeni wrote:
> >
> > > >So I remember something else from the BFQ code, which also had to
> > > >track entries for the 0-lag stuff, and I
On Tue, Dec 15, 2015 at 11:14:32AM -0800, Nish Aravamudan wrote:
> [Apologies for the resend, didn't realize I hadn't changed my GMail settings
> to not use HTML.]
>
> I have recently purchased a Lenovo Yoga 900 and most everything is working
> with a slightly modified 4.4-rc5 (https://lkml.org/lk
On 16/12/15 01:10, Noam Camus wrote:
> From: Noam Camus
>
> Adding EZchip NPS400 support.
> NPS internal interrupts are internally handled at
> Multi Thread Manager (MTM) that is signaled for deactivating
> an interrupt.
> External interrupts is handled also at Global Interrupt
> Controller (GIC)
Hi,
So you were using 4.4-rc5 before and it worked, but after applying a
patch it stopped?
The patch you pasted seems to relate to dts files and declarations in
it - did anything there change?
Best regards,
Crt
On 15 December 2015 at 20:19, Nish Aravamudan wrote:
> So, I apologize in advance fo
On Wed, Dec 16, 2015 at 10:21:55AM +0100, Daniel Lezcano wrote:
> On 12/16/2015 08:36 AM, Jisheng Zhang wrote:
> >And in fact, clocksource_mmio_readw_down() also has similar issue, but it
> >masks
> >with c->mask before return, the c->mask is less than 32 bit (because the
> >clocksource_mmio_init
Hi Ulf,
On 15/12/15 19:54, Ulf Hansson wrote:
> On 4 December 2015 at 15:57, Jon Hunter wrote:
>> Enable PM_GENERIC_DOMAINS for tegra 64-bit devices. To ensure that devices
>> dependent upon a particular power-domain are only probed when that power
>> domain has been powered up, requires that PM
+Jarkko and Andy
On Tue, Dec 15, 2015 at 04:38:58PM -0600, Suravee Suthikulpanit wrote:
> The current driver uses input clock source frequency to calculate
> values for [SS|FS]_[HC|LC] registers. However, when booting ACPI, we do not
> currently have a good way to provide the frequency information
On Tue, Dec 15, 2015 at 9:19 PM, Nish Aravamudan
wrote:
> So, I apologize in advance for this relatively vague report, but I'm fairly
> sure
> the Yoga 900 has an accelerometer amongst other sensors (ambient light?)
> exported over IIO.
>
> But, these sensors seem to not be updating at all with a
The stride value should always equal to 2^n, so we can use bit
rotation instead of % to improve the performance.
Signed-off-by: Xiubo Li
---
drivers/base/regmap/regmap.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/base/regmap/regmap.c b/drivers/ba
On 16 December 2015 at 10:40, Jon Hunter wrote:
> Hi Ulf,
>
> On 15/12/15 19:54, Ulf Hansson wrote:
>> On 4 December 2015 at 15:57, Jon Hunter wrote:
>>> Enable PM_GENERIC_DOMAINS for tegra 64-bit devices. To ensure that devices
>>> dependent upon a particular power-domain are only probed when th
Update Srinivas Gowda as dcdbas driver Maintainer
Signed-off-by: Srinivas Gowda
Acked-by: Doug Warzecha
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 79c2e48..7e3a8d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3390,7 +33
On 16 December 2015 at 02:27, Krzysztof Kozlowski
wrote:
> 2015-12-16 10:11 GMT+09:00 Sebastian Reichel :
>> Hi,
>>
>> On Tue, Dec 15, 2015 at 04:53:31PM -0800, Eric Anholt wrote:
>>> >>> What motivated the location of this power domain driver in
>>> >>> arch/arm/mach-bcm? Should not we have this
On Wed, 2015-12-16 at 16:34 +0800, Daniel Kurtz wrote:
> On Wed, Dec 16, 2015 at 11:59 AM, Dawei Chien
> wrote:
> >
> > This adds thermal zone node to Mediatek MT8173 dtsi file.
> >
> > Signed-off-by: Dawei Chien
> > ---
> > This patch is base on patchset:
> > https://lkml.org/lkml/2015/11/30/23
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller
IP. This series adds support for a Synopsys DesignWare MIPI DSI host
controller DRM driver.
The MIPI DSI feature is tested on rk3288 evb board, backport them to
chrome os kernel chrome_v3.14, and it can display normally.
This
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Change
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5:
- add a blank line befor lcd_en
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v6:
- update the document, since the bridge device has been deleted.
Changes in v5: None
Changes in v4: None
Changes in v3:
- move dw_mipi_dsi_rockchip.txt
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5:
- modify the clk name to SCLK_MIPIDSI_24M
Changes in v4: None
Changes in v3: None
arch/arm/boot/dts/rk3288.dtsi | 39
Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v6:
- Do not use bridge driver (Thierry Reding)
- Optimization the phy init sequence
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/
On 11/12/15 09:08, Linus Walleij wrote:
On Fri, Dec 4, 2015 at 6:31 PM, Martyn Welch
wrote:
Select Chromebooks have gpio attached to switches used to cause the
firmware to enter alternative modes of operation and/or control other
device characteristics (such as write protection on flash devi
From: Liu Ying
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_
Arnd, Olof, Kevin,
This is the first PR for AT91 DT material targeted to 4.5. The main part is the
addition for the new DENX platform. Other things are simply basic fixes and
updates.
Thanks, best regards,
The following changes since commit 31ade3b83e1821da5fbb2f11b5b3d4ab2ec39db8:
Linux 4.4-
On Wed, Dec 16, 2015 at 04:01:43PM +1100, Stephen Rothwell wrote:
> Hi Andrew,
>
> Today's linux-next merge of the akpm-current tree got a conflict in:
>
> include/linux/memblock.h
>
> between commit:
>
> bf3d3cc580f9 ("mm/memblock: add MEMBLOCK_NOMAP attribute to memblock memory
> table")
On Tue, Dec 15, 2015 at 09:48:06PM -0800, John Stultz wrote:
> Thus its been occasionally noted that users have seen
> confusing warnings like:
>
> Adjusting tsc more than 11% (5941981 vs 7759439)
> v2: Catch single unit adjustment that was being made
> repeatedly to push us past the limi
On 12/15/2015 07:54 PM, Mathieu Desnoyers wrote:
> One instance of "sys_membarrier" needs to be renamed to "membarrier" for
> consistency.
Thanks, Mathieu. Applied.
Cheers,
Michael
> Signed-off-by: Mathieu Desnoyers
> CC: Michael Kerrisk
> ---
> man2/membarrier.2 | 2 +-
> 1 file changed, 1
[...]
>> It seems like a reasonable assumption that the controller can't cope
>> with a higher clock rate than 100 MHz as "input" clock. That would
>> then mean that there are different versions of the controller, as it
>> seems like for some version it's fine with 200MHz and for some 100MHz.
>>
>
Dexuan Cui writes:
>> From: devel [mailto:driverdev-devel-boun...@linuxdriverproject.org] On Behalf
>> Of K. Y. Srinivasan
>> Sent: Wednesday, December 16, 2015 8:27
>> To: gre...@linuxfoundation.org; linux-kernel@vger.kernel.org;
>> de...@linuxdriverproject.org; o...@aepfle.de; a...@canonical.co
Arnd, Olof, Kevin,
As single patch for this pull-request: tell me if you would like to take it
independently, as a patch.
Thanks, best regards,
The following changes since commit 31ade3b83e1821da5fbb2f11b5b3d4ab2ec39db8:
Linux 4.4-rc3 (2015-11-29 18:58:26 -0800)
are available in the git repo
On 12/15/2015 06:30 PM, Jason Gunthorpe wrote:
> On Tue, Dec 15, 2015 at 05:38:34PM +0100, Michael Wang wrote:
>> The hop_limit is only suggest that the package allowed to be
>> routed, not have to, correct?
>
> If the hop limit is >= 2 (?) then the GRH is mandatory. The
> SM will return this inf
On Wednesday 16 December 2015 11:04:57 Sergei Ianovich wrote:
> On Tue, 2015-12-15 at 22:51 +0100, Arnd Bergmann wrote:
> > On Wednesday 16 December 2015 00:04:45 Sergei Ianovich wrote:
> > > index 000..5f9a4c1
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/serial/lp8x4x-seri
On 2015/12/16 1:37, Steven Rostedt wrote:
> On Tue, 15 Dec 2015 11:26:41 +0800
> "Zhang, Yanmin" wrote:
>
>>> This seems very hackish, although I can't think of a better way at the
>>> moment. But I would like not to add more code into module.c if
>>> possible, and just use a notifier unless ther
PCI-2.2 VPD entries have a maximum size of 32k, but might actually
be smaller than that. To figure out the actual size one has to read
the VPD area until the 'end marker' is reached.
Trying to read VPD data beyond that marker results in 'interesting'
effects, from simple read errors to crashing the
On Wed, Aug 19, 2015 at 12:44:16AM +0800, fu@linaro.org wrote:
> From: Huang Ying
>
> Under normal circumstances, when a hardware error occurs, kernel will
> be notified via NMI, MCE or some other method, then kernel will
> process the error condition, report it, and recover it if possible.
>
On Wed, Aug 19, 2015 at 12:44:17AM +0800, fu@linaro.org wrote:
> From: Tomasz Nowicki
>
> Once error log is printed out clear error status so it would not be
> print during next boot again.
>
> Signed-off-by: Tomasz Nowicki
> Signed-off-by: Chen, Gong
> Tested-by: Jonathan (Zhixiong) Zhang
Add myself as a co-maintainer for Renesas Pin Controllers.
Signed-off-by: Geert Uytterhoeven
---
To be included in next sh-pfc-for-v4.5 pull request.
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e9caa4b288284b92..f625860effec8c16 100644
--- a/M
On 12/16/2015 10:33 AM, Russell King - ARM Linux wrote:
On Wed, Dec 16, 2015 at 10:21:55AM +0100, Daniel Lezcano wrote:
On 12/16/2015 08:36 AM, Jisheng Zhang wrote:
And in fact, clocksource_mmio_readw_down() also has similar issue, but it masks
with c->mask before return, the c->mask is less th
Convert the dw_wdt driver to the new watchdog core api.
Signed-off-by: Jisheng Zhang
---
This patch depends on the signedness bug fix patch:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/393872.html
drivers/watchdog/Kconfig | 1 +
drivers/watchdog/dw_wdt.c | 316 +++
On 15/12/15 23:32, Krzysztof Kozlowski wrote:
On 16.12.2015 01:35, Sudeep Holla wrote:
On 21/10/15 11:10, Sudeep Holla wrote:
Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "linux-keypad,wakeup" boolean property to enable the
wakeup source, "wake
Hi Eric,
Am 16.12.2015 um 00:35 schrieb Eric Anholt:
> These will be used for enabling UART1, SPI1, and SPI2.
>
> Signed-off-by: Eric Anholt
> ---
>
> v2: Make the binding cover both the IRQ and clock enable registers.
>
> arch/arm/boot/dts/bcm2835.dtsi | 7 +++
> 1 file changed, 7 insertion
On Wed, Dec 16, 2015 at 11:32:17AM +0100, Daniel Lezcano wrote:
> On 12/16/2015 10:33 AM, Russell King - ARM Linux wrote:
> >On Wed, Dec 16, 2015 at 10:21:55AM +0100, Daniel Lezcano wrote:
> >>On 12/16/2015 08:36 AM, Jisheng Zhang wrote:
> >>>And in fact, clocksource_mmio_readw_down() also has simi
Hi,
On Mon, Dec 14, 2015 at 09:11:14AM +0100, Marcus Weseloh wrote:
> Adds a new property "spi-word-wait-ns" to the spi-bus binding that allows
> SPI slave devices to set a wait time between the transmission of words.
> Modifies the spi_device struct and slave device probing to read and store
> th
On 15/12/15 11:55, Will Deacon wrote:
On Wed, Dec 09, 2015 at 09:57:15AM +, Suzuki K. Poulose wrote:
/*
* Initial data for bringing up a secondary CPU.
+ * @stack - sp for the secondary CPU
+ * @status - Result passed back from the secondary CPU to
+ * indicate failure.
> From: Vitaly Kuznetsov [mailto:vkuzn...@redhat.com]
> ...
> >> @@ -109,7 +109,7 @@ static unsigned int hvt_op_poll(struct file *file,
> >> poll_table *wait)
> >>poll_wait(file, &hvt->outmsg_q, wait);
> >>
> >>if (hvt->mode == HVUTIL_TRANSPORT_DESTROY)
> >> - return -EBADF;
> >> +
On 2015/12/16 17:17, Vitaly Kuznetsov wrote:
> Xishi Qiu writes:
>
>> On 2015/12/16 2:05, Vitaly Kuznetsov wrote:
>>
>>> Currently, all newly added memory blocks remain in 'offline' state unless
>>> someone onlines them, some linux distributions carry special udev rules
>>> like:
>>>
>>> SUBSYST
Hi Hannes,
[auto build test ERROR on pci/next]
[also build test ERROR on v4.4-rc5 next-20151216]
url:
https://github.com/0day-ci/linux/commits/Hannes-Reinecke/pci-Update-VPD-size-with-correct-length/20151216-183013
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
On Tue, Dec 15, 2015 at 11:15:06PM +, Mans Rullgard wrote:
> The Sigma Designs variant of this controller has the ability to generate
> interrupts. This is controlled using two additional registers, oddly
> enough overlapping with the defined but unused HDSTATIM.
>
> This patch adds support f
On Tue, Dec 15, 2015 at 11:15:05PM +, Mans Rullgard wrote:
> The BYTECNT register holds the transfer size minus one. Setting it to
> the correct value removes the need for a dummy read/write at the end of
> each transfer. As zero-length transfers are not supported, do not
> advertise I2C_FUNC
IFC NAND is not working on ARM layescape platform due to
undefined macro FSL_SOC.
This patch fixes the dependency to enable NAND.
Signed-off-by: Raghav Dogra
---
drivers/memory/Kconfig | 2 +-
drivers/memory/fsl_ifc.c | 4 +++-
drivers/mtd/nand/Kconfig | 2 +-
3 files changed, 5 insertions(+)
On Thu, 10 Dec 2015, Josh Poimboeuf wrote:
> On Wed, Dec 09, 2015 at 03:05:23PM -0500, Jessica Yu wrote:
> > +++ Josh Poimboeuf [08/12/15 12:32 -0600]:
> > >On Mon, Nov 30, 2015 at 11:21:15PM -0500, Jessica Yu wrote:
> > >>For livepatch modules, copy Elf section, symbol, and string information
> >
Hi,
On Tue, Dec 15, 2015 at 02:52:08AM +0100, Danny Milosavljevic wrote:
> Hi Maxime,
>
> On Sun, 13 Dec 2015 21:58:39 +0100
> Maxime Ripard wrote:
>
> > This is not the branch you should be basing your patch on. This is an
> > ASoC patch, base it on the ASoC tree.
>
> Okay, will do. To the br
[...]
> +static int pic32_sdhci_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct sdhci_host *host;
> + struct resource *iomem;
> + struct pic32_sdhci_pdata *sdhci_pdata;
> + struct pic32_sdhci_platform_data *plat_data;
> +
PCI-2.2 VPD entries have a maximum size of 32k, but might actually
be smaller than that. To figure out the actual size one has to read
the VPD area until the 'end marker' is reached.
Trying to read VPD data beyond that marker results in 'interesting'
effects, from simple read errors to crashing the
This partially reverts commit a34236155afb1cc41945e58388ac988431bcb0b8.
While reviewing the glibc patch to exploit the individual IPC calls,
Arnd & Andreas noticed that we were still requiring userspace to pass
IPC_64 in order to get the new style IPC API.
With a bit of cleanup in the kernel we c
Xishi Qiu writes:
> On 2015/12/16 17:17, Vitaly Kuznetsov wrote:
>
>> Xishi Qiu writes:
>>
>>> On 2015/12/16 2:05, Vitaly Kuznetsov wrote:
>>>
Currently, all newly added memory blocks remain in 'offline' state unless
someone onlines them, some linux distributions carry special udev ru
Hi Caesar,
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on next-20151216]
[cannot apply to clk/clk-next v4.4-rc5]
url:
https://github.com/0day-ci/linux/commits/Caesar-Wang/Kylin-board-is-based-on-RK3036-SOCs-add-the-initiation/20151216-163233
base:
https
Replacing the NO_IRQ macro with 0. If there is no interrupt,
returned value will be 0 regardless of what NO_IRQ is defined.
Signed-off-by: Raghav Dogra
---
drivers/memory/fsl_ifc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_i
On Mon, 30 Nov 2015, Jessica Yu wrote:
> @@ -3530,6 +3614,16 @@ static int load_module(struct load_info *info, const
> char __user *uargs,
> if (err < 0)
> goto bug_cleanup;
>
> + /*
> + * Save sechdrs, indices, and other data from info
> + * in order to patch
IFC has two set of registers viz FCM (Flash control machine)
aka global and run time registers. These set are defined in two
memory map PAGES. Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0
PAGE size is 64KB
Signed-off-by: Jaiprakash Singh
Signed-off-by: Raghav Dogra
---
drivers/memory/fsl_ifc.
Hi Boris,
That's fine - I hope to get a new version ready soon.
Thanks,
Harvey
On 14/12/15 16:25, Boris Brezillon wrote:
Hi Harvey,
I'm currently reworking the NAND subsystem to simplify NAND controller
drivers (see this series [1]), and some of my patches have made it into
Brian's tree.
Wou
On Wed, Dec 16, 2015 at 12:18:30PM +0900, Kamezawa Hiroyuki wrote:
> Hmm, my requests are
> - set the same capabilities as mlock() to set swap.limit=0
Setting swap.max is already privileged operation.
> - swap-full notification via vmpressure or something mechanism.
Why?
> - OOM-Killer's ava
> -Original Message-
> From: Borislav Petkov [mailto:b...@alien8.de]
> Sent: Wednesday, November 04, 2015 4:00 AM
>
> On Mon, Nov 02, 2015 at 06:47:29AM +, Kweh, Hock Leong wrote:
> > By looking at your dmesg log, the above print out message seem that
> > someone has called the flush()
On Tue, Dec 15, 2015 at 04:18:08PM -0800, Yang Shi wrote:
> The kernel just send out a SIGTRAP signal when handling ptrace breakpoint in
> debug exception, so it sounds safe to have interrupt enabled if it is not
> disabled by the parent process.
Is this actually fixing an issue you're seeing, or
Hello.
On 12/16/2015 2:25 AM, Mans Rullgard wrote:
This adds support for powering on an optional PHY when activating the
device.
Signed-off-by: Mans Rullgard
[...]
diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
index 9985749..d07aae1 100644
--- a/drivers/ata/sata_d
Hi Andrew,
On 16/12/15 03:01, Andrew Pinski wrote:
> On Tue, Dec 9, 2015 at 17:26:56, Catalin Marinas
> wrote:
>>
>> Currently the BUG_ON() checks do not give enough information about the PTEs
>> being set. This patch changes BUG_ON to WARN_ONCE and dumps the values of
>> the old and new PTEs.
On Wed, Dec 16, 2015 at 12:13:50AM +0100, Sebastian Reichel wrote:
> On Tue, Dec 15, 2015 at 11:52:10AM -0800, Tim Bird wrote:
> > Add a binding for the regulator which controls the OTG chargepath switch.
> > The OTG switch gets its power from pm8941_5vs1, and that should be
> > expressed as a usb_
2015-12-15 21:13 GMT-03:00 Joe Perches :
> On Tue, 2015-12-15 at 20:58 -0300, Geyslan G. Bem wrote:
>> 2015-12-10 8:24 GMT-03:00 Geyslan G. Bem :
>> > Suggested-by: Peter Senna Tschudin
>> > Reported-by: Geyslan G. Bem
>> >
>>
>> Joe, do you applied this patch? If not, would I send it?
>
> You ca
On Wed, Dec 16, 2015 at 6:09 PM, dawei chien wrote:
> On Wed, 2015-12-16 at 16:34 +0800, Daniel Kurtz wrote:
>> On Wed, Dec 16, 2015 at 11:59 AM, Dawei Chien
>> wrote:
>> >
>> > This adds thermal zone node to Mediatek MT8173 dtsi file.
>> >
>> > Signed-off-by: Dawei Chien
>> > ---
>> > This pat
On 23/11/15 03:15, MaJun wrote:
> From: Ma Jun
>
> This patch set adds the driver of mbigen and binding document for Hisilicon
> Mbigen chips.
[...]
Any update on this? If this is to be 4.5 material, I'd like to see the
various comments addressed shortly so that I can queue it.
Thanks,
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