From: Borislav Petkov
Hi guys,
here's v1, all feedback I know of has been addressed. So I guess it is
time. :)
We don't have it default y yet but will make it so after it has seen
wider testing. The end goal is to have it running by default so that
transient correctable ECC errors don't generat
From: Nicolas Ferre
commit b1708b72a0959a032cd2eebb77fa9086ea3e0c84 upstream
The dmas/dma-names properties are added to the UART nodes. Note that additional
properties are needed to enable them at the board level: check bindings for
details.
Cc: # 4.4.x
Signed-off-by: Nicolas Ferre
Signed-off
From: Andi Kleen
Since
cd9c57cad3fe ("x86/MCE: Dump MCE to dmesg if no consumers")
all MCEs are printed even when mcelog is running. Fix the regression to
not print to dmesg when mcelog is running as it is a consumer too.
Signed-off-by: Andi Kleen
Cc: sta...@vger.kernel.org # 4.10..
Cc: Ton
From: Borislav Petkov
We call it everywhere "struct mce *m". Adjust that here too to avoid
confusion.
No functionality change.
Signed-off-by: Borislav Petkov
---
arch/x86/kernel/cpu/mcheck/mce.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/mc
From: Borislav Petkov
A simple data structure for collecting correctable errors along with
accessors. More detailed description in the code itself.
The error decoding is done with the decoding chain now and
mce_first_notifier() gets to see the error first and the CEC decides
whether to log it an
From: Liang Chen
This patch adds core dtsi file for Rockchip RK3328 SoCs.
Signed-off-by: Liang Chen
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1275 ++
1 file changed, 1275 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328.dtsi
diff --git a/
On 2017年03月22日 22:36, Colin King wrote:
From: Colin Ian King
The variable 'data' is assigned null and never re-assigned. There
is also a redundant check for data being non-null which is always
false, so remove this and the variable data and dma_addr as they
are not used once the dead code has
From: Liang Chen
This patch add rk3328-evb.dts for RK3328 evaluation board.
Tested on RK3328 evb.
Signed-off-by: Liang Chen
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 57 +
2 files changed, 58 insertions(+)
From: Liang Chen
Signed-off-by: Liang Chen
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/soc/rockchip/grf.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
index
From: Liang Chen
The rk3328 saradc is the same as rk3399.
Signed-off-by: Liang Chen
Reviewed-by: Heiko Stuebner
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/ad
From: Liang Chen
Changes in v4:
Remove some assigned-clocks as they should be inited in their
respective device nodes.
Changes in v3:
Adjust some descriptions in dtsi.
Changes in v2:
Remove RK_FUNC_* in dtsi as it dose not help understand things better.
Adjust the order of d
On Mon, Mar 27, 2017 at 02:21:41PM +0800, Elaine Zhang wrote:
> Add support for the rk805 regulator. The regulator module consists
> of 4 DCDCs, 3 LDOs.
>
> The output voltages are configurable and are meant to supply power
> to the main processor and other components.
Acked-by: Mark Brown
sig
2017-03-24 16:58 GMT+01:00 Rob Herring :
> On Mon, Mar 20, 2017 at 02:32:22PM +0100, Richard Genoud wrote:
>> This adds support for the Winstar Display Co. WF35LTIACD 3.5" QVGA TFT
>> LCD panel, which can be supported by the simple panel driver.
>>
>> Signed-off-by: Richard Genoud
>> ---
>>
>> Cha
One of the features of STM32 trigger hardware block is a quadrature
encoder that can counts up/down depending of the levels and edges
of the selected external pins.
This patch allow to read/write the counter, get it direction,
set/get quadrature modes and get scale factor.
When counting up preset
Device counting could be controlled by the level or the edges of
a trigger.
in_count0_enable_mode attibute allow to set the control mode.
Signed-off-by: Benjamin Gaignard
---
.../ABI/testing/sysfs-bus-iio-timer-stm32 | 23 +++
drivers/iio/trigger/stm32-timer-trigger.c | 70
From: Liang Chen
Use "rockchip,rk3328-evb" compatible string for Rockchip RK3328
evaluation board.
Signed-off-by: Liang Chen
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/rockchip.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/a
A first encoder IIO driver (104-quad-8) with a count channel already exist.
STM32 driver have the same type of feature but with different counting modes.
Some parts, like counting direction (up/down) could be generalized so move the
corresponding documentation from driver file to sysfs-bus-iio.
ve
Adds a new endpoint function driver (to program the virtual
test device) making use of the EP-core library.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/Kconfig | 2 +
drivers/pci/endpoint/Makefile | 2 +-
drivers/pci/endpoint/functions/Kcon
Hi Bjorn,
Please find the pull request for PCI endpoint support below. I've
also included all the history here.
Changes from v4:
*) add #syscon-cells property and used of_parse_phandle_with_args
to perform a configuration in syscon module (as suggested by
Rob Herring)
*) Remove unnecessary
Hi Masahiro,
Le 27/03/2017 à 07:26, Masahiro Yamada a écrit :
> Hi Nocolas,
>
>
> 2017-03-24 18:03 GMT+09:00 Nicolas Dichtel :
[snip]
>
>
> As a whole, this series is amazing. Thanks for your great work!
Thank you. And thank you for taking time to review it.
>
>
> I added some comments, bu
Invoke API's provided by pci-ep-cfs to create configfs entry for
every EPC device and EPF driver to help users in creating EPF device
and binding the EPF device to the EPC device.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 4
drivers/pci/endpoint/pci-epf
Add documentation for the optional #syscon-cells property to determine
the number of cells that should be given in the phandle while
referencing the syscon-node.
Suggested-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/mfd/syscon.txt | 2 ++
1 file c
Hi Masahiro,
Le 27/03/2017 à 07:53, Masahiro Yamada a écrit :
> Hi Nicolas,
>
>
> 2017-03-14 21:54 GMT+09:00 Nicolas Dichtel :
[snip]
>> diff --git a/include/uapi/linux/btrfs_tree.h
>> b/include/uapi/linux/btrfs_tree.h
>> index 6a261cb52d95..6a754ada59af 100644
>> --- a/include/uapi/linux/btrfs
Le 27/03/2017 à 07:31, Masahiro Yamada a écrit :
[snip]
>> -#endif /* __ASM_H8300_BITS_PER_LONG */
>> diff --git a/arch/h8300/include/uapi/asm/bitsperlong.h
>> b/arch/h8300/include/uapi/asm/bitsperlong.h
>> new file mode 100644
>> index ..e56cf72369b6
>> --- /dev/null
>> +++ b/arch/h83
Add specification for the *pci test* virtual function device. The endpoint
function driver and the host pci driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/endpoint/pci-test
Add documentation to help users use pci-epf-test function driver
and pci_endpoint_test host driver for testing PCI.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX| 2 +
Documentation/PCI/endpoint/pci-test-howto.txt | 179 ++
2 f
Add device tree binding documentation for pci designware EP mode.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/designware-pcie.txt| 26 +++---
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetr
Add a simple test script that invokes the pcitest userspace tool
to perform all the PCI endpoint tests (BAR tests, interrupt tests,
read tests, write tests and copy tests).
Signed-off-by: Kishon Vijay Abraham I
---
tools/pci/pcitest.sh | 56
1
Add device IDs for DRA74x and DRA72x devices. These devices have
configurable PCI endpoint.
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index a4f77feecbb0..5f6b71d15393 1
Add Documentation to help users use pci endpoint to configure
pci endpoint function and to bind the endpoint function
with endpoint controller.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/endpoint/pci-endpoint-cfs.txt | 105
No functional change. Split dra7xx_pcie_enable_interrupts into
dra7xx_pcie_enable_wrapper_interrupts and dra7xx_pcie_enable_msi_interrupts
so that wrapper interrupts and msi interrupts can be enabled independently.
This is in preparation for adding EP mode support to dra7xx driver since
EP mode doe
The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
in RC mode. However in EP mode, the host system is not able to access the
MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.
Acked-by: Tony Lindgren
On 23/03/17 12:57, Colin King wrote:
> From: Colin Ian King
>
> The call to v4ls_m2m_get_vq is only used to get the return value
> which is not being used, so it appears to be redundant and can
> be removed.
>
> Detected with CoverityScan, CID#1420674 ("Useless call")
>
> Signed-off-by: Colin I
Add device tree binding documentation for pci dra7xx EP mode.
Acked-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 37 +++-
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/b
Add a userspace tool to invoke the ioctls exposed by the
PCI endpoint test driver to perform various PCI tests.
Signed-off-by: Kishon Vijay Abraham I
---
tools/pci/pcitest.c | 186
1 file changed, 186 insertions(+)
create mode 100644 tools/pc
Add Documentation for pci-endpoint-test driver.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/misc-devices/pci-endpoint-test.txt | 35
1 file changed, 35 insertions(+)
create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
diff --git a/Documentat
Hi Linus,
On lun., mars 27 2017, Linus Walleij wrote:
> On Tue, Mar 21, 2017 at 7:28 PM, Gregory CLEMENT
> wrote:
>
> You should add something to your Kconfig including:
>
> select GPIOLIB
> select OF_GPIO
>
> or so... or depends on. You certainly need them.
I missed it I will do it in v4.
According to the PCI local bus specifications (Revision 3.0, 3.2.5),
I/O Address space transactions are non-posted. On architectures where
I/O space is implemented through a chunk of memory mapped space mapped
to PCI address space (ie IA64/ARM/ARM64) the memory mapping for the
region backing I/O Ad
pci_remap_iospace() is marked as a weak symbol even though
no architecture is currently overriding it; given that its
implementation internals have already code paths that are
arch specific (ie PCI_IOBASE and ioremap_page_range() attributes)
there is no need to leave the weak symbol in the kernel s
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
On Mon, Mar 27, 2017 at 10:30:44AM +0200, Peter Rosin wrote:
> Hi Greg,
>
> Today seemed like a good day to send you the pull request for the new mux
> controller subsystem. I hope the details are ok. If not, let me know and
> I'll try to rework it. I also included some text for the merge commit,
The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and
Posting") mandate non-posted configuration transactions. As further
highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering
Considerations for the Enhanced Configuration Access Mechanism"),
through ECAM and ECAM-derivative con
On Mon, Mar 27 2017, Christoph Hellwig wrote:
> I don't really like the flag at all. I'd much prefer a __bio_endio
> with a 'bool trace' flag. Also please remove the manual tracing in
> dm.ċ. Once that is done I suspect we can also remove the
> block_bio_complete export.
Can you say why you do
This patch series[1] is a v2 of a previous version:
v1 -> v2:
- Changed pci_remap_cfgspace() to more generic ioremap_nopost()
interface
- Added pgprot_nonposted
- Fixed build errors on arches not relying on asm-generic headers
- Added PCI versatile host co
Current ECAM kernel implementation uses ioremap() to map the ECAM
configuration space memory region; this is not safe in that on some
architectures the ioremap interface provides mappings that allow posted
write transactions. This, as highlighted in the PCIe specifications
(4.0 - Rev0.3, "Ordering
According to the PCI local bus specifications (Revision 3.0, 3.2.5),
I/O Address space transactions are non-posted. On architectures where
I/O space is implemented through a chunk of memory mapped space mapped
to PCI address space (ie IA64/ARM/ARM64) the memory mapping for the
region backing I/O Ad
The introduction of the ioremap_nopost() interface allows
kernel drivers to map memory through a dedicated kernel
interface providing non-posted writes semantics.
Introduce two new functions in the Devres kernel layer and Devres
documentation:
- devm_ioremap_nopost()
- devm_ioremap_nopost_resourc
Update device tree binding documentation of TI's dra7xx PCI
controller to include property for enabling unaligned mem access.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetr
Hi Masahiro,
Le 27/03/2017 à 07:27, Masahiro Yamada a écrit :
> Hi Nicolas,
>
>
> 2017-03-14 21:54 GMT+09:00 Nicolas Dichtel :
>> diff --git a/arch/cris/include/uapi/asm/Kbuild
>> b/arch/cris/include/uapi/asm/Kbuild
>> index d0c5471856e0..b15bf6bc0e94 100644
>> --- a/arch/cris/include/uapi/asm/
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering
and Posting") defines rules for PCI configuration space transactions
ordering and posting, that state that configuration writes
are non-posted transactions.
This rule is reinforced by the ARM v8 architecture reference manual
(issue A
757(cmpxchg)
10726413(try_cmpxchg)
10730701(try_cmpxchg + likely)
10730509(try_cmpxchg + if)
10730445(try_cmpxchg-linus)
GCC-7 (20170327):
10709514(cmpxchg)
10704266(try_cmpxchg)
10704458(try_cmpxchg + likely)
10704266(try_cmpxchg + if)
10704
fixing some coding style issues in goldfish audio driver
>From 8368d1b6404d63da7d502f6cd2ce6b50c7ffa9b9 Mon Sep 17 00:00:00 2001
From: Aviya Erenfeld
Date: Tue, 21 Mar 2017 00:07:19 +0200
Subject: [PATCH] staging: goldfish: Fix coding style issues
Fix the coding style issues that raised by check
Add endpoint mode support to designware driver. This uses the
EP Core layer introduced recently to add endpoint mode support.
*Any* function driver can now use this designware device
in order to achieve the EP functionality.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig
Add PCI endpoint test driver that can verify base address
register, legacy interrupt/MSI interrupt and read/write/copy
buffers between host and device. The corresponding pci-epf-test
function driver should be used on the EP side.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/Kconfig
Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX | 2 ++
.../PCI/endpoint/function/binding/pci-test.txt | 17 ++
According to errata i870, access to the PCIe slave port
that are not 32-bit aligned will result in incorrect mapping
to TLP Address and Byte enable fields.
Accessing non 32-bit aligned data causes incorrect data in the target
buffer if memcpy is used. Implement the workaround for this
errata here.
Add Documentation to help users use endpoint library to enable endpoint
mode in the PCI controller and add new PCI endpoint functions.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/00-INDEX | 2 +
Documentation/PCI/endpoint/pci-endpoint.txt | 215
Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to
bind the EP function with EP controller.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/Kconfig | 9 +
drivers/pci/endpoint/Makefile | 1 +
Introduce a new EP core layer in order to support endpoint functions
in linux kernel. This comprises of EPC library
(Endpoint Controller Library) and EPF library (Endpoint
Function Library). EPC library implements functions that is specific
to an endpoint controller and EPF library implements funct
The PCIe controller integrated in dra7xx SoCs is capable of operating
in endpoint mode. Add endpoint mode support to dra7xx driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig | 31 +-
drivers/pci/dwc/Makefile | 4 +-
drivers/pci/dwc/pci-dra7xx.c
On Mon, Mar 27, 2017 at 11:25 AM, kbuild test robot wrote:
> Hi Deepa,
>
> [auto build test WARNING on tip/perf/core]
> [also build test WARNING on v4.11-rc4 next-20170327]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
&g
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
With CONFIG_RESET_CONTROLLER=n we get the following link error in the
sunxi-ng clk driver:
drivers/built-in.o: In function `sunxi_ccu_probe':
mux-core.c:(.text+0x12fe68): undefined reference to 'reset_controller_register'
mux-core.c:(.text+0x12fe68): relocation truncated to fit: R_AARCH64_CALL26
The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering
and Posting") define rules for PCI configuration space transactions
ordering and posting, that state that configuration writes have to
be non-posted transactions.
Current ioremap interface on ARM provides mapping functions that
provi
PCI configuration space should be mapped with a memory region type that
generate on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Piera
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use correct memory mapping attributes to map config space
regions to enforce configuration space non-posted writes behaviour.
Signed-off-by: Lore
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
On Fri, Mar 24, 2017 at 9:59 PM, Michael S. Tsirkin wrote:
> On Fri, Mar 24, 2017 at 09:40:07PM +0100, Arnd Bergmann wrote:
>> On Fri, Mar 24, 2017 at 9:11 PM, Ladi Prosek wrote:
>> > On Fri, Mar 24, 2017 at 7:38 PM, David Hildenbrand
>> > wrote:
>> >> On 23.03.2017 16:17, Arnd Bergmann wrote:
From: Steve Twiss
Add binding information for DA9062 and DA9061 watchdog.
Example bindings for both DA9062 and DA9061 devices are added. For
the DA9061 device, a fallback compatible line is added as a valid
combination of compatible strings.
The original binding for DA9062 (only) used to reside
On Mon, Mar 27, 2017 at 12:53:21PM +0300, aviyae wrote:
> fixing some coding style issues in goldfish audio driver
>
> >From 8368d1b6404d63da7d502f6cd2ce6b50c7ffa9b9 Mon Sep 17 00:00:00 2001
> From: Aviya Erenfeld
> Date: Tue, 21 Mar 2017 00:07:19 +0200
> Subject: [PATCH] staging: goldfish: Fix
From: Steve Twiss
Device tree binding information for DA9062 and DA9061 thermal junction
temperature monitor.
Binding descriptions for the DA9061 and DA9062 thermal TJUNC supervisor
device driver, using a single THERMAL_TRIP_HOT trip-wire and allowing for
a configurable polling period for over-t
From: Steve Twiss
Extend existing DA9062 binding information to include the DA9061 PMIC for
MFD core and regulators.
Add a da9062-onkey link to the existing onkey binding file.
Add a da9062-thermal link to the new temperature monitoring binding file.
Delete the da9062-watchdog section and repl
From: Steve Twiss
Hi,
Dialog Semiconductor support would like to add to the MAINTAINERS search
terms. This update will allow us to follow files for device tree bindings
and source code relating to input onkey drivers, chip thermal monitoring
and watchdog timers.
Signed-off-by: Steve Twiss
---
From: Steve Twiss
MFD support for DA9061 is provided as part of the DA9062 device driver.
The registers header file adds two new chip variant IDs defined in DA9061
and DA9062 hardware. The core header file adds new software enumerations
for listing the valid DA9061 IRQs and a da9062_compatible_t
From: Steve Twiss
This patch set adds support for the Dialog DA9061 Power Management IC.
Support is made by altering the existing DA9062 device driver, where
appropriate.
In this patch set the following is provided:
[PATCH V5 1/8] Binding for watchdog
[PATCH V5 2/8] Binding for thermal supervis
From: Steve Twiss
Regulator support for the DA9061 is added into the DA9062 regulator driver.
The regulators for DA9061 differ from those of DA9062.
A new DA9061 enumeration list for the LDOs and Bucks supported by this
device is added. Regulator information added: the old regulator
information
From: Steve Twiss
Add junction temperature monitoring supervisor device driver, compatible
with the DA9062 and DA9061 PMICs. A MODULE_DEVICE_TABLE() macro is added.
If the PMIC's internal junction temperature rises above T_WARN (125 degC)
an interrupt is issued. This T_WARN level is defined as t
Hi Deepa,
[auto build test WARNING on tip/perf/core]
[also build test WARNING on v4.11-rc4 next-20170327]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Deepa-Dinamani/trace-Make-trace_hwlat
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
Hi Rob,
2017-03-20 22:52 GMT+01:00 Rob Herring :
> On Mon, Mar 13, 2017 at 04:06:38PM +0100, M'boumba Cedric Madianga wrote:
>> This patch adds documentation of device tree bindings for the STM32 MDMA
>> controller.
>>
>> Signed-off-by: M'boumba Cedric Madianga
>> Reviewed-by: Ludovic BARRE
>> -
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pier
While calculating the compensation of the humidity there are negative
values interpreted as unsigned because of unsigned variables used.
These values need to be casted to signed as indicated by the documentation
of the sensor.
Signed-off-by: Andreas Klinger
---
drivers/iio/pressure/bmp280-core.c
On 19 February 2017 01:40, Eduardo Valentin wrote:
Hi Eduardo,
My apologies in taking so long to reply.
There were *no* problems with implementing your requests. See below.
I will have sent these changes as PATCH V6.
https://lkml.org/lkml/2017/3/27/253
Regards,
Steve
> To: Steve Twiss
> Subjec
On Mon, 2017-03-27 at 11:46 +0200, Hans Verkuil wrote:
> On 23/03/17 12:57, Colin King wrote:
> > From: Colin Ian King
> >
> > The call to v4ls_m2m_get_vq is only used to get the return value
> > which is not being used, so it appears to be redundant and can
> > be removed.
> >
> > Detected with
Split discard_cmd_list to discard_{pend,wait}_list, so while sending/waiting
discard command, we can avoid traversing unneeded entries in original list.
Signed-off-by: Chao Yu
---
v2: remove unneeded judgment condition in issue_discard_thread.
fs/f2fs/f2fs.h| 3 ++-
fs/f2fs/segment.c | 44 +
Add maintainer for the newly introduced PCI EP framework.
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c265a5fe4848..3c1b947811e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9581,6 +9581,15 @
Don't use blk plug covering area where there won't be any IOs being issued.
Signed-off-by: Chao Yu
---
fs/f2fs/segment.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c
index c1a03b0857f9..57a81f9c8c14 100644
--- a/fs/f2fs/segment.c
In f2fs_submit_discard_endio, we will wake up waiter before setting
discard command states, so waiter may use incorrect states. Change
the order between complete() and states setting to fix this issue.
Signed-off-by: Chao Yu
---
fs/f2fs/segment.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On Tue, Mar 21, 2017 at 7:28 PM, Gregory CLEMENT
wrote:
> Document the device tree binding for the pin controllers found on the
> Armada 37xx SoCs.
>
> Update the binding documention of the xtal clk which is a subnode of this
> syscon node.
>
> Signed-off-by: Gregory CLEMENT
These look all righ
Remove unneeded parameter and simply change flow in
destroy_discard_cmd_control.
Signed-off-by: Chao Yu
---
fs/f2fs/segment.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c
index ff53423e35fb..c1a03b0857f9 100644
--- a/f
From: "Scariah, Thomas"
Added functions to support ethtool to print the phy statistics and error
information along with other ethtool statistics. This will help ethtool
information to know the error is from physical layer or MAC layer.
This is an enahancement for ethtool to accommodate phy st
On Saturday 25 March 2017 08:20 PM, Icenowy Zheng wrote:
> Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is
> a MUSB controller, which can work in peripheral mode, but works badly in
> host mode (several hardware will fail on the MUSB controller, even connect
> one MUSB cont
On Sat, Mar 25, 2017 at 02:05:47AM -0300, Javier Martinez Canillas wrote:
> On 03/24/2017 05:38 PM, Brian Norris wrote:
> >
> >> + if (ops->get_voltage || ops->get_voltage_sel)
> It's valid to have a .get_voltage_sel callback without a .list_voltage?
No.
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