On 2/28/2018 4:28 AM, Borislav Petkov wrote:
> From: Borislav Petkov
>
> ... so that any newer version can land in the cache and can later be
> fished out by the application functions. Do that before grabbing the
> hotplug lock.
>
> Signed-off-by: Borislav Petkov
> ---
> arch/x86/kernel/cpu/mi
On 2/28/2018 4:28 AM, Borislav Petkov wrote:
> From: Ashok Raj
>
> Original idea by Ashok, completely rewritten by Borislav.
>
> Before you read any further: the early loading method is still the
> preferred one and you should always do that. The following patch is
> improving the late loading m
On 03/05/2018 02:59 AM, Mark Rutland wrote:
On Fri, Mar 02, 2018 at 11:19:56AM -0800, Saravana Kannan wrote:
On 03/02/2018 02:42 AM, Mark Rutland wrote:
It's important to note that the DSU PMU's event_init() ensures events
are affine to a single CPU, and the perf core code serializes operations
On Tue, Feb 13, 2018 at 08:25:57AM -0600, Gustavo A. R. Silva wrote:
> Return statements in functions returning bool should use
> true/false instead of 1/0.
>
> This issue was detected with the help of Coccinelle.
This one didn't get in time for the previous merge window.
Now applied, thanks.
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva
---
net/ipv6/ndisc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c
index 0a19c
On 2/28/2018 4:28 AM, Borislav Petkov wrote:
> From: Borislav Petkov
>
> Hi,
>
> here are a bunch of patches which improve microcode late loading.
>
> Before you read any further: the early loading method is still the
> preferred one and you should always do that. This patchset is improving
> t
Hi,
This patchset includes cleanups, improvements, and bug fixes for
Rockchip DRM driver and PSR support.
This new version is the same as before but rebased on top of
drm-misc-next plus the Marek patches that fixes Chromebook2 Peach-Pit [1]
and the latest series of Rockchip rk3399 eDP support [2]
On Tue, Feb 27, 2018 at 08:11:29AM +0100, Andrzej Hajda wrote:
> These bindings allow to describe most known standard USB connectors
> and it should be possible to extend it if necessary.
> USB connectors, beside USB can be used to route other protocols,
> for example UART, Audio, MHL. In such case
On Tue, Feb 27, 2018 at 07:37:02PM +0530, Sricharan R wrote:
> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
> that has KRAIT processors the voltage/current value of each OPP
> varies based on the silicon variant in use.
> operating-points-v2-krait-cpu specifies the phandle to nvmem
On 03/05/2018 04:10 PM, Pablo Neira Ayuso wrote:
On Tue, Feb 13, 2018 at 08:25:57AM -0600, Gustavo A. R. Silva wrote:
Return statements in functions returning bool should use
true/false instead of 1/0.
This issue was detected with the help of Coccinelle.
This one didn't get in time for the p
Hi,
This patchset includes cleanups, improvements, and bug fixes for
Rockchip DRM driver and PSR support.
This new version is the same as before but rebased on top of
drm-misc-next plus the Marek patches that fixes Chromebook2 Peach-Pit [1]
and the latest series of Rockchip rk3399 eDP support [2]
From: zain wang
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
---
drivers/gpu/drm/bridge/analogix/analogix
From: Lin Huang
There was a 1ms delay to detect the hpd signal, which is too short to
detect a short pulse. This patch extends this delay to 100ms.
Cc: Stéphane Marchesin
Cc: 征增 王
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Si
From: zain wang
There are some different bits between Rockchip and Exynos in register
"AUX_PD". This patch fixes the incorrect operations about it.
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by:
From: zain wang
Panel would reset its setting when it powers down. It would forget the last
succeeded link training setting. So we can't use the last successful link
training setting to do fast link training. Let's reset fast_train_enable in
analogix_dp_bridge_disable();
Cc: Stéphane Marchesin
From: zain wang
If we failed disable psr, it would hang the display until next psr
cycle coming. So we should restore psr->state when it failed.
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: En
From: zain wang
The STRM_VALID bit in register ANALOGIX_DP_SYS_CTL_3 may be unstable,
so we may hit the error log "Timeout of video streamclk ok" since
checked this unstable bit.
In fact, we can go continue and the streamclk is ok if we wait enough time,
it does no effect on display.
Let's change
From: Douglas Anderson
The comments in analogix_dp_init_aux() claim that we're disabling aux
channel retries, but then right below it for Rockchip it sets them to
3. If we actually need 3 retries for Rockchip then we could adjust
the comment, but it seems more likely that we want the same retry
From: Mark Yao
Some encoder have a crc verification check, crc check fail if
input and output data is not equal.
That means encoder input and output need use same color depth,
vop can output 10bit data to encoder, but some panel only support
8bit depth, that would make crc check die.
So pre dit
From: Lin Huang
We need to check the dpcd write/read return value to see whether the
write/read was successful
Cc: Kristian H. Kristensen
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: A
From: zain wang
It's too early to detect fast link training, if other step after it
failed, we will set fast_link flag to 1, and retry set_bridge again. In
this case we will power down and power up panel power supply, and we
will do fast link training since we have set fast_link flag to 1. In
fac
From: "Kristian H. Kristensen"
To improve PSR exit latency, we speculatively start exiting when we
receive input events. Occasionally, this may lead to false positives,
but most of the time we get a head start on coming out of PSR. Depending
on how userspace takes to produce a new frame in respon
From: Tomasz Figa
Driver callbacks, such as system suspend or resume can be called any
time, specifically they can be called before the component bind
callback. Let's use dp->adp pointer as a safeguard and skip calling
Analogix entry points if it is an ERR_PTR().
Signed-off-by: Tomasz Figa
Sign
From: Douglas Anderson
Some of the platform-specific stuff in rockchip_dp_poweron() needs to
happen before the generic code. Some needs to happen after. Let's
split the callback in two.
Specifically we can't start doing PSR work until _after_ the whole
controller is up, so don't set the enable
On Mon, Mar 05, 2018 at 02:10:59PM -0500, kan.li...@linux.intel.com wrote:
SNIP
> diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c
> index e3921ed..403c5e6 100644
> --- a/tools/perf/util/mmap.c
> +++ b/tools/perf/util/mmap.c
> @@ -235,16 +235,13 @@ static int overwrite_rb_find_range(v
From: Douglas Anderson
The code in analogix_dp_transfer() that was supposed to print out:
AUX CH error happened
Was actually dead code. That's because the previous check (whether
the interrupt status indicated any errors) would have hit for all
errors anyway.
Let's combine the two error check
From: Douglas Anderson
The current user of the analogix power_off is "analogix_dp-rockchip".
That driver does this:
- deactivate PSR
- turn off a clock
Both of these things (especially deactive PSR) should be done before
we turn the PHY power off and turn off analog power. Let's move the
callba
From: zain wang
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
R
From: zain wang
Register ANALOGIX_DP_FUNC_EN_1(offset 0x18), Rockchip is different to
Exynos:
on Exynos edp phy,
BIT 7 MASTER_VID_FUNC_EN_N
BIT 6 reserved
BIT 5 SLAVE_VID_FUNC_EN_N
on Rockchip edp phy,
BIT 7 reserved
BIT 6 RK_VID_CAP_FUNC_EN_N
B
From: zain wang
Enhanced mode is required by the eDP 1.2 specification, and not doing it
early could result in a period of time where we have a link transmitting
idle packets without it. Since there is no reason to disable it, we just
enable it at the beginning of link training and then keep it o
From: Tomasz Figa
If we change the state first and reschedule later, we might have the
work executed according to previous scheduled time and end up with PSR
re-enabled instantly. Let's cancel the work before changing the state.
While at it, consolidate psr_disable_handler() to just call
rockchi
From: Lin Huang
AUX errors are caused by many different reasons. We may not know what
happened in aux channel on failure, so let's reset aux channel if some
errors occurred.
Cc: 征增 王
Cc: Douglas Anderson
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Review
From: Lin Huang
When panel is shut down, we should make sure edp can be disabled to avoid
undefined behavior.
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Bal
From: Tomasz Figa
Currently PSR flush is triggered from CRTC's .atomic_begin() callback,
which is executed after modeset disables and enables and before plane
updates are committed. Since PSR flush and re-enable can be triggered
asynchronously by external sources (input event, delayed work), it c
From: Tomasz Figa
It looks like the driver subsystem detaches devices from power domains
at shutdown without consent of the drivers. This means that we might have
our power domain turned off behind our back and the only way to avoid
problems is to stop doing any hardware programming at some point
On Thu, Mar 01, 2018 at 12:13:10PM -0700, Logan Gunthorpe wrote:
>
>
> On 01/03/18 11:02 AM, Bjorn Helgaas wrote:
> > > void pci_enable_acs(struct pci_dev *dev)
> > > {
> > > + if (pci_p2pdma_disable_acs(dev))
> > > + return;
> >
> > This doesn't read naturally to me. I do see that
From: Tomasz Figa
The first time after we call rockchip_drm_do_flush() after
rockchip_drm_psr_register(), we go from PSR_DISABLE to PSR_FLUSH. The
difference between PSR_DISABLE and PSR_FLUSH is whether or not we have a
delayed work pending - PSR is off in either state. However
psr_set_state() o
From: Tomasz Figa
It is not used anymore after last changes and it was not even correct to
begin with as it assumed a 1:1 relation between a CRTC and encoder,
while in fact a CRTC can be attached to multiple encoders.
Signed-off-by: Tomasz Figa
Signed-off-by: Thierry Escande
Signed-off-by: Enr
From: Tomasz Figa
Currently both rockchip_drm_psr_activate() and _deactivate() only set the
boolean "active" flag without actually making sure that hardware state
complies with it.
Since we are going to extend the usage of this API to properly lock PSR
for the duration of atomic commits, we chan
On Tue, Feb 27, 2018 at 05:51:27PM -0500, Matt Porter wrote:
> DeviceTree binding for the tda7419 audio processor.
>
> Signed-off-by: Matt Porter
> ---
> Documentation/devicetree/bindings/sound/tda7419.txt | 15 +++
> 1 file changed, 15 insertions(+)
> create mode 100644 Documentati
From: zain wang
When we enable bridge failed, we have to retry it, otherwise we would get
the abnormal display.
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i Serra
---
dri
From: zain wang
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker
must first detect that the HPD signal is asserted high by the Downstream
Device before establishing a link with it.
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: T
From: Lin Huang
We should check AUX_EN bit to confirm the AUX CH operation is completed.
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
---
drivers/gpu/drm/bridge/analo
From: zain wang
We currently wait for the panel to mirror our intended PSR state
before continuing on both PSR enter and PSR exit. This is really
only important to do when we're entering PSR, since we want to
be sure the last frame we pushed is being served from the panel's
internal fb before shu
From: zain wang
Add a lock to vop to avoid disabling the crtc while waiting for a line
flag while enabling psr. If we disable in the middle of waiting for the
line flag, we'll end up timing out or worse.
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-o
From: Lin Huang
We need to enable video before analogix_dp_is_video_stream_on(), so
we can get the right video stream status.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Bal
From: Sean Paul
Now that the spinlocks and timers are gone, we can remove the psr
worker located in rockchip's analogix driver and do the enable/disable
directly. This should simplify the code and remove races on disable.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Sean Paul
Signed-off-by:
From: zain wang
We would meet a short black screen when exit PSR with the full link
training, In this case, we should use fast link train instead of full
link training.
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
---
From: Yakir Yang
Make sure the request PSR state takes effect in analogix_dp_send_psr_spd()
function, or print the sink PSR error state if we failed to apply the
requested PSR setting.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Yakir Yang
[seanpaul changed timeout loop to a readx poll]
Si
From: zain wang
There is a race between AUX CH bring-up and enabling bridge which will
cause link training to fail. To avoid hitting it, don't change psr state
while enabling the bridge.
Cc: Tomeu Vizoso
Cc: Sean Paul
Signed-off-by: zain wang
Signed-off-by: Caesar Wang
[seanpaul fixed up the
From: zain wang
There's a race between when bridge_disable and when vop_crtc_disable
are called. If the flush timer triggers a new psr work between these,
we will operate eDP without power shutdowned by bridge_disable. In this
case, moving activate/deactivate to enable/disable bridge to avoid it.
From: Sean Paul
Instead of using timer and spinlocks, use delayed_work and
mutexes for rockchip psr. This allows us to make blocking
calls when enabling/disabling psr (which is sort of important
given we're talking over dpcd to the display).
Cc: Caesar Wang
Cc: 征增 王
Cc: Stéphane Marchesin
Sig
On Tue, Feb 27, 2018 at 03:24:25PM -0800, Jolly Shah wrote:
> Add documentation to describe Xilinx ZynqMP power management
> bindings.
>
> Signed-off-by: Jolly Shah
> Signed-off-by: Rajan Vaja
> ---
> .../bindings/soc/xilinx/xlnx,zynqmp-power.txt | 28
> ++
> 1 file ch
ctxid_pid and vmid_val in config are of type u64. When an integer
0xFF is being left shifted more than 32 bits, the behavior is
undefined. The fix is to specify 0xFF as an unsigned long.
Detected by Coverity scan: CID 37650, 37651 (Bad bit shift operation)
Signed-off-by: Bo Yan
---
drivers/hwtr
On Mon, Mar 05, 2018 at 03:11:36PM +0800, Du, Changbin wrote:
SNIP
> > > on the other hand it's simple enough and looks
> > > like generic solution would be more tricky
> >
> > What about adding perf_sched__process_comm() to set it in the
> > thread::priv?
> >
> I can be done, then thread->comm_
On Thu, Nov 23, 2017 at 10:49:55PM +0100, Vasyl Gomonovych wrote:
> Add the missing iounmap() before put_device and
> return from txx9_sramc_init().
>
> Signed-off-by: Vasyl Gomonovych
> ---
> arch/mips/txx9/generic/setup.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/mips/tx
On Tue, Feb 27, 2018 at 03:55:49PM -0800, Jolly Shah wrote:
> Add documentation to describe ZynqMP power domain bindings.
>
> Signed-off-by: Jolly Shah
> Signed-off-by: Rajan Vaja
> ---
> .../devicetree/bindings/power/zynqmp-genpd.txt | 46
> ++
> 1 file changed, 46 ins
On 02/20/2018 06:56 AM, Andy Shevchenko wrote:
On Mon, Feb 19, 2018 at 11:57 PM, David Lechner wrote:
This fixes pcs_request_gpio() in the pinctrl-single driver when
bits_per_mux != 0. It appears this was overlooked when the multiple
pins per register feature was added.
Fixes: 4e7e8017a80e ("p
On Mon, Mar 05, 2018 at 04:05:22PM -0600, Brandon Streiff wrote:
> There are two compatibility strings for mv88e6xxx, but it isn't clear
> from the documentation why only those two exist when the mv88e6xxx driver
> supports more than the 6085 and 6190. Briefly describe how the compatible
> property
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva
---
net/tipc/bcast.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/tipc/bcast.c b/net/tipc/bcast.c
index 37892
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
We are going to want to be able use different FPGA managers with this
framework. The different manager may be part of a different FME in
fabric or it may be a hardware FPGA manager. Fortunately, at this
point now the changes, noted below,
Hi Jarrko,
On Mon, 2018-03-05 at 18:56 +0200, Jarkko Sakkinen wrote:
> In order to make struct tpm_buf the first class object for constructing TPM
> commands, migrate tpm2_probe() to use it.
>
> Signed-off-by: Jarkko Sakkinen
With this patch, the Pi doesn't find the TPM. I'm seeing the
followi
Hi,
This enables k10temp for the new AMD Ryzen APUs w/ Vega Mobile Gfx.
Tested on Ryzen 5 2500U, the temperature looked plausible.
Signed-off-by: René Rebe
PS: 1st RFC - might get white-space damaged, will resend when ACKed.
Sorry my Xemacs/Mew broke.
--- linux-4.15/drivers/hwmon/k10temp.c.v
On Wed, Feb 28, 2018 at 01:15:25AM +0100, Pierre Bourdon wrote:
> Signed-off-by: Pierre Bourdon
> ---
> .../devicetree/bindings/iio/light/bh1730.txt | 15 +++
> 1 file changed, 15 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/light/bh1730.txt
Reviewed
On 03/05/2018 02:31 PM, Dave Hansen wrote:
On 03/05/2018 01:14 PM, Khalid Aziz wrote:
Are you suggesting that vma returned by find_vma() could be split or
merged underneath me if I do not hold mmap_sem and thus make the flag
check invalid? If so, that is a good point.
This part does make me th
On 05/03/18 03:28 PM, Bjorn Helgaas wrote:
If you put the #ifdef right here, then it's easier to read because we
can see that "oh, this is a special and uncommon case that I can
probably ignore".
Makes sense. I'll do that.
Thanks,
Logan
On Mon, Mar 05, 2018 at 11:38:24PM +0100, René Rebe wrote:
> Hi,
>
> This enables k10temp for the new AMD Ryzen APUs w/ Vega Mobile Gfx.
> Tested on Ryzen 5 2500U, the temperature looked plausible.
>
> Signed-off-by: René Rebe
>
> PS: 1st RFC - might get white-space damaged, will resend when
> On Mon, Mar 05, 2018 at 09:21:37PM +, Winkler, Tomas wrote:
> > > On Mon, Mar 05, 2018 at 10:20:12PM +0200, Tomas Winkler wrote:
> > > > Make the tpm Makefile a bit more in order by putting objects in
> > > > one column and group together tpm2 modules
> > > >
> > > > Prefer tpm-objs += inste
On Mon, Mar 05, 2018 at 02:02:40PM -0800, Tim Harvey wrote:
> The Gateworks System Controller has a hwmon sub-component that exposes
> up to 16 ADC's, some of which are temperature sensors, others which are
> voltage inputs. The ADC configuration (register mapping and name) is
> configured via devi
Hi Mark and Maciej,
Looks like with next-20180305 there's a regulator regression
where mmc0 won't show any cards or produces errors:
mmcblk0: error -110 requesting status
mmc1: new high speed SDIO card at address 0001
mmcblk0: error -110 requesting status
mmcblk0: recov
On Mon 26 Feb 09:58 PST 2018, Lina Iyer wrote:
> From: Mahesh Sivasubramanian
>
> Command DB provides information on shared resources like clocks,
> regulators etc., probed at boot by the remote subsytem and made
> available in shared memory.
>
> Cc: devicet...@vger.kernel.org
> Signed-off-by:
Hi,
On Mon, Mar 05, 2018 at 11:37:54PM +0100, Jiri Olsa wrote:
> On Mon, Mar 05, 2018 at 03:11:36PM +0800, Du, Changbin wrote:
>
> SNIP
>
> > > > on the other hand it's simple enough and looks
> > > > like generic solution would be more tricky
> > >
> > > What about adding perf_sched__process_c
On Sun, Mar 04, 2018 at 08:44:26PM +0100, Michał Kępień wrote:
> > On Wed, Feb 28, 2018 at 06:08:52PM +0200, Andy Shevchenko wrote:
> > > On Tue, Feb 27, 2018 at 11:15 PM, Micha?? K??pie??
> > > wrote:
> > > > Various functions exposed by the firmware through the FUNC interface
> > > > tend to us
On Mon, Mar 05, 2018 at 03:57:37PM -0600, Rob Herring wrote:
> On Mon, Feb 26, 2018 at 03:19:05PM -0800, Guenter Roeck wrote:
> > Since commit 4670d610d5923 ("PCI: Move OF-related PCI functions into
> > PCI core"), sparc:allmodconfig fails to build with the following error.
> >
> > pcie-cadence-ho
Matheus Castello writes:
> To keep driver up to date we add generic pinctrl binding support, which covers
> the features used in this driver and has additional node properties that this
> SoC has compatibility, so enabling future implementations of these properties
> without the need to create ne
Hi Tony,
On Mon, Mar 5, 2018 at 8:12 PM, Tony Lindgren wrote:
> Hi Mark and Maciej,
>
> Looks like with next-20180305 there's a regulator regression
> where mmc0 won't show any cards or produces errors:
>
> mmcblk0: error -110 requesting status
> mmc1: new high
Since commit 4670d610d5923 ("PCI: Move OF-related PCI functions into
PCI core"), sparc:allmodconfig fails to build with the following error.
pcie-cadence-host.c:(.text+0x4c4):
undefined reference to `of_irq_parse_and_map_pci'
pcie-cadence-host.c:(.text+0x4c8):
undefined reference t
On Sun, 2018-03-04 at 23:28 +0100, Rafael J. Wysocki wrote:
>
> +++ linux-pm/kernel/sched/idle.c
> @@ -188,13 +188,14 @@ static void cpuidle_idle_call(void)
> } else {
> unsigned int duration_us;
>
> - tick_nohz_idle_go_idle(true);
> - rcu_idle_enter()
From: Sai Praneeth
Presently, efi_runtime_services() are executed by firmware in process
context. To execute efi_runtime_service(), kernel switches the page
directory from swapper_pgd to efi_pgd. However, efi_pgd doesn't have any
user space mappings. A potential issue could be, for instance, an N
On Mon, Mar 5, 2018 at 5:19 PM, Guenter Roeck wrote:
> On Mon, Mar 05, 2018 at 03:57:37PM -0600, Rob Herring wrote:
>> On Mon, Feb 26, 2018 at 03:19:05PM -0800, Guenter Roeck wrote:
>> > Since commit 4670d610d5923 ("PCI: Move OF-related PCI functions into
>> > PCI core"), sparc:allmodconfig fails
From: Sai Praneeth
When a process requests the kernel to execute any efi_runtime_service(),
the requested efi_runtime_service (represented as an identifier) and its
arguments are packed into a struct named efi_runtime_work and queued
onto work queue named efi_rts_wq. The caller then waits until t
From: Sai Praneeth
Invoking efi_runtime_services() through efi_workqueue means all accesses
to efi_runtime_services() should be done after efi_rts_wq has been
created. efi_delete_dummy_variable() calls set_variable(), hence
efi_delete_dummy_variable() should be called after efi_rts_wq has been
cr
From: Sai Praneeth
This patch set is an outcome of the discussion at
https://lkml.org/lkml/2017/8/21/607
Presently, efi_runtime_services() are executed by firmware in process
context. To execute efi_runtime_service(), kernel switches the page
directory from swapper_pgd to efi_pgd. However, efi_p
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva
---
drivers/infiniband/hw/bnxt_re/qplib_sp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/infiniband/hw/b
On Mon, 2018-03-05 at 10:31 +0100, Nestor Lopez Casado wrote:
> Hello Florent,
Hi Nestor,
> In my view, this driver may not be a good idea. The default behaviour
> of K290 is 'send multimedia keycodes' with the user given the choice
> to change that behaviour via vendor commands. Putting a driver
This is the equivalent of commit 001bf455d206 ("ARM: 8428/1: kgdb: Fix
registers on sleeping tasks") but for arm64. Nuff said.
...well, perhaps I could also add that task_pt_regs are userspace
registers and that's not what kgdb is supposed to be reporting. We're
supposed to be reporting kernel r
On Fri, 2018-02-23 at 19:24 +0100, Greg Kroah-Hartman wrote:
> 4.4-stable review patch. If anyone has any objections, please let me know.
>
> --
>
> From: Tony Lindgren
>
>
> [ Upstream commit d09220a887f70368afa79e850c95e74890c0a32d ]
[...]
This apparently breaks the build f
> -Original Message-
> From: Dexuan Cui
> Sent: Monday, March 5, 2018 11:22 AM
> To: bhelg...@google.com; linux-...@vger.kernel.org; KY Srinivasan
> ;
> Stephen Hemminger ; o...@aepfle.de;
> a...@canonical.com;
> jasow...@redhat.com
> Cc: linux-kernel@vger.kernel.org; driverdev-de...@linu
On Sat, Mar 03, 2018 at 11:59:55AM +, mario.limoncie...@dell.com wrote:
> > -Original Message-
> > From: Darren Hart [mailto:dvh...@infradead.org]
> > Sent: Friday, March 2, 2018 8:11 PM
> > To: Limonciello, Mario
> > Cc: Andy Shevchenko ; pali.ro...@gmail.com; LKML
> > ; platform-driv
Thanks Tom
On Mon, 2018-03-05 at 16:12 -0600, Tom Lendacky wrote:
> Borislav Petkov (3):
> > x86/microcode: Get rid of struct apply_microcode_ctx
> > x86/microcode/intel: Look into the patch cache first
> > x86/microcode: Request microcode on the BSP
> >
> > arch/x86/kernel/cpu/microcode/c
Hi Liviu,
Today's linux-next merge of the mali-dp tree got a conflict in:
drivers/gpu/drm/arm/malidp_planes.c
between commit:
81af63a4af82 ("drm: Don't pass clip to drm_atomic_helper_check_plane_state()")
from the drm-misc tree and commit:
4968211e7b8f ("drm: mali-dp: Uninitialized vari
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva
---
drivers/spi/spi-tegra20-slink.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-tegra20-slin
On 03/01/2018 05:19 AM, Alexei Starovoitov wrote:
> Introduce BPF_PROG_TYPE_RAW_TRACEPOINT bpf program type to access
> kernel internal arguments of the tracepoints in their raw form.
>
> From bpf program point of view the access to the arguments look like:
> struct bpf_raw_tracepoint_args {
>
On Sun, 4 Mar 2018 16:14:48 -0800 frowand.l...@gmail.com wrote:
> From: Frank Rowand
>
> When CONFIG_HAVE_MEMBLOCK is not set, an error version of
> memblock_alloc() exists. Add the matching memblock_free().
>
> Signed-off-by: Frank Rowand
> ---
>
> Andrew or Michal, can you please ack this
On 03/05/2018 02:00 AM, Salvador Fandiño wrote:
> On 02/21/2018 01:35 AM, Shuah Khan wrote:
>> Hi Salvador,
>>
>> On 01/30/2018 01:36 AM, Salvador Fandino wrote:
>>> Let me start by explaining the problem that have motivated me to write
>>> this patches:
>>>
>>> I work on the QVD, a virtual desktop
On Mon, Mar 5, 2018 at 3:23 PM, Sai Praneeth Prakhya
wrote:
> From: Sai Praneeth
>
> Presently, efi_runtime_services() are executed by firmware in process
> context. To execute efi_runtime_service(), kernel switches the page
> directory from swapper_pgd to efi_pgd. However, efi_pgd doesn't have a
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva
---
drivers/hid/hid-ntrig.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/hid/hid-ntrig.c b/d
On Sat, 3 Mar 2018 23:11:16 +0300 Alexey Dobriyan wrote:
> It is more natural to check for read-from-memory permissions in case of
> process_vm_readv() as PTRACE_MODE_ATTACH is equivalent to write
> permissions.
>
> ...
>
> --- a/mm/process_vm_access.c
> +++ b/mm/process_vm_access.c
> @@ -204,7
On Wed, Sep 27, 2017 at 08:45:26PM +0530, PrasannaKumar Muralidharan wrote:
> Add initial Ingenic X1000 SoC support. Provide minimum necessary
> information to boot kernel to an initramfs userspace.
>
> Signed-off-by: PrasannaKumar Muralidharan
> ---
> arch/mips/boot/dts/ingenic/x1000.dtsi | 93
On Mon, Mar 05, 2018 at 03:22:30PM -0800, Guenter Roeck wrote:
> Since commit 4670d610d5923 ("PCI: Move OF-related PCI functions into
> PCI core"), sparc:allmodconfig fails to build with the following error.
>
> pcie-cadence-host.c:(.text+0x4c4):
> undefined reference to `of_irq_parse_and_ma
501 - 600 of 1157 matches
Mail list logo
