On Wed, Mar 28, 2018 at 11:26 AM, Jia He wrote:
>
>
> On 3/28/2018 12:52 AM, Daniel Vacek Wrote:
>>
>> On Sat, Mar 24, 2018 at 1:24 PM, Jia He wrote:
>>>
>>> Commit b92df1de5d28 ("mm: page_alloc: skip over regions of invalid pfns
>>> where possible")
On 28/03/2018 12:20, David Rientjes wrote:
> On Wed, 28 Mar 2018, Laurent Dufour wrote:
>
@@ -2913,7 +2921,8 @@ int do_swap_page(struct vm_fault *vmf)
int exclusive = 0;
int ret = 0;
>>>
>>> Initialization is now unneeded.
>>
>> I'm sorry, what "initialization" are you
On Wed, Mar 28, 2018 at 12:37 PM, Rafael J. Wysocki wrote:
> On Wed, Mar 28, 2018 at 10:38 AM, Thomas Ilsche
> wrote:
>> On 2018-03-28 10:13, Rafael J. Wysocki wrote:
>>>
[cut]
>
> So I do
>
> $ for cpu in 0 1 2 3; do taskset -c $cpu sh -c 'while
On Fri, 23 Mar 2018, Enric Balletbo i Serra wrote:
> From: Gwendal Grignou
>
> This adds a sysfs attribute (/sys/class/chromeos/cros_ec/kb_wake_angle)
> used to set and get the keyboard wake lid angle. This attribute is
> present only if 2 accelerometers are controlled by
On Mon, 26 Mar 2018, Enric Balletbo i Serra wrote:
> Before this patch the enable signal was set before the PWM signal and
> vice-versa on power off. This sequence is wrong, at least, it is on
> the different panels datasheets that I checked, so I inverted the sequence
> to follow the specs.
>
>
On Tue, Mar 27, 2018 at 12:05:23PM -0400, Mathieu Desnoyers wrote:
> +#ifdef CONFIG_RSEQ
> + struct rseq __user *rseq;
> + u32 rseq_len;
> + u32 rseq_sig;
> + /*
> + * RmW on rseq_event_mask must be performed atomically
> + * with respect to preemption.
> + */
> +
Hi Rob,
On Mon, 26 Mar 2018 17:24:58 -0500
Rob Herring wrote:
> > +
> > +I3C devices
> > +===
> > +
> > +All I3C devices are supposed to support DAA (Dynamic Address Assignment),
> > and
> > +are thus discoverable. So, by default, I3C devices do not have to be
> >
On Wed, Mar 28, 2018 at 09:29:03AM +0200, Martijn Coenen wrote:
> This can't happen with normal nodes (because you can't get a ref
> to a node you own), but it could happen with the context manager;
> to make the behavior consistent with regular nodes, reject
> transactions into the context
Sehr geehrte Damen und Herren,
nach unserem Besuch Ihrer Homepage möchten wir Ihnen ein Angebot von Produkten
vorstellen, das Ihnen ermöglichen wird, den Verkauf Ihrer Produkte sowie
Dienstleistungen deutlich zu erhöhen.
Ich biete Ihnen den ganz neuen Adressenkatalog der Österreicher
Hi!
> > I can talk to the modem and start a call.
>
> Doing an AT query is the easy part :)
>
> > Then something like this (untested!) is certainly needed.
> > Probably more...
>
> I intentionally left this part out. The CPCAP codec has two DAIs
> and not 3+. The code you just added is a hack
On Tue, 13 Mar 2018, Richard Fitzgerald wrote:
> This adds the generic core support for Cirrus Logic "Madera" class codecs.
> These are complex audio codec SoCs with a variety of digital and analogue
> I/O, onboard audio processing and DSPs, and other features.
>
> These codecs are all based off
This includes the infrastructure to map the test into the guest and
run code from the test program inside a VM.
Signed-off-by: Ken Hofsass
Signed-off-by: Paolo Bonzini
---
tools/testing/selftests/kvm/Makefile | 3 +-
On 2018-03-22 18:40, Rafael J. Wysocki wrote:
From: Rafael J. Wysocki
Add a new pointer argument to cpuidle_select() and to the ->select
cpuidle governor callback to allow a boolean value indicating
whether or not the tick should be stopped before entering the
On Sat, Mar 24, 2018 at 05:24:38AM -0700, Jia He wrote:
>Commit b92df1de5d28 ("mm: page_alloc: skip over regions of invalid pfns
>where possible") optimized the loop in memmap_init_zone(). But it causes
>possible panic bug. So Daniel Vacek reverted it later.
>
Why this has a bug? Do you have some
This can't happen with normal nodes (because you can't get a ref
to a node you own), but it could happen with the context manager;
to make the behavior consistent with regular nodes, reject
transactions into the context manager by the process owning it.
Reported-by:
On Wed, Mar 28, 2018 at 02:24:30PM +0530, Aniruddha Banerjee wrote:
> The kernel documentation states that the locking of the irq-chip
> registers should be handled by the irq-chip driver. In the irq-gic,
> the accesses to the irqchip are seemingly not protected and multiple
> writes to SPIs from
Add support for Qualcomm serial slave devices. Probe the serial device,
retrieve its maximum speed and register a new hci uart device.
Signed-off-by: Thierry Escande
Reviewed-by: Andy Shevchenko
---
v6:
- Fix gpio name in error
Hi,
This patchset enables the Qualcomm BT controller QCA6174 node in the
device tree of the db820c board. This allows the bluetooth chipset to
be probed and registered against the hci layer by using the serdev
framework.
This patchset also contains the documentation for the compatible
string
On Tue, Mar 27, 2018 at 02:22:31PM -1000, Linus Torvalds wrote:
> On Tue, Mar 27, 2018 at 1:03 PM, Andrew Morton
> wrote:
> >
> > Why? What caused this padding? It happens in all configs?
>
> I assume what happens is that the anonymous struct ends up containing
>
Add binding document for serial bluetooth chips using Qualcomm protocol.
Signed-off-by: Thierry Escande
Reviewed-by: Rob Herring
---
v6:
- Remove chip specific pinctrl conf
- Move gpio and clocks into optional props section
v5:
- Rename
On Tue, Mar 27, 2018 at 03:21:20PM -0500, Dan Rue wrote:
> On Tue, Mar 27, 2018 at 06:27:04PM +0200, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.4.125 release.
> > There are 43 patches in this series, all will be posted as a response
> > to this one. If
On Wed, 28 Mar 2018, Thierry Reding wrote:
> On Wed, Feb 14, 2018 at 11:04:31AM +0100, Fabrice Gasnier wrote:
> > This series adds support for capture to stm32-pwm driver.
> > Capture is based on DMAs.
> > - First two patches are precursor patches
> > - Subsequent two patches add support for
On Tue, Mar 27, 2018 at 11:24:44AM -0700, Nathan Chancellor wrote:
> On Tue, Mar 27, 2018 at 06:27:04PM +0200, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.4.125 release.
> > There are 43 patches in this series, all will be posted as a response
> > to this
On 2018-03-28 09:34, Boris Brezillon wrote:
> Hi Peter,
>
> On Mon, 26 Mar 2018 09:35:02 +0200
> Peter Rosin wrote:
>
>> I have an sama5d31-based system with 64MB of memory and a 1920x1080
>> LVDS display wired for 16-bpp. When I enable legacy fbdev support,
>> the contiguous
On Tue, 20 Mar 2018, Enric Balletbo i Serra wrote:
> Check whether this EC instance has RTC host command support and instatiate
> the RTC driver as a subdevice in such case.
>
> Signed-off-by: Enric Balletbo i Serra
> Reviewed-by: Gwendal Grignou
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> Move the test for -fstack-protector(-strong) option to Kconfig.
>
> If the compiler does not support the option, the corresponding menu
> is automatically hidden. If _STRONG is not supported, it will fall
>
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> This will be useful to specify the required compiler version,
> like this:
>
> config FOO
> bool "Use Foo"
> depends on GCC_VERSION >= 408000
> help
> This feature requires
On Wed, Mar 28, 2018 at 1:29 PM, Greg KH wrote:
> I can mark it for stable, and then when you get the "this did not apply
> to this tree" email, you can send a backported patch to me so I know to
> take that one then.
Ack, thanks.
>
> thanks,
>
> greg k-h
On Wed, Mar 28, 2018 at 1:28 PM, Greg KH wrote:
> What is different from "v2" you sent before this? No change information
> from v1?
Sorry I messed this up - the first resend did not have "v2" in the
subject but did contain v2 change information, the second resend
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/Kconfig
Replaces a simple division by 2 to a right shiftrotation of 1 bit.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-host.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-host.c
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 16
Since a 64-bit BAR consists of a BAR pair, we need to write to both
BARs in the BAR pair to clear the BAR properly.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 4
1 file changed, 4 insertions(+)
diff --git
On Fri, Mar 23, 2018 at 11:40:42PM -0700, Quytelda Kahja wrote:
> The "_t" suffix is not needed for structure names in this driver,
> and is a reflection of an older typedef system that is no longer
> in place. Remove the "_t" suffix from every structure defined in this
> driver.
>
>
2018-03-28 20:22 GMT+09:00 Kees Cook :
> On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
> wrote:
>> This will be useful to describe the clang version dependency.
>>
>> Signed-off-by: Masahiro Yamada
>
> One
Since a 64-bit BAR consists of a BAR pair, and since there is no
BAR after BAR_5, BAR_5 cannot be 64-bits wide.
This sanity check is done in pci_epc_clear_bar(), so that we don't need
to do this sanity check in all epc->ops->clear_bar() implementations.
Signed-off-by: Niklas Cassel
Since a 64-bit BAR consists of a BAR pair, we need to write to both
BARs in the BAR pair to setup the BAR properly.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git
Hi Wei,
i'll add this fix, got this also from the kbuild test robot.
Thank you,
Yael
> -Original Message-
> From: Wei Yongjun
> Sent: Wednesday, 28 March 2018 14:12
> To: Alasdair Kergon ; Mike Snitzer ;
> yaeceh01
On Tue, Mar 27, 2018 at 08:03:07PM -0500, Shanker Donthineni wrote:
> On 03/27/2018 12:36 PM, Will Deacon wrote:
> > On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
> @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct
> vm_area_struct *vma,
>
On Tue, Mar 27, 2018 at 07:04:51PM +0200, Sebastian Ott wrote:
> What was wrong with the old behavior (let the caller decide - the same
> as with memory allocations)?
The old behavior on most (all?) mainstream architectures is that we
always zero the return value. On x86/i386 this goes back to
> +#ifdef CONFIG_INITRAMFS_GENERIC_UNLOAD
> +void free_initrd_mem(unsigned long start, unsigned long end)
> +{
> + free_reserved_area((void *)start, (void *)end, -1, "initrd");
> +}
> +#endif
Given how trivial this is and how many architectures can use it I'd
reverse the polarity and add a
I goofed up in making a patch file so enumeration is wrong.
I'll upload v7
On 3/28/2018 4:28 PM, Chintan Pandya wrote:
This series of patches are follow up work (and depends on)
Toshi Kani 's patches "fix memory leak/
panic in ioremap huge pages".
This series of patches are
On Wed, 28 Mar 2018 14:22:36 +0200
Daniel Vetter wrote:
> On Wed, Mar 28, 2018 at 09:34:54AM +0200, Boris Brezillon wrote:
> > Hi Peter,
> >
> > On Mon, 26 Mar 2018 09:35:02 +0200
> > Peter Rosin wrote:
> >
> > > I have an sama5d31-based system with 64MB of
This patch ("mm/vmalloc: Add interfaces to free unmapped
page table") adds following 2 interfaces to free the page
table in case we implement huge mapping.
pud_free_pmd_page() and pmd_free_pte_page()
Some architectures (like arm64) needs to do proper TLB
maintanance after updating pagetable
This series of patches are follow up work (and depends on)
Toshi Kani 's patches "fix memory leak/
panic in ioremap huge pages".
This series of patches are tested on 4.9 kernel with Cortex-A75
based SoC.
These patches can also go into '-stable' branch (if accepted)
for 4.6
Add an interface to invalidate intermediate page tables
from TLB for kernel.
Signed-off-by: Chintan Pandya
---
arch/arm64/include/asm/tlbflush.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h
On Sun, Mar 25, 2018 at 12:59:53PM +0200, Christian König wrote:
> Use this function to set an sg entry to point to device resources mapped
> using dma_map_resource(). The page pointer is set to NULL and only the DMA
> address, length and offset values are valid.
NAK. Please provide a higher
On Sun, Mar 25, 2018 at 12:59:54PM +0200, Christian König wrote:
> From: "wda...@nvidia.com"
>
> Add an interface to find the first device which is upstream of both
> devices.
Please work with Logan and base this on top of the outstanding peer
to peer patchset.
On Wed, Mar 28, 2018 at 02:29:46PM +0200, Peter Zijlstra wrote:
> > +static int rseq_get_rseq_cs(struct task_struct *t,
> > + unsigned long *start_ip,
> > + unsigned long *post_commit_offset,
> > + unsigned long *abort_ip,
> > +
I am leaving Axis, so this address will bounce in the not too
distant future.
Fortunately, I will still be working with the community.
Signed-off-by: Niklas Cassel
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
On Wed 28-03-18 01:34:24, Li,Rongqing wrote:
> OK, I see this commit, I will test the latest kernel
>
> commit 1c610d5f93c709df56787f50b3576704ac271826
> Author: Andrey Ryabinin
> Date: Thu Mar 22 16:17:42 2018 -0700
Yes, that should fix your memcg OOM
--
Michal
On Mon, Mar 26, 2018 at 02:57:35PM -0400, Steven Rostedt wrote:
> On Mon, 26 Mar 2018 10:53:13 +0200
> Andrea Parri wrote:
>
> > > --- a/kernel/smp.c
> > > +++ b/kernel/smp.c
> > > @@ -724,6 +724,30 @@ void kick_all_cpus_sync(void)
> > > }
> > >
+linux-ia64
On 3/27/2018 11:02 AM, Paul E. McKenney wrote:
> On Tue, Mar 27, 2018 at 02:11:27PM +0100, Will Deacon wrote:
>> The section of memory-barriers.txt that describes the dma_Xmb() barriers
>> has an incorrect example claiming that a wmb() is required after writing
>> to coherent memory
On Tue 27-03-18 21:52:17, Cyrill Gorcunov wrote:
> On Tue, Mar 27, 2018 at 02:38:11PM -0400, Yang Shi wrote:
> > > Why do we need to hold mmap_sem here and call find_vma, when only
> > > PR_SET_MM_ENV_END: is consuming it? I guess we can replace it wit the
> > > new lock and take the mmap_sem only
On Wed, Mar 28, 2018 at 10:57:07PM +0800, Jin Yao wrote:
SNIP
> +
> +static void library_status(void)
> +{
> + STATUS(HAVE_DWARF_SUPPORT, dwarf);
> + STATUS(HAVE_DWARF_GETLOCATIONS, dwarf_getlocations);
> + STATUS(HAVE_GLIBC_SUPPORT, glibc);
> + STATUS(HAVE_GTK2_SUPPORT, gtk2);
>
Hi Niklas,
On 28/03/2018 12:50, Niklas Cassel wrote:
> Since a 64-bit BAR consists of a BAR pair, we need to write to both
> BARs in the BAR pair to setup the BAR properly.
>
> Signed-off-by: Niklas Cassel
> ---
> drivers/pci/dwc/pcie-designware-ep.c | 11 +--
>
Hi Niklas,
On 28/03/2018 12:50, Niklas Cassel wrote:
> Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar.
>
> This is needed so that epc->ops->clear_bar() can clear the BAR pair,
> if the BAR is 64-bits wide.
>
> This also makes it possible for pci_epc_clear_bar() to sanity
Hi Chintan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on v4.16-rc7]
[also build test WARNING on next-20180328]
[cannot apply to arm64/for-next/core tip/x86/core asm-generic/master]
[if your patch is applied to the wrong git tree, please drop us a note
On Tue, Mar 27, 2018 at 10:22 PM, Anson Huang wrote:
> The clock name should be ipg instead of igp.
>
> Signed-off-by: Anson Huang
> ---
> Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
On Tue 27-03-18 19:54:35, Luis R. Rodriguez wrote:
> On Tue, Mar 27, 2018 at 09:06:37AM +0200, Michal Hocko wrote:
> > So by no means the MM backports were reviewed by me. And considering how
> > hard
> > it is to get any review for MM patches in general I strongly suspect that
> > others didn't
On Wed, Mar 28, 2018 at 10:57:08PM +0800, Jin Yao wrote:
> We keep having bug reports that when users build perf on their own,
> but they don't install some needed libraries such as libelf,
> libbfd/libibery.
>
> The perf can build, but it is missing important functionality.
>
> This patch
On Thursday, March 22, 2018 03:13:32 PM Gustavo A. R. Silva wrote:
> Assign true or false to boolean variables instead of an integer value.
>
> This issue was detected with the help of Coccinelle.
>
> Signed-off-by: Gustavo A. R. Silva
Patch queued for 4.17, thanks.
On 03/27/2018 08:58 AM, Tyler Hicks wrote:
Hello Guenter
On 02/13/2018 04:36 PM, Guenter Roeck wrote:
Commit 88ae4ab9802e ("ecryptfs_lookup(): try either only encrypted or
plaintext name") was supposed to fix a situation where two files with
the same name and same inode could be created in
On 03/27/2018 09:27 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.4.125 release.
There are 43 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On Sunday, January 07, 2018 02:34:51 PM SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Sun, 7 Jan 2018 14:02:36 +0100
>
> * Return an error code without storing it in an intermediate variable.
>
> * Delete the label "error" and local variable "retval"
>
cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means
that a 64-bit BAR can be set-up, even when the flag
PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.
If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64,
so that the calling function can know what BAR width that was
If a 64-bit BAR was set-up, we need to skip a BAR,
since a 64-bit BAR consists of a BAR pair.
We need to check what BAR width the epc->ops->set_bar() specific
implementation actually did set-up, since some drivers, like the
Cadence EP controller, sometimes sets up a 64-bit BAR, even though
a
Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar.
This is needed so that epc->ops->clear_bar() can clear the BAR pair,
if the BAR is 64-bits wide.
This also makes it possible for pci_epc_clear_bar() to sanity check
the flags.
Signed-off-by: Niklas Cassel
Since a 64-bit BAR consists of a BAR pair, and since there is no
BAR after BAR_5, BAR_5 cannot be 64-bits wide.
This sanity check is done in pci_epc_set_bar(), so that we don't need
to do this sanity check in all epc->ops->set_bar() implementations.
Signed-off-by: Niklas Cassel
A 64-bit BAR consists of a BAR pair, where the second BAR has the
upper bits, so we cannot simply call pci_ioremap_bar() on every single
BAR index.
The second BAR in a BAR pair will not have the IORESOURCE_MEM resource
flag set. Only call ioremap on BARs that have the IORESOURCE_MEM
resource flag
Hi Gustavo,
On Wed, Mar 28, 2018 at 8:38 AM, Gustavo Pimentel
wrote:
> diff --git a/drivers/pci/dwc/pcie-designware-host.c
> b/drivers/pci/dwc/pcie-designware-host.c
> index 550fdbb..03e9b82 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++
Implement pud_free_pmd_page() and pmd_free_pte_page().
Implementation requires,
1) Clearing off the current pud/pmd entry
2) Invalidate TLB which could have previously
valid but not stale entry
3) Freeing of the un-used next level page tables
Signed-off-by: Chintan Pandya
This commit 15122ee2c515a ("arm64: Enforce BBM for huge
IO/VMAP mappings") is a temporary work-around until the
issues with CONFIG_HAVE_ARCH_HUGE_VMAP gets fixed.
Revert this change as we have fixes for the issue.
Signed-off-by: Chintan Pandya
---
arch/arm64/mm/mmu.c |
when pid is bigger than PID_MAX_DEFAULT, the comm of task
is <...>, it is better use pid_max to compare
Signed-off-by: Wang Yu
---
kernel/trace/trace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
mode change 100644 => 100755 kernel/trace/trace.c
diff --git
On 28/03/2018 10.28, Christoph Hellwig wrote:
I really don't want more lightnvm cruft in the core. We'll need
a proper abstraction.c
I agree, we should get that moving, and make a proper abstraction for
it. Also with respect to how an SMR interface in general is integrated
into NVMe.
The
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi Linus,
Please pull some more powerpc fixes for 4.16. Apologies if this is a bit
big at rc7, but they're all reasonably important fixes. None are
actually for new code, so they aren't indicative of 4.16 being in bad
shape from our point of view.
On Wed, Mar 28, 2018 at 07:10:12AM -0400, Stefan Berger wrote:
Good morning, I hope the day is starting out well for everyone.
> On 03/27/2018 07:01 PM, Eric W. Biederman wrote:
> >Stefan Berger writes:
> >
> >>From: Yuqiong Sun
> >>
> >>Add new
On Tue, Mar 27, 2018 at 8:15 AM, liwei (CM) wrote:
> Hi, Arnd
>
> At present our ufs module mainly has four clocks from the outside:
> hclk_ufs: main clock of ufs controller ,freq is 207.5MHz
> cfg_phy_clk: configuration clock of MPHY, freq is 51.875MHz
> ref_phy_clk:
Hi Fabio,
On 28/03/2018 13:05, Fabio Estevam wrote:
> Hi Gustavo,
>
> On Wed, Mar 28, 2018 at 8:38 AM, Gustavo Pimentel
> wrote:
>
>> diff --git a/drivers/pci/dwc/pcie-designware-host.c
>> b/drivers/pci/dwc/pcie-designware-host.c
>> index 550fdbb..03e9b82 100644
On 03/27/2018 07:13 PM, Davidlohr Bueso wrote:
> On Tue, 27 Mar 2018, Waiman Long wrote:
>
>> Add a new master LOCK_DEBUGGING Kconfig option to turn on all the lock
>> debugging options except the selftests and the torture tests.
>
> For what purpose?
>
> I'm not sure we want yet another config
During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information as a capability of
platform device.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 35 ++-
1
From: Krishna Konda
The PADs for SD card are dual-voltage that support 3v/1.8v. Those PADs
have a control signal (io_pad_pwr_switch/mode18 ) that indicates
whether the PAD works in 3v or 1.8v.
SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset
based
Hi Niklas,
On 28/03/2018 12:50, Niklas Cassel wrote:
> Add barno and flags to struct epf_bar.
> That way we can simplify epc->ops->set_bar()/pci_epc_set_bar()
> by passing a struct *epf_bar instead of a whole lot of arguments.
>
> This is needed so that epc->ops->set_bar() implementations can
>
Remove duplicated include.
Signed-off-by: Wei Yongjun
---
drivers/bus/fsl-mc/dpbp.c | 1 -
drivers/bus/fsl-mc/dpcon.c | 1 -
2 file changed, 2 deletion(-)
diff --git a/drivers/bus/fsl-mc/dpbp.c b/drivers/bus/fsl-mc/dpbp.c
index 0aeacc5..9a7faab 100644
---
> On 28/03/2018 12:51, Niklas Cassel wrote:
> cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means that a
> 64-bit BAR can be set-up, even when the flag
> PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.
> If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64, so
> that
On Sunday, January 07, 2018 12:56:45 PM SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Sun, 7 Jan 2018 11:33:59 +0100
>
> Replace an error code for the indication of a memory allocation failure
> in this function.
>
> Fixes:
Hi Joerg,
> -Original Message-
> From: Linuxarm [mailto:linuxarm-boun...@huawei.com] On Behalf Of
> Shameerali Kolothum Thodi
> Sent: Friday, March 23, 2018 8:57 AM
> To: Robin Murphy ; Alex Williamson
>
> Cc: k...@vger.kernel.org; Joerg
Hello!
The prototype patch shown below provides files required to allow herd7 to
evaluate C-language litmus tests for the multicopy-atomic TSO ordering
provided by s390. This patch should be viewed with great suspicion.
It does what I expect it to do on SB (with and without barriers),
IRIW
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> The plugin availability is checked in Kconfig, so all{yes,mod}config
> will not be bothered. Remove 'depends on !COMPILE_TEST'.
>
> Signed-off-by: Masahiro Yamada
> ---
>
>
If flag PCI_BASE_ADDRESS_SPACE_IO is set, also having any
PCI_BASE_ADDRESS_MEM_* bit set is invalid.
This sanity check is done in pci_epc_set_bar(), so that we don't need
to do this sanity check in all epc->ops->set_bar() implementations.
Signed-off-by: Niklas Cassel
---
On Wed, Mar 28, 2018 at 9:26 AM, Mathieu Malaterre wrote:
> On Tue, Mar 27, 2018 at 7:33 PM, LEROY Christophe
> wrote:
>> LEROY Christophe a écrit :
>>
>>
>>> Mathieu Malaterre a écrit :
>>>
Christophe,
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> As Documentation/kbuild/kconfig-language.txt notes, 'select' should be
> used with care - it forces a lower limit of another symbol, ignoring
> the dependency. In this case, KCOV can select GCC_PLUGINS even
Hi Stephen,
On Wed, Mar 28, 2018 at 04:00:34PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the kvm-arm tree got a conflict in:
>
> arch/arm64/kernel/cpu_errata.c
>
> between commit:
>
> c0cda3b8ee6b ("arm64: capabilities: Update prototype for enable call
Hi Abel,
On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa wrote:
> From: Dong Aisheng
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the
> clock
> is
Hi Aniruddha,
On 28/03/18 09:54, Aniruddha Banerjee wrote:
> The kernel documentation states that the locking of the irq-chip
> registers should be handled by the irq-chip driver. In the irq-gic,
> the accesses to the irqchip are seemingly not protected and multiple
> writes to SPIs from
Hi all,
The directory (not yet three years old although, I freely admit, I've
only recently become aware of it) provides arch. support matrices for
more than 40 generic kernel features that need per-arch. support:
This is a superb project! ;-) and not a simple one given that, to be
effective,
Hi Vadim,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on net-next/master]
[also build test WARNING on v4.16-rc7 next-20180328]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
On Tue, Mar 27, 2018 at 12:05:23PM -0400, Mathieu Desnoyers wrote:
> +static int rseq_update_cpu_id(struct task_struct *t)
> +{
> + uint32_t cpu_id = raw_smp_processor_id();
u32
> +
> + if (__put_user(cpu_id, >rseq->cpu_id_start))
> + return -EFAULT;
> + if
On Tue, Mar 27, 2018 at 09:13:32PM +0200, Thorsten Leemhuis wrote:
> On 26.03.2018 01:37, Linus Torvalds wrote:
> > […] Anyway. Go out and test. And let's hope next week is nice and calm and
> > I can release the final 4.16 next Sunday without any extra rc's.
> >
> >Linus
>
>
On Wed, Mar 21, 2018 at 02:13:33PM -0500, Yazen Ghannam wrote:
> From: Yazen Ghannam
>
> It's possible that a system can be used without any DRAM populated on
> one or more physical Dies on multi-die systems. Firmware will not
> enable DRAM ECC on Dies without DRAM. Users
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