From: Daniel Silsby
Simple cleanup, no changes to actual logic here.
Signed-off-by: Daniel Silsby
Tested-by: Mathieu Malaterre
---
drivers/dma/dma-jz4780.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
v2: No change
diff --git a/drivers/dma/dma-jz4780.c b/drivers/d
From: Daniel Silsby
Normally, we wouldn't set the channel transfer count register directly
when using descriptor-driven transfers. However, there is no harm in
doing so, and it allows jz4780_dma_desc_residue() to report the correct
residue of an ongoing transfer, no matter when it is called.
Sig
From: Daniel Silsby
This is the standard method provided by dmaengine header.
Signed-off-by: Daniel Silsby
Tested-by: Mathieu Malaterre
---
drivers/dma/dma-jz4780.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
v2: No change
diff --git a/drivers/dma/dma-jz4780.c b/drivers/
Hi,
This is the version 2 of my jz4780-dma driver update patchset.
Changelog:
- All documentation changes have been moved to one single patch [01/17].
- The new patch [02/17] enforces that we're probed from devicetree.
- The driver will not fail if only one memory resource has been supplied
The driver is now compatible with four SoCs: JZ4780, JZ4770, JZ4725B and
JZ4740.
Besides, it now expects the devicetree to supply a second memory
resource. This resource is mandatory on the newly supported SoCs.
For the JZ4780, new devicetree code must also provide it, although the
driver is still
The JZ4740 SoC has a single DMA core starring six DMA channels.
Signed-off-by: Paul Cercueil
Tested-by: Mathieu Malaterre
Reviewed-by: PrasannaKumar Muralidharan
---
drivers/dma/Kconfig | 2 +-
drivers/dma/dma-jz4780.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
v2: The doc
As part of the work to support various other Ingenic JZ47xx SoC versions,
which don't feature the same number of DMA channels per core, we now
deduce the number of DMA channels available from the devicetree
compatible string.
Signed-off-by: Paul Cercueil
Tested-by: Mathieu Malaterre
---
drivers
On Wed, Jul 18, 2018 at 01:22:19PM -0400, Rik van Riel wrote:
> > On Jul 18, 2018, at 12:00 PM, Peter Zijlstra wrote:
> > Also, I don't suppose you've looked at the paravirt instances of
> > flush_tlb_other() ? They don't elide the flushes because of lazy.
>
> Let me look at those now :)
> kv
Add the support of regulator to use it as VCC source.
Signed-off-by: Mylène Josserand
---
.../bindings/input/touchscreen/edt-ft5x06.txt | 1 +
drivers/input/touchscreen/edt-ft5x06.c | 29 ++
2 files changed, 30 insertions(+)
diff --git a/Documentation/devic
Hello everyone,
This is a V3 of the patch series that adds touchscreen support
(FocalTech EDT-FT5x06 Polytouch) for TBS A711 (Allwinner sun8i-a83t SoC).
Based on last master of linux-input tree.
Since I can't test the suspend/resume functions there is no updates in
this series about factory/norma
Tha A711 tablet has a FocalTech EDT-FT5x06 Polytouch touchscreen.
It is connected via I2C0. The reset line is PD5, the interrupt
line is PL7 and the VCC supply is the ldo_io0 regulator.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 16
1 file ch
On resume and suspend, set the value of wake and reset gpios
to be sure that we are in a know state after suspending/resuming.
Signed-off-by: Mylène Josserand
---
drivers/input/touchscreen/edt-ft5x06.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/input/touchscreen/ed
On Sat, 7 Jul 2018 05:37:22 +0200
Jann Horn wrote:
> The first checks in mtdchar_read() and mtdchar_write() attempt to limit
> `count` such that `*ppos + count <= mtd->size`. However, they ignore the
> possibility of `*ppos > mtd->size`, allowing the calculation of `count` to
> wrap around. `mtd
Hi Alex,
On Tue, Jul 17, 2018 at 8:52 PM, Alex Williamson
wrote:
> On Fri, 13 Jul 2018 10:26:17 +0530
> Srinath Mannam wrote:
>
>> By default all BARs map with VMA access permissions
>> as pgprot_noncached.
>>
>> In ARM64 pgprot_noncached is MT_DEVICE_nGnRnE which
>> is strongly ordered and allo
On 18 July 2018 at 20:13, Shakeel Butt wrote:
> On Wed, Jul 18, 2018 at 10:58 AM Bruce Merry wrote:
> Yes, if there is no memory pressure such memory can stay around.
>
> On your production machine, before deleting memory containers, you can
> try force_empty to reclaim such memory from them. See
> On Jul 18, 2018, at 2:23 PM, Peter Zijlstra wrote:
>
> On Wed, Jul 18, 2018 at 01:22:19PM -0400, Rik van Riel wrote:
>>> On Jul 18, 2018, at 12:00 PM, Peter Zijlstra wrote:
>
>>> Also, I don't suppose you've looked at the paravirt instances of
>>> flush_tlb_other() ? They don't elide the f
On 07/18/2018 09:56 AM, Pavel Machek wrote:
Hi!
I believe I meant "changing patterns from kernel in response to events
is probably overkill"... or something like that.
Anyway -- to clean up the confusion -- I'd like to see
echo pattern > trigger
echo "1 2 3 4 5 6 7 8" > somewhere
s/somewhe
* Nishanth Menon [180718 18:08]:
> On 16:26-20180626, Nishanth Menon wrote:
> > Hi,
> >
> > This is an minor update from V1 posted earlier:
> > https://marc.info/?l=linux-kernel&m=152943745424138&w=2
> >
> > The following series enables support for newest addition in TI's SoC
> > portfolio -
Paul,
On Wed, 18 Jul 2018, Paul Menzel wrote:
> On 07/18/18 17:39, Thomas Gleixner wrote:
> > Bah. Could you please enable GENERIC_IRQ_DEBUGFS and after a successful
> > boot up provide me the content of all files in /sys/kernel/debug/irq/ and
> > its subfolders?
>
> Sure, please find them attach
On Tue, Jul 17, 2018 at 5:28 PM Andrew Jeffery wrote:
>
> On Tue, 17 Jul 2018, at 14:26, Benjamin Herrenschmidt wrote:
> > On Mon, 2018-07-16 at 07:55 -0600, Rob Herring wrote:
> > > If that data is one set per SoC, then i'm not that concerned having
> > > platform-specific data in the driver. Tha
Hi Yixun,
On Wed, 18 Jul 2018 17:38:56 +0800
Yixun Lan wrote:
> >> +
> >> +#define NFC_REG_CMD 0x00
> >> +#define NFC_REG_CFG 0x04
> >> +#define NFC_REG_DADR 0x08
> >> +#define NFC_REG_IADR 0x0c
> >> +#define NFC_REG_BUF 0x10
>
On Fri, Jun 22, 2018 at 05:58:14AM -0400, Oza Pawandeep wrote:
> We are handling ERR_FATAL by resetting the Link in software,skipping the
> driver pci_error_handlers callbacks, removing the devices from the PCI
> subsystem, and re-enumerating, because of, no need to handle
> pci_channel_io_frozen c
On 07/18/2018 08:54 PM, Jacek Anaszewski wrote:
On 07/18/2018 09:56 AM, Pavel Machek wrote:
Hi!
I believe I meant "changing patterns from kernel in response to
events
is probably overkill"... or something like that.
Anyway -- to clean up the confusion -- I'd like to see
echo pattern > trig
On Mehlow Xeon-E workstation, ISH PCI device is enabled but without ISH
firmware. Here the ISH device PCI device id was reused for some non Linux
storage drivers. So this was not done for enabling ISH. But this has a
undesirable side effect for Linux.
Here the ISH driver will be loaded via PCI enu
On Wed, 2018-07-18 at 09:37 -0700, Paul E. McKenney wrote:
> On Wed, Jul 18, 2018 at 06:01:51PM +0200, David Woodhouse wrote:
> >
> > On Wed, 2018-07-18 at 08:36 -0700, Paul E. McKenney wrote:
> > >
> > > And I finally did get some near misses from an earlier commit, so we
> > > should consider
When enabling the lockdep mechanic and working with CPU-wide scenarios we
get the following console output:
[ 54.632093] ==
[ 54.638207] WARNING: possible circular locking dependency detected
[ 54.644322] 4.18.0-rc3-00042-g2d39e6356bb7-dirt
This is a v3 of Oza's patches [1]. It's available at [2] if you prefer
git.
v3 changes:
- Add pci_aer_clear_fatal_status() to clear ERR_FATAL bits, only called
from pcie_do_fatal_recovery(). Moved to first in series to avoid a
window where ERR_FATAL recovery only clears ERR_NONFATAL bi
From: Oza Pawandeep
aer_error_resume() clears all ERR_NONFATAL error status bits. This is
exactly what pci_cleanup_aer_uncorrect_error_status(), so use that instead
of duplicating the code.
Signed-off-by: Oza Pawandeep
[bhelgaas: split to separate patch]
Signed-off-by: Bjorn Helgaas
---
driv
From: Bjorn Helgaas
During recovery from fatal errors, we previously called
pci_cleanup_aer_uncorrect_error_status(), which cleared *all* uncorrectable
error status bits (both ERR_FATAL and ERR_NONFATAL).
Instead, call a new pci_aer_clear_fatal_status() that clears only the
ERR_FATAL bits (as in
From: Oza Pawandeep
pci_cleanup_aer_uncorrect_error_status() is called by driver .slot_reset()
methods when handling ERR_NONFATAL errors. Previously this cleared *all*
the bits, including ERR_FATAL bits.
Since we're only handling ERR_NONFATAL errors, clear only the ERR_NONFATAL
error status bit
From: Oza Pawandeep
broadcast_error_message() is only used for ERR_NONFATAL events, when the
state is always pci_channel_io_normal, so remove the unused alternate path.
Signed-off-by: Oza Pawandeep
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pcie/err.c | 11 +++---
From: Oza Pawandeep
Clear the device status bits while handling both ERR_FATAL and ERR_NONFATAL
cases.
Signed-off-by: Oza Pawandeep
[bhelgaas: rename to pci_aer_clear_device_status(), declare internal to PCI
core instead of exposing it everywhere]
Signed-off-by: Bjorn Helgaas
---
drivers/pci/
From: Oza Pawandeep
In case of correctable error, the Correctable Error Detected bit in the
Device Status register is set. Clear it after handling the error.
Signed-off-by: Oza Pawandeep
Signed-off-by: Bjorn Helgaas
---
drivers/pci/pcie/aer.c |1 +
1 file changed, 1 insertion(+)
diff --
From: Oza Pawandeep
The pci_error_handlers.slot_reset() callback is only used for non-bridge
devices (see broadcast_error_message()). Since portdrv only binds to
bridges, we don't need pcie_portdrv_slot_reset(), so remove it.
Signed-off-by: Oza Pawandeep
[bhelgaas: changelog, remove pcie_portd
On Wed, Jul 18, 2018 at 11:19:18AM -0700, Linus Torvalds wrote:
> On Wed, Jul 18, 2018 at 11:13 AM Al Viro wrote:
> >
> > Linus, David - do you have any objections to the above?
>
> I damn well do.
>
> I explained earlier why it's wrong and fragile, and why it can just
> cause the *reverse* secu
On Thu, Jun 28, 2018 at 2:50 AM, Federico Vaga wrote:
> On Wednesday, 27 June 2018 23:23:07 CEST Alan Tull wrote:
>> On Wed, Jun 27, 2018 at 4:25 AM, Federico Vaga
> wrote:
>> > Hi Alan,
>> >
>> > On Tuesday, 26 June 2018 23:00:46 CEST Alan Tull wrote:
>> >> On Fri, Jun 22, 2018 at 2:53 AM, Feder
Fix incorrect format used for OR clause in SPDX license identifier.
Signed-off-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +-
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/
Three files dual-licensed were missing the SPDX license identifiers.
Signed-off-by: Krzysztof Kozlowski
---
arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 38 +-
arch/arm/boot/dts/tegra124-apalis-eval.dts | 38 +-
arch/arm/boot/dts/tegra124-a
---
kernel: 4.4.142-rc1
git repo: https://git.linaro.org/lkft/arm64-stable-rc.git
git branch: 4.4.142-rc1-hikey-20180718-235
git commit: 70607bf14095a0aabac2828351f3cec1ac1b1267
git describe: 4.4.142-rc1-hikey-20180718-235
Test details:
https://qa-reports.linaro.org/lkft/linaro-hike
Fix indentation and alignment when spaces were used instead of tabs.
This fixes checkpatch errors like:
ERROR: code indent should use tabs where possible
#306: FILE: arch/arm/boot/dts/tegra20-paz00.dts:306:
+^I^I <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;$
Signed-off-by: Krzysztof K
On Mon, Jul 16, 2018 at 10:56 PM Benjamin Herrenschmidt
wrote:
>
> On Mon, 2018-07-16 at 07:55 -0600, Rob Herring wrote:
> > If that data is one set per SoC, then i'm not that concerned having
> > platform-specific data in the driver. That doesn't mean the driver is
> > not "generic". It's still n
Greetings,
Please I decided to contact you about this Business Offer. Please If you are
not interested, ignore this mail and if you are interested please reply me and
i will give you more information.
Thanks,
Peter Achilleos
On Wed, Jul 18, 2018 at 12:46 PM Al Viro wrote:
>
> Huh? Nevermind ->write(), what about open()?
What about open?
At open time, file->f_cred is the same as current_cred().
So yes, open uses current cred. What's the problem?
Now, if you then use a tasklet or some other thread to do the open,
t
The driver supports multiple hardware variants of Exynos I2C controller
which differ in FIFO depth, handling of interrupts and bus recovery in
HSI2C_MASTER_ST_LOSE state.
The difference in variant was a single bit set for Exynos7 variants and
implicit lack of this bit for other variants.
Make eac
Remove unused 'mout_user_aclk400_mcuisp_p4x12' variable to fix GCC warning:
drivers/clk/samsung/clk-exynos4412-isp.c:40:27: warning:
'mout_user_aclk400_mcuisp_p4x12' defined but not used
[-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski
---
drivers/clk/samsung/clk-exyno
Replace GPL license statements with SPDX license identifiers (GPL-2.0).
Signed-off-by: Krzysztof Kozlowski
---
include/dt-bindings/clock/exynos3250.h| 5 +
include/dt-bindings/clock/exynos4.h | 7 ++-
include/dt-bindings/clock/exynos5250.h| 7 ++-
Replace GPL license statement with SPDX license identifier (GPL-2.0+).
Signed-off-by: Krzysztof Kozlowski
---
include/dt-bindings/thermal/thermal_exynos.h | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/include/dt-bindings/thermal/thermal_exynos.h
b/include/dt-b
Replace GPL license statement with SPDX license identifier (GPL-2.0).
Signed-off-by: Krzysztof Kozlowski
---
include/dt-bindings/pinctrl/samsung.h | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/include/dt-bindings/pinctrl/samsung.h
b/include/dt-bindings/pinctrl/samsu
On Wed, Jul 18, 2018 at 12:53:48PM -0700, Linus Torvalds wrote:
> On Wed, Jul 18, 2018 at 12:46 PM Al Viro wrote:
> >
> > Huh? Nevermind ->write(), what about open()?
>
> What about open?
>
> At open time, file->f_cred is the same as current_cred().
int cachefiles_write_page(struct fscache_sto
Dear Thomas,
Am 18.07.2018 um 21:00 schrieb Thomas Gleixner:
On Wed, 18 Jul 2018, Paul Menzel wrote:
On 07/18/18 17:39, Thomas Gleixner wrote:
Bah. Could you please enable GENERIC_IRQ_DEBUGFS and after a successful
boot up provide me the content of all files in /sys/kernel/debug/irq/ and
its
On Mon, Jul 9, 2018 at 4:39 PM, Alan Tull wrote:
On Mon, Jul 9, 2018 at 4:39 PM, Alan Tull wrote:
This patch is now outdated and would break the upstream. I currently
doubt that this change is needed or would be helpful. The discussion
on whether this patch is needed is on a separate thread:
This patchset adds DMA controller support for Actions Semi Owl family
S900 SoC. This driver has been structured in a way such that there will be only
one controller driver for the whole Owl family series (S500, S700 and
S900 SoCs).
There are 12 physical channels and 46 logical channels supported b
Add devicetree binding for Actions Semi Owl SoCs DMA controller.
Signed-off-by: Manivannan Sadhasivam
---
.../devicetree/bindings/dma/owl-dma.txt | 46 +++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/owl-dma.txt
diff --git a/D
Add DMA controller node for Actions Semi S900 SoC.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm64/boot/dts/actions/s900.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi
b/arch/arm64/boot/dts/actions/s900.dtsi
index 7ae8b931f000..
Add Actions Semi Owl family S900 DMA driver.
Signed-off-by: Manivannan Sadhasivam
---
drivers/dma/Kconfig |8 +
drivers/dma/Makefile |1 +
drivers/dma/owl-dma.c | 1021 +
3 files changed, 1030 insertions(+)
create mode 100644 drivers/dma/owl-dm
Add entry for Actions Semi Owl SoCs DMA driver under ARM/ACTIONS.
Signed-off-by: Manivannan Sadhasivam
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 09b54e9ebc6f..56d9c7715c2a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1145,12 +1145,14
On Wed, Jul 18, 2018 at 09:41:05PM +0200, David Woodhouse wrote:
>
>
> On Wed, 2018-07-18 at 09:37 -0700, Paul E. McKenney wrote:
> > On Wed, Jul 18, 2018 at 06:01:51PM +0200, David Woodhouse wrote:
> > >
> > > On Wed, 2018-07-18 at 08:36 -0700, Paul E. McKenney wrote:
> > > >
> > > > And I fin
From: NeilBrown
Date: Mon, 16 Jul 2018 09:57:11 +1000
> Some users of rhashtable might need to change the key
> of an object and move it to a different location in the table.
> Other users might want to allocate objects using
> SLAB_TYPESAFE_BY_RCU which can result in the same memory allocation
>
On Wed, Jul 18, 2018 at 09:04:11PM +0100, Al Viro wrote:
> On Wed, Jul 18, 2018 at 12:53:48PM -0700, Linus Torvalds wrote:
> > On Wed, Jul 18, 2018 at 12:46 PM Al Viro wrote:
> > >
> > > Huh? Nevermind ->write(), what about open()?
> >
> > What about open?
> >
> > At open time, file->f_cred is
On Wed, Jul 18, 2018 at 1:19 AM Jiri Olsa wrote:
>
> On Mon, Jul 16, 2018 at 02:51:01PM -0700, Cong Wang wrote:
> > hrtimer_cancel() busy-waits for the hrtimer callback to stop,
> > pretty much like del_timer_sync(). This creates a possible deadlock
> > scenario where we hold a spinlock before cal
On Wed, 18 Jul 2018, Tetsuo Handa wrote:
> > diff --git a/mm/mmap.c b/mm/mmap.c
> > --- a/mm/mmap.c
> > +++ b/mm/mmap.c
> > @@ -3059,25 +3059,28 @@ void exit_mmap(struct mm_struct *mm)
> > if (unlikely(mm_is_oom_victim(mm))) {
> > /*
> > * Manually reap the mm to free
On Thu 2018-07-19 00:38:06, Chen Yu wrote:
> As security becomes more and more important, we add the in-kernel
> encryption support for hibernation.
Sorry, this does not really explain what security benefit it is
supposed have to against what attack scenarios.
Which unfortunately means it can not
Speaking of the ISP clocks driver, I wonder why this one was never merged?
https://patches.linaro.org/patch/115531/
- Tobias
Krzysztof Kozlowski wrote:
> Remove unused 'mout_user_aclk400_mcuisp_p4x12' variable to fix GCC warning:
>
> drivers/clk/samsung/clk-exynos4412-isp.c:40:27: warning:
On Tue, 17 Jul 2018 12:39:00 -0500
"Gustavo A. R. Silva" wrote:
> info.index can be indirectly controlled by user-space, hence leading
> to a potential exploitation of the Spectre variant 1 vulnerability.
>
> This issue was detected with the help of Smatch:
>
> drivers/vfio/pci/vfio_pci.c:734 v
On Wed, 2018-07-18 at 21:48 +0200, Krzysztof Kozlowski wrote:
> Fix incorrect format used for OR clause in SPDX license identifier.
Can you please elaborate how you got to that conclusion as there are
various other device trees having it specified the exact same way. Plus
I was actually even in di
On Wed, Jul 18, 2018 at 1:04 PM Al Viro wrote:
>
>
> int cachefiles_write_page(struct fscache_storage *op, struct page *page)
> {
> ...
> file = dentry_open(&path, O_RDWR | O_LARGEFILE, cache->cache_cred);
Ugh. So on the one hand, in this case I'd actually be more ok with the
whole "call_
On Wed, 2018-07-18 at 21:48 +0200, Krzysztof Kozlowski wrote:
> Fix indentation and alignment when spaces were used instead of tabs.
> This fixes checkpatch errors like:
>
> ERROR: code indent should use tabs where possible
> #306: FILE: arch/arm/boot/dts/tegra20-paz00.dts:306:
> +^I^I
Do you have need for image editing?
We have 20 image editors and on daily basis 2000 images can be processed.
If you want to check our quality of work please send us a photo with
instruction and we will work on it.
Photo cut out, masking, clipping path Color, brightness and contrast
correction
On Wed, 2018-07-18 at 21:48 +0200, Krzysztof Kozlowski wrote:
> Three files dual-licensed were missing the SPDX license identifiers.
As mentioned before [1] I am in the process of preparing a patch set
which cleans that up across all Toradex device trees. Our plan is to
actually move them all to d
On Wed, 2018-07-18 at 21:48 +0200, Krzysztof Kozlowski wrote:
> Fix incorrect format used for OR clause in SPDX license identifier.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +-
> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +-
> 2
On Wed, Jun 6, 2018 at 1:02 PM Richard Guy Briggs wrote:
> Signed-off-by: Richard Guy Briggs
> ---
> net/rfkill/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
I would suggest splitting this patch from the audit container ID
patchset and sending it to the netdev folks. It really
On Wed, Jul 18, 2018 at 12:24 PM, Bo Chen wrote:
> In 'e1000_set_ringparam()', the tx_ring and rx_ring are updated with new value
> and the old tx/rx rings are freed only when the device is up. There are
> resource
> leaks on old tx/rx rings when the device is not up. This bug is reported by
> C
> On Jul 17, 2018, at 4:04 PM, Andy Lutomirski wrote:
>
>
> I think you've introduced a minor-ish performance regression due to
> changing the old (admittedly terribly documented) control flow a bit.
> Before, if real_prev == next, we would skip:
>
> load_mm_cr4(next);
> switch_ldt(real_prev
On 18/07/2018 20:03, Jim Mattson wrote:
> On Wed, Jul 18, 2018 at 10:55 AM, Radim Krčmář wrote:
>
>>> + vmx->nested.nested_run_pending = 1;
>> This is not necessary. We're only copying state and do not add anything
>> that would be lost on a nested VM exit without prior VM entry.
> If nested
In preparation for enabling the stackleak plugin on arm64,
we need a way to get the bounds of the current stack.
Introduce a new primitive current_stack_type which is similar
to x86's get_stack_info. Utilize that to rework
on_accessible_stack slightly as well.
Signed-off-by: Laura Abbott
---
So
Implementation of stackleak based heavily on the x86 version
Signed-off-by: Laura Abbott
---
Since last time: Minor style cleanups. Re-wrote check_alloca to
correctly handle all stack types. While doing that, I also realized
current_top_of_stack was incorrect so I fixed that as well.
---
arch/
Hi,
This is the new version of stackleak for arm64 to go with v14 of the
series for x86. I have a cover letter and few more cc's to go along with
some of the prep work.
I also apologize for terrible versioning on these series. Usually I try
to just reply to the top level patch with this addition
Hi Abhishek,
Abhishek Sahu wrote on Fri, 6 Jul 2018
13:21:58 +0530:
> Remove the NAND_SKIP_BBTSCAN to use RAM based BBT.
Unless I am understanding it the wrong way, NAND_SKIP_BBTSCAN will skip
the scan of the on-chip BBT and will scan every block to construct a
RAM, based BBT thanks to the BBM
Sigh...
Nacked-by: Tetsuo Handa
because David is not aware what is wrong.
On 2018/07/19 5:22, David Rientjes wrote:
> On Wed, 18 Jul 2018, Tetsuo Handa wrote:
>
>>> diff --git a/mm/mmap.c b/mm/mmap.c
>>> --- a/mm/mmap.c
>>> +++ b/mm/mmap.c
>>> @@ -3059,25 +3059,28 @@ void exit_mmap(struct mm_s
On Wed, Jul 18, 2018 at 01:43:00PM -0700, Linus Torvalds wrote:
> What I really think I'd prefer is to have some simple way to "poison"
> current_cred(). It could be something as simple as a per-thread
> counter, and we'd have current_cred() do
>
> WARN_ON_ONCE(in_interrupt() || current-
Boris,
Can you please check the change in qcom_nandc_write_oob() is
valid? I think it is but as this is a bit of a hack I prefer double checking.
Thanks,
Miquèl
Abhishek Sahu wrote on Fri, 6 Jul 2018
13:21:56 +0530:
> The NAND base layer calls write_oob() by setting bytes at
> chip->badblock
On Thu, 19 Jul 2018 00:05:18 +0530
Srinath Mannam wrote:
> Hi Alex,
>
> On Tue, Jul 17, 2018 at 8:52 PM, Alex Williamson
> wrote:
> > On Fri, 13 Jul 2018 10:26:17 +0530
> > Srinath Mannam wrote:
> >
> >> By default all BARs map with VMA access permissions
> >> as pgprot_noncached.
> >>
> >>
Linus Torvalds wrote:
> and then read/write/open could just inc/dec the cred_poison counter
> (when the debug option is set).
As I may have said, I have tried modifying the kernel to pass the cred pointer
down. The drivers and ioctl() implementations are/were particularly nasty in
this respect.
Linus Torvalds wrote:
> I explained earlier why it's wrong and fragile, and why it can just
> cause the *reverse* security problem if you do it wrong. So now you
> take a subtle bug, and make it even more subtle, and encourage people
> to do this known-broken model of using creds at IO time.
Are
Hi Linus, Al,
I'm thinking of adding in the attached patch as a starting point for replacing
write() as the method by which configuration/actioning is done.
For the moment, it just glues the key and the value back together inside the
kernel and passes that on to the filesystem. I'm still working
Hi Abhishek,
Abhishek Sahu wrote on Fri, 6 Jul 2018
13:21:59 +0530:
> Driver does not send the commands to NAND device for page
> read/write operations in ->cmdfunc(). It just does some
> minor variable initialization and rest of the things
> are being done in actual ->read/write_oob[_raw].
Th
Hi Mathieu,
On 07/18/2018 08:43 PM, Mathieu Poirier wrote:
When enabling the lockdep mechanic and working with CPU-wide scenarios we
get the following console output:
This is fixed by working with the cpu_present_mask, avoinding at the same
the need to use get/put_online_cpus() that triggers
On Wed, 18 Jul 2018 23:15:26 +0200
Miquel Raynal wrote:
> Hi Abhishek,
>
> Abhishek Sahu wrote on Fri, 6 Jul 2018
> 13:21:58 +0530:
>
> > Remove the NAND_SKIP_BBTSCAN to use RAM based BBT.
>
> Unless I am understanding it the wrong way, NAND_SKIP_BBTSCAN will skip
> the scan of the on-chip
Adjust tcp_client.py and tcp_server.py to work with Python 3 by using
the print function, marking string literals as bytes, and using the
newer exception syntax. This should be functionally equivalent and
support Python 2.6 through Python 3.7.
Signed-off-by: Jeremy Cline
---
tools/testing/selfte
Hi Boris,
Boris Brezillon wrote on Wed, 18 Jul 2018
23:36:37 +0200:
> On Wed, 18 Jul 2018 23:15:26 +0200
> Miquel Raynal wrote:
>
> > Hi Abhishek,
> >
> > Abhishek Sahu wrote on Fri, 6 Jul 2018
> > 13:21:58 +0530:
> >
> > > Remove the NAND_SKIP_BBTSCAN to use RAM based BBT.
> >
> >
On Wed, 18 Jul 2018 16:52:54 +0200 Geert Uytterhoeven
wrote:
> As PERL uses its own internal character encoding, always calling
> encode("utf8", ...) on the author name may cause corruption, leading to
> an author signoff mismatch.
>
> This happens in the following cases:
> - If a patch is in
Abhishek,
Miquel Raynal wrote on Wed, 18 Jul 2018
23:41:44 +0200:
> Hi Boris,
>
> Boris Brezillon wrote on Wed, 18 Jul 2018
> 23:36:37 +0200:
>
> > On Wed, 18 Jul 2018 23:15:26 +0200
> > Miquel Raynal wrote:
> >
> > > Hi Abhishek,
> > >
> > > Abhishek Sahu wrote on Fri, 6 Jul 2018
> >
On Wed, 18 Jul 2018 23:23:50 +0200
Miquel Raynal wrote:
> Boris,
>
> Can you please check the change in qcom_nandc_write_oob() is
> valid? I think it is but as this is a bit of a hack I prefer double checking.
Indeed, it's hack-ish.
>
> Thanks,
> Miquèl
>
>
> Abhishek Sahu wrote on Fri, 6
Hi Alan,
Thanks for your time, comments below
On Wednesday, July 18, 2018 9:47:24 PM CEST Alan Tull wrote:
> On Thu, Jun 28, 2018 at 2:50 AM, Federico Vaga
wrote:
> > On Wednesday, 27 June 2018 23:23:07 CEST Alan Tull wrote:
> >> On Wed, Jun 27, 2018 at 4:25 AM, Federico Vaga
> >
> > wrote:
>
Adding a new IOCTL command to communicate PMU specific configuration to
PMU kernel drivers. This can be anything a PMU might need for
configuration that doesn't fit in the perf_event_attr structure, such
as the CoreSight sink to use for a session.
Signed-off-by: Mathieu Poirier
---
include/uapi
Using sysFS to communicate sink information for a trace session doesn't
work when more than one CPU is involved in the scenario. As such
communicate the sink information to each event by using the SET_DRV_CONFIG
ioctl command.
Signed-off-by: Mathieu Poirier
---
tools/perf/arch/arm/util/cs-etm.c
This set adds the capability to communiate event specific configuration
to the PMU kernel driver using an ioctl(). The functionatlity is made
generic enough for anyone to use but is targeted at the identification
of CoreSight sinks when operating in CPU-wide trace scenarios.
Applies cleanly on v4
Following in the footsteps of what was done for filters, adding the
necessary mechanic needed to push down driver specific configuration
to the kernel using an ioctl. By proceeding this way PMU specific
configuration such as CoreSight sink specification can be communicated
to each event.
Signed-of
This patch uses the PMU driver configuration held in event::hw::drv_config
to select a sink for each event that is created (the old sysFS way of
working is kept around for backward compatibility).
By proceeding in this way a sink can be used by multiple sessions
without having to play games with e
Make structure perf_evsel available to the PMU driver configuration code.
That way function perf_evsel__apply_drv_config() can be used from within
that code and information pertaining to the 'perf_evsel_config_term' is
still available.
Signed-off-by: Mathieu Poirier
---
tools/perf/arch/arm/util/
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