Add mappings to the KVM ASI page-table so that KVM can run with its
address space isolation without faulting too much.
Signed-off-by: Alexandre Chartre
---
arch/x86/kvm/vmx/isolation.c | 155 -
arch/x86/kvm/vmx/vmx.c |1 -
arch/x86/kvm/vmx/vmx.h
Provide functions to copy page-table entries from the kernel page-table
to an ASI page-table for a specified VA range. These functions are based
on the copy_pxx_range() functions defined in mm/memory.c. A difference
is that a level parameter can be specified to indicate the page-table
level (PGD, P
From: Liran Alon
Add the address_space_isolation parameter to the kvm module.
When set to true, KVM #VMExit handlers run in isolated address space
which maps only KVM required code and per-VM information instead of
entire kernel address space.
This mechanism is meant to mitigate memory-leak sid
Add an option to map the current task into an ASI page-table.
The task is mapped when entering isolation and unmapped on
abort/exit.
Signed-off-by: Alexandre Chartre
---
arch/x86/include/asm/asi.h |2 ++
arch/x86/mm/asi.c | 25 +
arch/x86/mm/asi_pagetable
From: Liran Alon
Switch to KVM address space on entry to guest. Most of KVM #VMExit
handlers will run in KVM isolated address space and switch back to
host address space only before accessing sensitive data. Sensitive
data is defined as either host data or other VM data.
Currently, we switch bac
Hi,
This is version 2 of the "KVM Address Space Isolation" RFC. The code
has been completely changed compared to v1 and it now provides a generic
kernel framework which provides Address Space Isolation; and KVM is now
a simple consumer of that framework. That's why the RFC title has been
changed f
Provide functions to copy page-table entries from the kernel page-table
to an ASI page-table for a percpu buffer. A percpu buffer have a different
VA range for each cpu and all them have to be copied.
Signed-off-by: Alexandre Chartre
---
arch/x86/include/asm/asi.h |6 ++
arch/x86/mm/asi
Add functions to keep track of VA ranges mapped in an ASI page-table.
This will be used when unmapping to ensure the same range is unmapped,
at the same page-table level. This is also be used to handle mapping
and unmapping of overlapping VA ranges.
Signed-off-by: Alexandre Chartre
---
arch/x86/
When address space isolation is active, cpu_tlbstate isn't necessarily
mapped in the ASI page-table, this would cause ASI to fault. Instead of
just mapping cpu_tlbstate, update __get_current_cr3_fast() and
cr4_read_shadow() by caching the cr3/cr4 values in the ASI session
when ASI is active.
Note
tree.h has static forward declarations for inline function declared
in tree_plugin.h and tree_stall.h. These forward declarations prevent
including tree.h into a file different from tree.c
Signed-off-by: Alexandre Chartre
---
kernel/rcu/tree.c | 54 +
Add an option to map RCU data when creating an ASI. This will map
the percpu rcu_data (which is not exported by the kernel), and
allow ASI to use RCU without faulting.
Signed-off-by: Alexandre Chartre
---
arch/x86/include/asm/asi.h |1 +
arch/x86/mm/asi.c |4
2 files change
Map KVM memslots and IO buses into KVM ASI. Mapping is checking on each
KVM ASI enter because they can change.
Signed-off-by: Alexandre Chartre
---
arch/x86/kvm/x86.c | 36 +++-
include/linux/kvm_host.h |2 ++
2 files changed, 37 insertions(+), 1 delet
Address space isolation should be aborted if there is an interrupt,
an exception or a context switch. Interrupt/exception handlers and
context switch code need to run with the full kernel address space.
Address space isolation is aborted by restoring the original CR3
value used before entering addr
Add functions to track buffers allocated for an ASI page-table. An ASI
page-table can have direct references to the kernel page table, at
different levels (PGD, P4D, PUD, PMD). When freeing an ASI page-table,
we should make sure that we free parts actually allocated for the ASI
page-table, and not
kmsg_dump_get_buffer() is supposed to select all the youngest log
messages which fit into the provided buffer. It determines the correct
start index by using msg_print_text() with a NULL buffer to calculate
the size of each entry. However, when performing the actual writes,
msg_print_text() only
On Wed, Jul 10, 2019 at 09:05:21PM -0700, Linus Torvalds wrote:
> If wait_event_interruptible() returns -ERESTARTSYS, it means that we
> have a signal pending.
>
> And if we have a signal pending, then you can't go back and call
> wait_event_interruptible() in a loop, because the signal will
> *co
Hi Ezequiel,
Just a few small points:
On 7/5/19 4:50 PM, Ezequiel Garcia wrote:
> From: Pawel Osciak
>
> Add the parsed VP8 frame pixel format and controls, to be used
> with the new stateless decoder API for VP8 to provide parameters
> for accelerator (aka stateless) codecs.
>
> Reviewed-by:
The VFIO reset hook is called every time a platform device is passed
to a guest or removed from a guest.
When the XHCI device is unbound from the host, the host driver
disables the XHCI clocks/phys/regulators so when the device is passed
to the guest it becomes dis-functional.
This initial implem
On Thu, Jul 11, 2019 at 12:29:21PM +, Bernard Metzler wrote:
>
> >To: "Bernard Metzler"
> >From: "Jason Gunthorpe"
> >Date: 07/11/2019 01:53PM
> >Cc: "Leon Romanovsky" , "Stephen Rothwell"
> >, "Doug Ledford" , "David
> >Miller" , "Networking" ,
> >"Linux Next Mailing List" , "Linux Kernel
>
Arnaldo, can you pick this?
On 2019/6/4 16:50, Yuehaibing wrote:
> Hi,
>
> Friendly ping:
>
> Arnaldo, will you take this serial?
>
> On 2019/3/21 10:31, Yue Haibing wrote:
>> From: YueHaibing
>>
>> v2:
>> - patch 1 fix commilt log
>> - patch 2 use correct Fixes tag
>>
>> This patch series f
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Use the correct macro when registering the platform device.
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
> ---
> drivers/mailbox/qcom-apcs-ipc-m
On Thu, Jul 11, 2019 at 1:13 AM Uros Bizjak wrote:
>
> Recent patch [1] disabled a self-snoop feature on a list of processor
> models with a known errata, so we are confident that the feature
> should work on remaining models also for other purposes than to speed
> up MTRR programming.
>
> I would
On 07/10/2019 11:35 PM, wen.yan...@zte.com.cn wrote:
>>> we developed a coccinelle script to detect such problems.
>>
>> Would you find the implementation of the function “dt_init_idle_driver”
>> suspicious according to discussed source code search patterns?
>> https://git.kernel.org/pub/scm/linux/
And I've just noticed that I've messed up the subject of the cover letter.
There are 26 patches, not 27. So it should have been 00/26 not 00/27.
Sorry about that.
alex.
On 7/11/19 4:25 PM, Alexandre Chartre wrote:
Hi,
This is version 2 of the "KVM Address Space Isolation" RFC. The code
has
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> There is clock controller functionality in the APCS hardware block of
> qcs404 devices similar to msm8916.
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
> drivers/mailbox/
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> When the APCS clock is registered (platform dependent), it retrieves
> its parent names from hardcoded values in the driver.
>
> The following commit allows the DT node to provide such clock names to
> the platform data based clock driver
Document Amazon's Annapurna Labs PCIe host bridge.
Signed-off-by: Jonathan Chocron
---
.../devicetree/bindings/pci/pcie-al.txt | 45 +++
MAINTAINERS | 1 +
2 files changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bind
On Thu, Jul 11, 2019 at 4:51 AM Peter Zijlstra wrote:
>
> Since INT3/#BP no longer runs on an IST, this workaround is no longer
> required.
>
> Tested by running lockdep+ftrace as described in the initial commit:
>
> 5963e317b1e9 ("ftrace/x86: Do not change stacks in DEBUG when calling
> lockde
For the paltforms including LS1012A, LS1021A, LS1028A, LS1043A,
LS1046A, LS1088A, LS208xA that has the FlexTimer
module, implementing alarm functions within RTC subsystem
to wakeup the system when system going to sleep (work with RCPM driver).
Signed-off-by: Biwen Li
---
Change in v3:
- a
On Tue, Jul 9, 2019 at 4:44 PM Cedric Hombourger
wrote:
>
> Debian-based distributions place libc header files in a machine
> specific directory (/usr/include/) instead of
> /usr/include/asm to support installation of the linux-libc-dev
> package from multiple architectures. Move headers installed
On Thu, Jul 11, 2019 at 03:12:13PM +0800, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/infiniband/sw/siw/siw_cm.c: In function siw_cm_llp_state_change:
> drivers/infiniband/sw/siw/siw_cm.c:1278:17: warning: variable s set but not
> used [-Wunused-but-set-variable
On Wed, Jul 10, 2019 at 03:39:30PM +0200, Geert Uytterhoeven wrote:
> If LIBCRC32C and DMA_VIRT_OPS are not enabled:
>
> drivers/infiniband/sw/siw/siw_main.o: In function `siw_newlink':
> siw_main.c:(.text+0x35c): undefined reference to `dma_virt_ops'
> drivers/infiniband/sw/siw/siw_qp
ping...
This series adds support for Amazon's Annapurna Labs DT-based PCIe host
controller driver.
Additionally, it adds 3 quirks (ACS, VPD and MSI-X) and 2 generic DWC patches.
Regarding the 2nd DWC patch (PCI flags support), do you think this should
be done in the context of a host-bridge driver at all
The patch adds binding for ftm alarm driver
Signed-off-by: Biwen Li
---
Change in v3:
- remove reg-names property
- correct cells number
Change in v2:
- replace ls1043a with ls1088a as example
- add rcpm node and fsl,rcpm-wakeup property
.../devicetree/bindings/
On 11/07/2019 13:57, Bhupesh Sharma wrote:
> With commit b6664ba42f14 ("s390, kexec_file: drop arch_kexec_mem_walk()"),
> we introduced the KEXEC_BUF_MEM_UNKNOWN macro. If kexec_buf.mem is set
> to this value, kexec_locate_mem_hole() will try to allocate free memory.
>
> While other arch(s) lik
Add Amazon's Annapurna Labs vendor ID to pci_ids.h.
Signed-off-by: Jonathan Chocron
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 0dd239f11e91..ed350fd522c6 100644
--- a/include/linux/pci_ids.h
+++ b/incl
On Thu, Jul 11, 2019 at 09:55:56AM -0400, Qian Cai wrote:
> The linux-next commit "linux/dim: Implement RDMA adaptive moderation
> (DIM)" [1] introduced a few compilation warnings.
>
> In file included from ./include/rdma/ib_verbs.h:64,
> from ./include/linux/mlx5/device.h:37,
>
From: Ali Saidi
The Amazon's Annapurna Labs root ports don't advertise an ACS
capability, but they don't allow peer-to-peer transactions and do
validate bus numbers through the SMMU. Additionally, it's not possible
for one RP to pass traffic to another RP.
Signed-off-by: Ali Saidi
Signed-off-by
The Amazon Annapurna Labs pcie host bridge exposes the VPD capability,
but there is no actual support for it.
The reason for not using the already existing quirk_blacklist_vpd()
is that, although this fails pci_vpd_read/write, the 'vpd' sysfs
entry still exists. When running lspci -vv, for example
On some platforms, the host bridge exposes an MSI-X capability but
doesn't actually support it.
This causes a crash during initialization by the pcieport driver, since
it tries to configure the MSI-X capability.
Signed-off-by: Jonathan Chocron
---
drivers/pci/quirks.c | 8
1 file change
This driver is DT based and utilizes the DesignWare APIs.
It allows using a smaller ECAM range for a larger bus range -
usually an entire bus uses 1MB of address space, but the driver
can use it for a larger number of buses.
All link initializations are handled by the boot FW.
Signed-off-by: Jona
Some PCIe controllers can be set to either Host or EP according to some
early boot FW. To make sure there is no discrepancy (e.g. FW configured
the port to EP mode while the DT specifies it as a host bridge or vice
versa), a check has been added for each mode.
Signed-off-by: Jonathan Chocron
---
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Allow accessing the parent clock names required for the driver
> operation by using the device tree node.
>
> This permits extending the driver to other platforms without having to
> modify its source code.
>
> For backwards compatibilit
Changelog from v1:
o resend the whole filesystem into a patchset suggested by Greg;
o code is more cleaner, especially for decompression frontend.
--8<--
Hi,
EROFS file system has been in Linux-staging for about a year.
It has been proved to be stable enough to move out of staging
by 1
This basically aligns the usage of PCI_PROBE_ONLY and
PCI_REASSIGN_ALL_BUS in dw_pcie_host_init() with the logic in
pci_host_common_probe().
Now it will be possible to control via the devicetree whether to just
probe the PCI bus (in cases where FW already configured it) or to fully
configure it.
On Thu, Jul 11, 2019 at 4:31 AM Nitesh Narayan Lal wrote:
>
>
> On 7/10/19 7:40 PM, Alexander Duyck wrote:
> > On Wed, Jul 10, 2019 at 12:52 PM Nitesh Narayan Lal
> > wrote:
> >
> > The results up here were redundant with what is below so I am just
> > dropping them. I would suggest only includi
This patch introduces an temporary _on-stack_ page
pool to reuse the freed page directly as much as
it can for better performance and release all pages
at a time, it also slightly reduces the possibility of
the potential memory allocation failure.
Signed-off-by: Gao Xiang
---
fs/erofs/internal.h
On Thu, Jul 11, 2019 at 09:08:49AM -0400, Joel Fernandes wrote:
> On Thu, Jul 11, 2019 at 05:30:52AM -0700, Paul E. McKenney wrote:
> > On Wed, Jul 10, 2019 at 10:20:25AM +0900, Byungchul Park wrote:
> > > On Tue, Jul 09, 2019 at 05:41:02AM -0700, Paul E. McKenney wrote:
> > > > > Hi Paul,
> > > >
On 7/11/19 10:58 AM, Alexander Duyck wrote:
> On Thu, Jul 11, 2019 at 4:31 AM Nitesh Narayan Lal wrote:
>>
>> On 7/10/19 7:40 PM, Alexander Duyck wrote:
>>> On Wed, Jul 10, 2019 at 12:52 PM Nitesh Narayan Lal
>>> wrote:
>>>
>>> The results up here were redundant with what is below so I am just
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Allow accessing the parent clock name required for the driver
> operation using the device tree node.
>
> This permits extending the driver to other platforms without having to
> modify its source code.
>
> For backwards compatibility le
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Make the output of the high frequency pll a clock provider.
> On the QCS404 this PLL controls cpu frequency scaling.
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
> Acked-by: Ste
This print statement is redundant as kfifo_alloc just calls kmalloc_array
and without the __GFP_NOWARN flag, already does a dump_stack().
Signed-off-by: Keyur Patel
---
drivers/staging/most/cdev/cdev.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/most/
On Thu, Jul 11, 2019 at 10:01:34AM +0200, Peter Zijlstra wrote:
> On Thu, Jul 11, 2019 at 07:11:19AM +, Nadav Amit wrote:
> > > On Jul 10, 2019, at 7:22 AM, Jiri Kosina wrote:
> > >
> > > On Wed, 10 Jul 2019, Peter Zijlstra wrote:
> > >
> > >> If we mark the key as RO after init, and then tr
On Thu, Jul 11, 2019 at 8:04 AM Nitesh Narayan Lal wrote:
>
>
> On 7/11/19 10:58 AM, Alexander Duyck wrote:
> > On Thu, Jul 11, 2019 at 4:31 AM Nitesh Narayan Lal
> > wrote:
> >>
> >> On 7/10/19 7:40 PM, Alexander Duyck wrote:
> >>> On Wed, Jul 10, 2019 at 12:52 PM Nitesh Narayan Lal
> >>> wro
Add IOMMU node for Marvell AP806 based SoCs.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
inde
Now that the i.MX6 and i.MX7 clock drivers have been switched to clk_hw based,
we can remove the clk based API that is not used by any i.MX clock driver.
The following APIs are going away now:
- imx_clk_busy_divider
- imx_clk_busy_mux
- imx_clk_fixup_divider
- imx_clk_fixup_mux
- imx_clk_mux_ldb
-
On Thu 11-07-19 08:38:52, Steven J. Magnani wrote:
> Some UDF creators (specifically Microsoft, but perhaps others) mishandle
> the ECMA-167 corner case that requires descriptors within a Volume
> Recognition Sequence to be placed at 4096-byte intervals on media where
> the block size is 4K. Inst
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
> to keep the software model of the clock in line with reality, the
> framework transverses the clock tree and disables those clocks that
> were enabled by the firmware
On 7/11/19 11:08 AM, Alexander Duyck wrote:
> On Thu, Jul 11, 2019 at 8:04 AM Nitesh Narayan Lal wrote:
>>
>> On 7/11/19 10:58 AM, Alexander Duyck wrote:
>>> On Thu, Jul 11, 2019 at 4:31 AM Nitesh Narayan Lal
>>> wrote:
On 7/10/19 7:40 PM, Alexander Duyck wrote:
> On Wed, Jul 10, 2019
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Specify the clocks that feed the APCS mux/divider instead of using
> default hardcoded values in the source code.
>
> The driver still supports the previous bindings; however with this
> update it we allow the msm8916 to access the parent
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Add a CPU OPP table to qcs404
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjorn Andersson
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> The high frequency pll functionality is required to enable CPU
> frequency scaling operation.
>
Reviewed-by: Bjorn Andersson
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
> ---
Hi Linus,
The following changes since commit a188339ca5a396acc588e5851ed7e19f66b0ebd9:
Linux 5.2-rc1 (2019-05-19 15:47:09 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git
tags/tag-chrome-platform-for-v5.3
for you to fet
On 7/10/19 4:45 PM, Dave Hansen wrote:
> On 7/10/19 12:51 PM, Nitesh Narayan Lal wrote:
>> +struct zone_free_area {
>> +unsigned long *bitmap;
>> +unsigned long base_pfn;
>> +unsigned long end_pfn;
>> +atomic_t free_pages;
>> +unsigned long nbits;
>> +} free_area[MAX_NR_ZONES]
On Thu, Jul 11, 2019 at 10:25:25AM +0900, Minchan Kim wrote:
> When a process expects no accesses to a certain memory range, it could
> give a hint to kernel that the pages can be reclaimed when memory pressure
> happens but data should be preserved for future use. This could reduce
> workingset e
On Thu, Jul 11, 2019 at 07:13:50AM -0700, Matthew Wilcox wrote:
> However, the XA_RETRY_ENTRY might be a good choice. It doesn't normally
> appear in an XArray (it may appear if you're looking at a deleted node,
> but since we're holding the lock, we can't see deleted nodes).
Updated patch (also
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> The high frequency pll is required on compatible Qualcomm SoCs to
> support the CPU frequency scaling feature.
>
Reviewed-by: Bjorn Andersson
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Rami
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Specify the clocks that feed the APCS mux/divider instead of using
> default hardcoded values in the source code.
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
Reviewed-by: Bjor
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Support dynamic voltage and frequency scaling on qcs404.
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
I agree with Niklas on the possibility of squashing this with the opp
tabl
On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
> specifications.
>
> Co-developed-by: Niklas Cassel
> Signed-off-by: Niklas Cassel
> Signed-off-by: Jorge Ramirez-Ortiz
> Acked-by: Stephen Boyd
Reviewed-by: Bjorn
On 7/11/19 2:00 PM, Peter Zijlstra wrote:
> On Thu, Jul 11, 2019 at 01:17:17PM +0200, Dietmar Eggemann wrote:
>> On 7/9/19 3:42 PM, Peter Zijlstra wrote:
>
> That is, we only do those callbacks from:
>
> schedule_tail()
> __schedule()
> rt_mutex_setprio()
> __sched_
On Thu 11 Jul 04:03 PDT 2019, Vivek Gautam wrote:
> To avoid adding files for each future supported SoCs rename
> the file to a generic name - llcc-plat, so that llcc configuration
> tables for other SoCs can be added in the same driver.
>
We've had a generic LLCC Kconfig option and then a speci
Hi Zhengjun,
The patch itself looks fine to me, but could you please create a v3
with a couple changes to the commit message? I noticed you dropped
your original commit message - please add it back and combine with part
of mine, as below. Also, please keep your original Subject line
('[PATCH] tr
Dear RT folks!
I'm pleased to announce the v5.2-rt1 patch set.
Changes since v5.0.21-rt16:
- Rebase to v5.2
First release in the v5.2 series. I had in testing for the last few
days and did not notice anything unusual.
Known issues
- rcutorture is currently broken on -RT. Reported by Ju
On Thu, 2019-07-11 at 10:32 +0100, Lorenzo Pieralisi wrote:
> On Thu, Jul 11, 2019 at 10:12:35AM +0300, Shenhar, Talel wrote:
> >
> > On 7/10/2019 7:45 PM, Jonathan Chocron wrote:
> > > Document Amazon's Annapurna Labs PCIe host bridge.
> >
> > That is the way! (best to keep same wordings (Amazon
Em Thu, Jul 11, 2019 at 10:33:09PM +0800, Yuehaibing escreveu:
>
> Arnaldo, can you pick this?
Thanks, and sorry for the delay, fell thru the cracks.
- Arnaldo
IPQ8074 uses secure PIL. Hence, adding the support for the same.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/remoteproc/qcom_q6v5_wcss.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/
Fixed issue in reading halt-regs parameter from device-tree.
Also adding a flag to check for bcr reset which is not
required for ipq8074.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
---
drivers/remoteproc/qcom_q6v5_wcss.c | 28 ++--
1 file changed,
IPQ8074 needs support for secure pil as well.
Also, currently only unified firmware is supported.
IPQ8074 supports split firmware for q6 and m3, so
adding support for that.
Gokul Sriram Palanisamy (12):
remoteproc: qcom: Add PRNG proxy clock
remoteproc: qcom: Add secure PIL support
remotepro
Add name for ssr subdevice on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c
b/drivers/remoteproc/qco
PRNG clock is needed by the secure PIL, support for the same
is added in subsequent patches.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/remoteproc/qcom_q6v5_wcss.c | 63 +++--
1 file changed, 46
Add mailbox support required in IPQ8074 SoCs.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-g
Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock
IPQ8074 supports split firmware for q6 and m3 as well.
So add support for loading the m3 firmware before q6.
Now the drivers works fine for both split and unified
firmwares.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/remoteproc
Enable remoteproc WCSS PIL driver with glink
and ssr subdevices. Also configures shared memory
and enables smp2p and mailboxes required for IPC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 125 +++
Add support of IPQ8074 with IPC register offset as 8.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbo
Add compatible for IPQ8074 support.
This does not need clocks for scm calls.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmwa
Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
Signed-off-by: Nikhil Prakash V
---
drivers/clk/qcom/gcc-ipq8074.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq
Enables scm support, clock is not needed for enabling scm interface.
Signed-off-by: Gokul Sriram Palanisamy
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts
On 7/11/19 11:25 AM, Nitesh Narayan Lal wrote:
> On 7/10/19 4:45 PM, Dave Hansen wrote:
>> On 7/10/19 12:51 PM, Nitesh Narayan Lal wrote:
>>> +struct zone_free_area {
>>> + unsigned long *bitmap;
>>> + unsigned long base_pfn;
>>> + unsigned long end_pfn;
>>> + atomic_t free_pages;
>>> +
On Thu, Jul 11, 2019 at 12:38:09PM +0300, Jarkko Sakkinen wrote:
> On Wed, Jul 10, 2019 at 04:37:41PM -0700, Xing, Cedric wrote:
> > We are not judging which vessel is better (or the best) among all possible
> > vessels. We are trying to enable more vessels. Every vessel has its pros and
> > cons s
Estimado usuario de correo electrónico,
En nuestro mejor esfuerzo por brindar un excelente servicio a todos nuestros
usuarios, planeamos realizar una actualización del sistema, el proceso tomará
alrededor de 30 minutos. Este mensaje ha estado transmitido por algún tiempo y
aconsejamos a los usu
On Thu, Jun 27, 2019 at 01:32:58PM -0700, Xing, Cedric wrote:
> Just a reminder that #DB/#BP shall be treated differently because they are
> used by debuggers. So instead of branching to the fixup address, the kernel
> shall just signal the process.
More importantly, doing fixup on #DB and #BP si
Estimado usuario de correo electrónico,
En nuestro mejor esfuerzo por brindar un excelente servicio a todos nuestros
usuarios, planeamos realizar una actualización del sistema, el proceso tomará
alrededor de 30 minutos. Este mensaje ha estado transmitido por algún tiempo y
aconsejamos a los usu
On 7/11/19 10:04 AM, Jan Kara wrote:
Thanks for the patches! I've added them to my tree and somewhat simplified
the logic since we don't really care about nsr 2 vs 3 or whether we
actually saw BEA or not. Everything seems to work fine for me but I'd
appreciate if you could doublecheck - the resul
On Tue, Jun 25, 2019 at 06:43:41PM +0300, Jarkko Sakkinen wrote:
> Is there any obvious reason why #PF fixup is in its own patch and the
> rest are collected to the same patch? I would not find it confusing if
> there was one patch per exception but really don't get this division.
I split them due
On Thu 11 Jul 04:03 PDT 2019, Vivek Gautam wrote:
> - Remove 'sdm845' from names, and use 'plat' instead.
> - Move SCT_ENTRY macro to header file.
> - Create a new config structure to asssign to of-match-data.
>
I interpret the intention of these two patches as that you want to add
some new plat
The nr_allocated_banks and allocated banks are initialized as part of
tpm_chip_register. Currently, this is done as part of auto startup
function. However, some drivers, like the ibm vtpm driver, do not run
auto startup during initialization. This results in uninitialized memory
issue and causes a
Estimado usuario de correo electrónico,
En nuestro mejor esfuerzo por brindar un excelente servicio a todos nuestros
usuarios, planeamos realizar una actualización del sistema, el proceso tomará
alrededor de 30 minutos. Este mensaje ha estado transmitido por algún tiempo y
aconsejamos a los usu
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