From: Peng Fan
Add i.MX8MQ/M/N/P compatible string to support i.MX8M SoCs
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/
From: Peng Fan
V3:
Add R-b tag
Remove undocumented property
V2:
Add dt-bindings
Merge dts changes into one patch, since all is to add mu node
Add mu dt bindings
Add mu node
Add i.MX8MP mu root clk
Peng Fan (3):
dt-bindings: mailbox: imx-mu: support i.MX8M
arm64: dts: imx8m: add mu node
From: Peng Fan
Add mu node to let A53 could communicate with M Core.
Signed-off-by: Peng Fan
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8
arch/arm64/boot/dts/freescale
On Mon, Jun 01, 2020 at 12:37:16AM +0200, Rikard Falkeborn wrote:
> + Emil who was working on a patch for this
>
> On Sun, May 31, 2020 at 02:00:45PM +0300, Andy Shevchenko wrote:
> > On Sun, May 31, 2020 at 4:11 AM Syed Nayyar Waris
> > wrote:
> > > On Sat, May 30, 2020 at 2:50 PM Andy Shevchen
From: Alexander Antonov
The previous version can be found at:
v9:
https://lkml.kernel.org/r/20200525080554.21313-1-alexander.anto...@linux.intel.com/
Changes in this revision are:
v9 -> v10:
- Addressed comment from CI Test Service:
1. Fixed coding style issues (old style declaration)
The pre
From: Roman Sudarikov
Each Uncore unit type, by its nature, can be mapped to its own context -
which platform component each PMON block of that type is supposed to
monitor.
Intel® Xeon® Scalable processor family (code name Skylake-SP) makes
significant changes in the integrated I/O (IIO) archite
From: Roman Sudarikov
The accessor to return number of dies on the platform.
Co-developed-by: Alexander Antonov
Signed-off-by: Alexander Antonov
Signed-off-by: Roman Sudarikov
Reviewed-by: Kan Liang
Reviewed-by: Alexander Shishkin
---
arch/x86/events/intel/uncore.c | 13 +++--
arch
From: Roman Sudarikov
Current version supports a server line starting Intel® Xeon® Processor
Scalable Family and introduces mapping for IIO Uncore units only.
Other units can be added on demand.
IIO stack to PMON mapping is exposed through:
/sys/devices/uncore_iio_/dieX
where dieX is fil
> Even in failed case of pm_runtime_get_sync, the usage_count
> is incremented. In order to keep the usage_count with correct
> value call appropriate put.
* I suggest to adjust the word “usage_count” in this change description.
* Would you like to add the tag “Fixes” to the commit message?
Rega
On Mon, Jun 01, 2020 at 12:24:03AM -0700, syzbot wrote:
> syzbot has bisected this bug to:
>
> commit f2c2e717642c66f7fe7e5dd69b2e8ff5849f4d10
> Author: Andrey Konovalov
> Date: Mon Feb 24 16:13:03 2020 +
>
> usb: gadget: add raw-gadget interface
>
> bisection log: https://syzkaller.
On Mon, Jun 01, 2020 at 03:22:01PM +0800, Tao pilgrim wrote:
> On Fri, May 29, 2020 at 10:13 PM Jens Axboe wrote:
> >
> > On 5/29/20 8:11 AM, Kaitao Cheng wrote:
> > > There is a function named ilog2() exist which can replace blksize.
> > > The generated code will be shorter and more efficient on
Any runtime WARN_ON() has to be fixed, and BUILD_BUG_ON() can
help you nitice it earlier.
Signed-off-by: Lai Jiangshan
---
kernel/workqueue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index 7a1fc9fe6314..35120b909234 100644
--- a/
Currently, the size of struct pool_workqueue is smaller than the
smellest requirement (1 << WORK_STRUCT_FLAG_BITS). When the size
of struct pool_workqueue is increasing in future development and
exceed the smellest requirement a little, it will be a big waste
due to alignment.
Add a check in case
The major memory ussage in workqueue is on the pool_workqueue.
The pool_workqueue has alignment requirement which often leads
to padding.
Reducing the memory usage for the pool_workqueue is valuable.
And 32bit system often has less memory, less workqueues,
less works, less concurrent flush_workqu
8a2e8e5dec7e("workqueue: fix cwq->nr_active underflow")
allocated one more bit from the work flags, and it updated
partial of the comments (128 bytes -> 256 bytes), but it
failed to update the info about the number of reserved bits.
Signed-off-by: Lai Jiangshan
---
include/linux/workqueue.h | 2
The major memory ussage in workqueue is on the pool_workqueue.
The pool_workqueue has alignment requirement which often leads
to padding.
Reducing the memory usage for the pool_workqueue is valuable.
And 32bit system often has less memory, less workqueues,
less works, less concurrent flush_workqu
On 30/05/20 19:28, Denis Efremov wrote:
>> On Sat, 2020-05-30 at 17:35 +0300, Denis Efremov wrote:
>>> array_size() is used in alloc calls to compute the allocation
>>> size. Next, "raw" multiplication is used to compute the size
>>> for copy_from_user(). The patch removes duplicated computation
>>
On Mon, 1 Jun 2020 at 07:30, Jarkko Sakkinen
wrote:
>
> On Wed, May 06, 2020 at 03:10:14PM +0530, Sumit Garg wrote:
> > Current trusted keys framework is tightly coupled to use TPM device as
> > an underlying implementation which makes it difficult for implementations
> > like Trusted Execution En
On 30/05/2020 00:04, Vadym Kochan wrote:
ONIE is a small operating system, pre-installed on bare metal network
switches, that provides an environment for automated provisioning.
This system requires that NVMEM (EEPROM) device holds various system
information (mac address, platform name, etc)
On Sun, May 31, 2020 at 11:17 PM Nick Gasson wrote:
>
> On 05/28/20 17:32 PM, Ian Rogers wrote:
> >
> > So on tip/perf/core with:
> > 1c0cd2dbb993 perf jvmti: Fix jitdump for methods without debug info
> > 3ce17c1e52f4 perf jvmti: remove redundant jitdump line table entries
> >
> > I've been tryin
On 5/28/20 1:06 PM, Andy Shevchenko wrote:
On Thu, May 28, 2020 at 12:33:17PM +0300, Serge Semin wrote:
A PM workaround activated by the flag MODEL_CHERRYTRAIL has been removed
since commit 9cbeeca05049 ("i2c: designware: Remove Cherry Trail PMIC I2C
bus pm_disabled workaround"), but the flag mo
+CC linux-mm
On 5/31/20 12:34 PM, Pavel Machek wrote:
> Hi!
>
> This is simple cat /dev/sda > /dev/zero... on thinkpad x60 (x86-32),
> with spinning rust.
>
> PID USER PR NIVIRTRESSHR S %CPU %MEM TIME+ COMMAND
>1000 root 20 0 0 0 0 R 53.3 0.
On 29/05/2020 00:53, Douglas Anderson wrote:
The 'struct nvmem_config' has a stride attribute that specifies the
needed alignment for accesses into the nvmem. This is used in
nvmem_cell_info_to_nvmem_cell() but not in the sysfs read/write
functions. If the alignment is important in one place
Hi Tudor,
On 30/05/20 06:42PM, tudor.amba...@microchip.com wrote:
> On Monday, May 25, 2020 12:15:38 PM EEST Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > The Micron MT35XU512ABA flash does not support the quad ena
Christophe JAILLET writes:
> Commit 6d33ee7a0534 ("pinctrl: pxa: Use devm_pinctrl_register() for pinctrl
> registration")
> has turned a 'pinctrl_register()' into 'devm_pinctrl_register()' in
> 'pxa2xx_pinctrl_init()'.
> However, the corresponding 'pinctrl_unregister()' call in
> 'pxa2xx_pinctrl
On Mon, Jun 1, 2020 at 4:15 PM Greentime Hu wrote:
>
> Guo Ren 於 2020年5月31日 週日 上午9:56寫道：
> >
> > Hi Greentime,
> >
> > Why remove vxrm and xstat ?
> >
> > > Appendix B: Calling Convention
> > > In the RISC-V psABI, the vector registers v0-v31 are all caller-saved.
> > > The vstart, vl, and vtype
On Mon, 1 Jun 2020, Suravee Suthikulpanit wrote:
> > Moving init_iommu_perf_ctr just after iommu_flush_all_caches resolves
> > the issue. This is the earliest point in amd_iommu_init_pci where the
> > call succeeds on my laptop.
>
> According to your description, it should just need to be anywher
Hi Rich,
On Mon, Jun 1, 2020 at 5:03 AM Rich Felker wrote:
> On Sun, May 31, 2020 at 12:43:11PM +0200, Geert Uytterhoeven wrote:
> > On Sun, May 31, 2020 at 11:59 AM John Paul Adrian Glaubitz
> > wrote:
> > > On 5/31/20 11:54 AM, John Paul Adrian Glaubitz wrote:
> > > > On 5/31/20 11:52 AM, Geer
Hi,
On Mon, Jun 01, 2020 at 09:50:52AM +0100, Srinivas Kandagatla wrote:
>
>
> On 30/05/2020 00:04, Vadym Kochan wrote:
> > ONIE is a small operating system, pre-installed on bare metal network
> > switches, that provides an environment for automated provisioning.
> >
> > This system requires t
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> Follow the riscv vector spec to add new csr number.
>
> [greentime...@sifive.com: update the defined value
On Fri, May 29, 2020 at 08:05:18PM +0200, Thierry Reding wrote:
> On Thu, May 21, 2020 at 10:47:09AM +0800, Dinghao Liu wrote:
> > pm_runtime_get_sync() increments the runtime PM usage counter even
> > when it returns an error code. Thus a pairing decrement is needed on
> > the error handling path
On Mon, Jun 01, 2020 at 12:22:30AM -0700, Ian Rogers wrote:
SNIP
> > +
> > + list = alloc_list();
> > + if (!list)
> > + YYABORT;
> > +
> > + err = parse_events_add_pmu(_parse_state, list, $1, NULL, false,
> > false);
> > + free($1);
> > + if (err < 0)
On Fri 29-05-20 21:37:50, Martijn Coenen wrote:
> Hi Jan,
>
> On Fri, May 29, 2020 at 5:20 PM Jan Kara wrote:
> > I understand. I have written a fix (attached). Currently its under testing
> > together with other cleanups. If everything works fine, I plan to submit
> > the patches on Monday.
>
>
On Mon, Jun 01, 2020 at 12:28:31AM -0700, Ian Rogers wrote:
> On Sun, May 24, 2020 at 3:42 PM Jiri Olsa wrote:
> >
> > Adding parse_events_fake interface to parse events
> > and use fake pmu event in case pmu event is parsed.
> >
> > This way it's possible to parse events from PMUs
> > which are n
Fix some potential memory leaks in error handling branches while
iterating dent entries. For example, function dbg_check_dir()
forgets to free pdent if it exists.
Signed-off-by: Zhihao Cheng
Cc:
Fixes: 1e51764a3c2ac05a2 ("UBIFS: add new flash file system")
---
fs/ubifs/debug.c | 1 +
1 file cha
Fix some potential memory leaks in error handling branches while
iterating xattr entries. For example, function ubifs_tnc_remove_ino()
forgets to free pxent if it exists. Similar problems also exist in
ubifs_purge_xattrs(), ubifs_add_orphan() and ubifs_jnl_write_inode().
Signed-off-by: Zhihao Chen
Following process triggers a memleak caused by forgetting to release the
initial anchor PEB (CONFIG_MTD_UBI_FASTMAP is disabled):
1. attach -> __erase_worker -> produce the initial anchor PEB
2. detach -> ubi_fastmap_close (Do nothing, it should have released the
initial anchor PEB)
Don't produ
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> Add vector state context struct in struct thread and asm-offsets.c
> definitions.
>
> The vector registers
On Mon, 1 Jun 2020 at 07:41, Jarkko Sakkinen
wrote:
>
> On Wed, May 06, 2020 at 03:10:14PM +0530, Sumit Garg wrote:
> > Current trusted keys framework is tightly coupled to use TPM device as
> > an underlying implementation which makes it difficult for implementations
> > like Trusted Execution En
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds task switch support for vector. It supports lazy
> save and restore mechanism. It also supp
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds sigcontext save/restore for vector. The vector registers
> will be saved in datap pointer.
Hello!
On 6/1/20 11:02 AM, Geert Uytterhoeven wrote:
>> Can I propose a different solution? For archs where there isn't
>> actually any 64-bit load or store instruction, does it make sense to
>> be writing asm just to do two 32-bit loads/stores, especially when
>> this code is not in a hot path?
>
A detach hung is possible when a race occurs between the detach process
and the ubi background thread. The following sequences outline the race:
ubi thread: if (list_empty(&ubi->works)...
ubi detach: set_bit(KTHREAD_SHOULD_STOP, &kthread->flags)
=> by kthread_stop()
On Mon, Jun 1, 2020 at 1:11 PM Marc Zyngier wrote:
>
> On 2020-06-01 05:09, Anup Patel wrote:
> > On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-31 11:06, Anup Patel wrote:
>
> [...]
>
> > Also, the PLIC spec is now owned by RISC-V foundation (not SiFive) so
> > we will
Hi Finn,
On Mon, Jun 1, 2020 at 2:15 AM Finn Thain wrote:
> On Sun, 31 May 2020, Geert Uytterhoeven wrote:
> > On Sun, May 31, 2020 at 1:20 AM Finn Thain
> > wrote:
> > > arch/m68k/include/asm/adb_iop.h | 1 +
> > > drivers/macintosh/adb-iop.c | 32 ++--
> >
> >
On 01/06/2020 10:03, Vadym Kochan wrote:
+
+ nvmem = of_nvmem_device_get(np, NULL);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
+
TBH, this looks completely incorrect way to do this and misuse of nvmem
consumer interface.
Ideally nvmem provider driver should popul
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch is used to detect vector support status of CPU and use
> riscv_vsize to save the size of all the
On Fri, 29 May 2020, Philippe CORNU wrote:
Hi Adrian, and thank you very much for the patchset. Thank you
also for having tested it on STM32F769 and STM32MP1. Sorry for
the late response, Yannick and I will review it as soon as
possible and we will keep you posted. Note: Do not hesitate to
On Sun, May 31, 2020 at 12:13:18PM -0400, Keno Fischer wrote:
> > Keno -- are you planning to send out a patch? You previously spoke about
> > implementing this using PTRACE_SETOPTIONS.
>
> Yes, I'll have a patch for you. Though I've come to the conclusion
> that introducing a new regset is probab
Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> This patch adds ptrace support for riscv vector. The vector registers will
> be saved in datap pointer of _
The RISC-V per-HART local interrupt controller manages software
interrupts, timer interrupts, external interrupts (which are routed
via the platform level interrupt controller) and other per-HART
local interrupts.
We add a driver for the RISC-V local interrupt controller, which
eventually replaces
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/include/asm
The only thing do_IRQ() does is call handle_arch_irq function
pointer. We can very well call handle_arch_irq function pointer
directly from assembly and remove do_IRQ() function hence this
patch.
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/kernel/entry.S | 4 +++-
arch/ris
Hi Chao,
Can you please help review below diff given by Jaegeuk?
If it looks good, I can send a v2.
Thanks,
On Thu, May 28, 2020 at 12:18:39PM -0700, Jaegeuk Kim wrote:
> On 05/28, Chao Yu wrote:
> > On 2020/5/28 10:45, Chao Yu wrote:
> > > On 2020/5/27 10:20, Sahitya Tummala wrote:
> > >> In ca
The RISC-V per-HART local interrupt controller driver is mandatory
for all RISC-V system (with/without MMU) hence we force select it
for CONFIG_RISCV (just like RISCV_TIMER).
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --
Currently, the IPI handling routine riscv_software_interrupt() does
not take any argument and also does not perform irq_enter()/irq_exit().
This patch makes IPI handling routine more self-contained by:
1. Passing "pt_regs *" argument
2. Explicitly doing irq_enter()/irq_exit()
3. Explicitly save/re
The plic_find_hart_id() can be useful to other interrupt controller
drivers (such as RISC-V local interrupt driver) so we rename this
function to riscv_of_parent_hartid() and place it in arch directory
along with riscv_of_processor_hartid().
Signed-off-by: Anup Patel
Reviewed-by: Atish Patra
Rev
This patchset provides a new RISC-V Local Interrupt Controller Driver
for managing per-CPU local interrupts. The overall approach is inspired
from the way per-CPU local interrupts are handled by Linux ARM64 and
ARM GICv3 driver.
It is a major re-write over perviously submitted version.
(Refer, htt
Below is the list of build error/warning regressions/improvements in
v5.7[1] compared to v5.6[2].
Summarized:
- build errors: +4/-8
- build warnings: +51/-253
JFYI, when comparing v5.7[1] to v5.7-rc7[3], the summaries are:
- build errors: +0/-0
- build warnings: +0/-0
Note that there may
Create the 'sysfs' attributes according to configuration provided
through the capability register, which purpose is to indicate the
actual number of the components within the particular group.
Such components could be, for example the FAN or power supply units.
The motivation is to avoid adding a n
Add new field 'regnum' to the structure 'mlxreg_core_data' to specify
the number of registers occupied by multi-register attribute.
Signed-off-by: Vadim Pasternak
---
include/linux/platform_data/mlxreg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/platform_data/mlxreg.h
Add support for attributes composed from few registers.
Such attributes could occupy from 2 to 4 sequential registers.
For word size register space complex attribute can occupy up to two
register, for byte size - up to four. These attributes can carry, for
example, CPLD or FPGA versioning, power co
Add documentation for the new attributes for exposing CPLDs part
numbers and CPLD minor versions.
Signed-off-by: Vadim Pasternak
---
Documentation/ABI/stable/sysfs-driver-mlxreg-io | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg
The patchset adds new features for the existing Mellanox systems.
Patch #1 allows to configure number of hotplug 'sysfs' attributes for
the particular system class according to the hardware data for
the specific system from this class, instead of configuring it
Add new field 'reg_prsnt' to the structure 'mlxreg_core_data' to
provide the number FAN drawers equpped within the system. The purpose
is to allow mapping between FAN drawers and FAN rotors (tachometer),
since FAN drawer can be eqipped with a few rotors.
Signed-off-by: Vadim Pasternak
---
includ
Extend FAN platform data with register presence field.
Add register present entry per rotor (tachometer) description tuple.
The purpose is to allow indication of FAN presence.
Signed-off-by: Vadim Pasternak
---
drivers/platform/x86/mlx-platform.c | 13 +
1 file changed, 13 insertions
> Uninterruptible context is not needed in the driver and causes lockdep
> warning because of mutex taken in of_alias_get_id().
Was a spin lock taken?
> Convert the lock to mutex to avoid the issue.
Would you like to add the tag “Fixes” to the commit message?
Regards,
Markus
Add new attributes for the all type systems specifying for each
equipped CPLD device, the CPLD part number and the CPLD minor version
of the device: 'cpld{n}_pn' and 'cpld{n}_version_min'.
This information is to be used for mathcing the current CPLD image and
for making decision if image upgrade is
Send "udev" event with environmental data in order to allow handling
"ENV{}" variables in "udev" rules.
Signed-off-by: Vadim Pasternak
---
drivers/platform/mellanox/mlxreg-hotplug.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/
Hi Chao,
Can you please help review the diff given by Jaegeuk below?
If it looks good, I can post a v2.
Thanks,
On Thu, May 28, 2020 at 12:18:39PM -0700, Jaegeuk Kim wrote:
> On 05/28, Chao Yu wrote:
> > On 2020/5/28 10:45, Chao Yu wrote:
> > > On 2020/5/27 10:20, Sahitya Tummala wrote:
> > >> I
On 5/29/20 6:43 PM, Daniel Lezcano wrote:
On 27/05/2020 11:58, Lukasz Luba wrote:
The Energy Model framework is going to support devices other that CPUs. In
order to make this happen change the callback function and add pointer to
a device as an argument.
Update the related users to use new
On 31/05/20 14:44, Marc Zyngier wrote:
>>
>> Is there an ARM-approved way to reuse the S2 fault syndromes to detect
>> async page faults?
>
> It would mean being able to set an ESR_EL2 register value into ESR_EL1,
> and there is nothing in the architecture that would allow that,
I understand that
sysnames should be freed after refcnt being decreased to zero in
afs_put_sysnames(). Besides, it would be better set net->sysnames
to 'NULL' after net->sysnames being released if afs_put_sysnames()
aims on an afs_sysnames object.
Signed-off-by: Zhihao Cheng
Cc: # v4.17+
Fixes: 6f8880d8e681557 ("
> On May 30, 2020, at 5:26 PM, Gabriel Krisman Bertazi
> wrote:
>
> Andy Lutomirski writes:
>
On May 29, 2020, at 11:00 PM, Gabriel Krisman Bertazi
wrote:
>>>
>>> Modern Windows applications are executing system call instructions
>>> directly from the application's code without goi
On Sun, May 31, 2020 at 12:20:51PM -0400, Keno Fischer wrote:
> > Can't PTRACE_SYSEMU be emulated by using PTRACE_SYSCALL, cancelling the
> > syscall at the syscall enter stop, then modifying the regs at the
> > syscall exit stop?
>
> Yes, it can. The idea behind SYSEMU is to be able to save half
On Mon, Jun 1, 2020 at 5:14 AM Dave Martin wrote:
> Can you explain why userspace would write a changed value for x7
> but at the same time need that new to be thrown away?
The discarding behavior is the primary reason things aren't completely
broken at the moment. If it read the wrong x7 value a
On 26/05/2020 23:31, Doug Anderson wrote:
Hi,
On Fri, May 22, 2020 at 4:18 AM Srinivas Kandagatla
wrote:
On 21/05/2020 22:28, Doug Anderson wrote:
Hi,
On Thu, May 21, 2020 at 8:56 AM Srinivas Kandagatla
wrote:
On 21/05/2020 16:10, Doug Anderson wrote:
On 20/05/2020 23:48, Doug Anders
On Sun 31-05-20 14:16:01, Pavel Machek wrote:
> On Thu 2020-05-28 14:07:50, Michal Hocko wrote:
> > On Thu 28-05-20 14:03:54, Pavel Machek wrote:
> > > On Thu 2020-05-28 11:05:17, Michal Hocko wrote:
> > > > On Tue 26-05-20 11:10:54, Pavel Machek wrote:
> > > > [...]
> > > > > [38617.276517] oom_re
Hi Linus,
just a single fix this time. Please pull,
thx.
---
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
tags/x86_m
On 29/05/2020 22:38, John Stultz wrote:
Fixes the following kCFI crash seen on db845c, caused
by the function prototypes not matching the callback
function prototype.
[ 82.585661] Unable to handle kernel NULL pointer dereference at virtual
address 0001
[ 82.595387] Mem abort
Hi Pavel and Dan,
On 5/31/20 9:06 PM, Pavel Machek wrote:
Hi!
+ There can only be one instance of the ti,led-bank
+ property for each device node. This is a required node is the LED
+ modules are to be backed.
I don't understand the second sentence. Pretty sure it
Hi Anup,
On Mon, Jun 1, 2020 at 12:09 PM Anup Patel wrote:
>
> On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
> >
> > On 2020-05-31 11:06, Anup Patel wrote:
> > > On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
> > >>
> > >> On 2020-05-31 06:36, Anup Patel wrote:
> > >> > On Sat, May 3
Hi Sergei,
On Mon, 1 Jun 2020 at 10:51, Sergei Shtylyov
wrote:
>
> Hello!
>
> On 31.05.2020 21:07, Vladimir Oltean wrote:
>
> > From: Vladimir Oltean
> >
> > Sometimes debugging a device is easiest using devmem on its register
> > map, and that can be seen with /proc/iomem. But some device drive
Hi Chanwoo,
On 31.05.2020 02:01, Chanwoo Choi wrote:
> On Sat, May 30, 2020 at 1:32 AM Sylwester Nawrocki
> wrote:
>>
>> Add documentation for new optional properties in the exynos bus nodes:
>> samsung,interconnect-parent, #interconnect-cells.
>> These properties allow to specify the SoC interco
On Mon, Jun 1, 2020 at 5:23 AM Dave Martin wrote:
> > > Can't PTRACE_SYSEMU be emulated by using PTRACE_SYSCALL, cancelling the
> > > syscall at the syscall enter stop, then modifying the regs at the
> > > syscall exit stop?
> >
> > Yes, it can. The idea behind SYSEMU is to be able to save half th
> From: Peng Fan
> Sent: Monday, June 1, 2020 4:20 PM
>
> Add mu node to let A53 could communicate with M Core.
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Aisheng
Add devicetree bindings for a Arm PSA FF-A compliant non-secure partition
at virtual interface(VMs).
Signed-off-by: Sudeep Holla
---
.../devicetree/bindings/arm/arm,psa-ffa.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/
This is just an example non-secure VM partition to show how to create
the device and use the PSA FF-A interface APIs.
Signed-off-by: Sudeep Holla
---
drivers/firmware/arm_psa_ffa/Kconfig | 7 +++
drivers/firmware/arm_psa_ffa/Makefile| 1 +
drivers/firmware/arm_psa_ffa/partition.c | 71
Hi All,
Sorry for posting in the middle of merge window and I must have done
this last week itself. This is not the driver I had thought about posting
last week. After I started cleaning up and looking at Will's KVM prototype[1]
for PSA FF-A (previously known as SPCI), I got more doubts on alignme
Initial support for PSA FF-A interface providing APIs for non-secure VM
partitions.
Signed-off-by: Sudeep Holla
---
drivers/firmware/Kconfig | 1 +
drivers/firmware/Makefile | 1 +
drivers/firmware/arm_psa_ffa/Kconfig | 15 ++
drivers/firmware/arm_psa_ffa/Makefile
On 2020-06-01 10:15, Anup Patel wrote:
The RISC-V per-HART local interrupt controller manages software
interrupts, timer interrupts, external interrupts (which are routed
via the platform level interrupt controller) and other per-HART
local interrupts.
We add a driver for the RISC-V local interr
On 2020-06-01 10:15, Anup Patel wrote:
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
Reviewed-by:
On Mon, Jun 01, 2020 at 12:36:08PM +0300, Vladimir Oltean wrote:
> Hi Sergei,
>
> On Mon, 1 Jun 2020 at 10:51, Sergei Shtylyov
> wrote:
> >
> > Hello!
> >
> > On 31.05.2020 21:07, Vladimir Oltean wrote:
> >
> > > From: Vladimir Oltean
> > >
> > > Sometimes debugging a device is easiest using dev
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 19a1f5ec699954d21be10f74ff71c2a7079e99ad
Gitweb:
https://git.kernel.org/tip/19a1f5ec699954d21be10f74ff71c2a7079e99ad
Author:Peter Zijlstra
AuthorDate:Tue, 26 May 2020 18:10:58 +02:00
Committ
The following commit has been merged into the locking/core branch of tip:
Commit-ID: 91710728d1725de51d06b40674abf6e860d592c7
Gitweb:
https://git.kernel.org/tip/91710728d1725de51d06b40674abf6e860d592c7
Author:Thomas Gleixner
AuthorDate:Wed, 27 May 2020 22:11:13 +02:00
Comm
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 52103be07d8b08311955f8c30e535c2dda290cf4
Gitweb:
https://git.kernel.org/tip/52103be07d8b08311955f8c30e535c2dda290cf4
Author:Peter Zijlstra
AuthorDate:Tue, 26 May 2020 18:10:59 +02:00
Committ
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 4b44a21dd640b692d4e9b12d3e37c24825f90baa
Gitweb:
https://git.kernel.org/tip/4b44a21dd640b692d4e9b12d3e37c24825f90baa
Author:Peter Zijlstra
AuthorDate:Tue, 26 May 2020 18:11:02 +02:00
Committ
The following commit has been merged into the locking/core branch of tip:
Commit-ID: ed19f19256be2949af1ab5634e62178d30a355c2
Gitweb:
https://git.kernel.org/tip/ed19f19256be2949af1ab5634e62178d30a355c2
Author:Sebastian Andrzej Siewior
AuthorDate:Wed, 27 May 2020 22:11:18 +
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 1f8db4150536431b031585ecc2a6793f69245de2
Gitweb:
https://git.kernel.org/tip/1f8db4150536431b031585ecc2a6793f69245de2
Author:Ingo Molnar
AuthorDate:Thu, 28 May 2020 11:01:34 +02:00
Committer:
The following commit has been merged into the locking/core branch of tip:
Commit-ID: cfa6705d89b6562f79c40c249f8d94073c4276e4
Gitweb:
https://git.kernel.org/tip/cfa6705d89b6562f79c40c249f8d94073c4276e4
Author:Sebastian Andrzej Siewior
AuthorDate:Wed, 27 May 2020 22:11:14 +
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