From: Uwe Kleine-König
commit 1866541492641c02874bf51f9d8712b5510f2c64 upstream
When using RS485 half duplex the Transmitter Complete irq is needed to
determine the moment when the transmitter can be disabled. When using
DMA this irq must only be enabled when DMA has completed to transfer all
Hi Wang,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on linux/master v5.7]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base'
This is an add-on series to the main SoC Sparx5 series
(Message-ID: <20200608123024.5330-1-lars.povl...@microchip.com>)
Changes in v2:
- Changes in driver as per review comments
Lars Povlsen (3):
dt-bindings: hwmon: Add Sparx5 temperature sensor
arm64: dts: sparx5: Add hwmon temperature
On Mon, Jun 8, 2020 at 11:45 PM Marco Felsch wrote:
>
> On 20-06-08 13:11, Andrzej Hajda wrote:
> >
> > On 08.06.2020 11:17, Marco Felsch wrote:
> > > On 20-03-26 18:31, Andy Shevchenko wrote:
> > >> On Thu, Mar 26, 2020 at 03:01:22PM +, Grant Likely wrote:
> > >>> On 25/03/2020 12:51, Andy
On Mon, 2020-06-08 at 14:51 +0200, Vitaly Kuznetsov wrote:
> Paolo Bonzini writes:
>
> > is_intercept takes an INTERCEPT_* constant, not SVM_EXIT_*; because
> > of this, the compiler was removing the body of the conditionals,
> > as if is_intercept returned 0.
> >
> > This unveils a latent bug:
Add maintainers to rockchip nfc.
Signed-off-by: Yifeng Zhao
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Support building i.MX8MP clock driver as module.
Signed-off-by: Anson Huang
---
No change.
---
drivers/clk/imx/Kconfig | 2 +-
drivers/clk/imx/clk-imx8mp.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index
There are more and more requirements of building SoC specific drivers
as modules, add support for building i.MX common clock driver as module
to meet the requirement.
Signed-off-by: Anson Huang
---
Changes since V1:
- move scu lpcg driver change to SCU patch.
---
drivers/clk/imx/Kconfig
Hi Nicolas,
On 08/06/2020 20:59, Nicolas Dufresne wrote:
> Le lundi 08 juin 2020 à 16:43 +0200, Hans Verkuil a écrit :
>> On 08/06/2020 16:14, Neil Armstrong wrote:
>>> On 08/06/2020 11:26, Hans Verkuil wrote:
On 08/06/2020 10:16, Neil Armstrong wrote:
> Hi Nicolas,
>
> On
Support building i.MX8MQ clock driver as module.
Signed-off-by: Anson Huang
---
No change.
---
drivers/clk/imx/Kconfig | 2 +-
drivers/clk/imx/clk-imx8mq.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index
i.MX common clock drivers may support module build, so it is NOT
selected by default, for ARCH_MXC ARMv7 platforms, need to select
it manually to make build pass.
Signed-off-by: Anson Huang
---
No change.
---
arch/arm/mach-imx/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
There are more and more requirements of building SoC specific drivers
as modules, add support for building SCU clock driver as module to meet
the requirement.
Signed-off-by: Anson Huang
---
Changes since V1:
- add ARCH_MXC to build dependency to avoid build fail on x86 arch;
-
Nowdays, there are more and more requirements of building SoC specific drivers
as modules, such as Android GKI (generic kernel image), this patch set supports
building i.MX8 SoCs clock drivers as modules, including i.MX8MQ/MM/MN/MP/QXP,
the common clock modules are: mxc-clk.ko for
Export clk_hw_register_composite() to support user built as module.
ERROR: modpost: "clk_hw_register_composite" [drivers/clk/imx/mxc-clk.ko]
undefined!
scripts/Makefile.modpost:111: recipe for target 'Module.symvers' failed
make[1]: *** [Module.symvers] Error 1
make[1]: *** Deleting file
Support building i.MX8MM clock driver as module.
Signed-off-by: Anson Huang
---
No change.
---
drivers/clk/imx/Kconfig | 2 +-
drivers/clk/imx/clk-imx8mm.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index
Support building i.MX8MN clock driver as module.
Signed-off-by: Anson Huang
---
No change.
---
drivers/clk/imx/Kconfig | 2 +-
drivers/clk/imx/clk-imx8mn.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index
Support building i.MX8QXP clock driver as module.
Signed-off-by: Anson Huang
---
No change.
---
drivers/clk/imx/Kconfig| 2 +-
drivers/clk/imx/clk-imx8qxp-lpcg.c | 1 +
drivers/clk/imx/clk-imx8qxp.c | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git
On Mon, Jun 08, 2020 at 08:42:21PM -0700, Andrei Vagin wrote:
> On Wed, Jun 03, 2020 at 06:23:26PM +0200, Adrian Reber wrote:
> > This patch introduces CAP_CHECKPOINT_RESTORE, a new capability facilitating
> > checkpoint/restore for non-root users.
> >
> > Over the last years, The CRIU
On Sun, Jun 07, 2020 at 12:20:53PM +0900, Masahiro Yamada wrote:
> Even after commit c624adc9cb6e ("samples: fix binderfs sample"), this
> sample is never compiled.
>
> 'hostprogs' teaches Kbuild that this is a host program, but not enough
> to order to compile it. You must add it to 'always-y'
From: Yifeng Zhao
Add nfc(nand flash controller) node for RK3308 Soc.
Signed-off-by: Yifeng Zhao
Signed-off-by: Yifeng Zhao
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 15 +++
Rockchp's NFC(Nand Flash Controller) has four versions: V600, V622, V800 and
V900.
This series patch can support all four versions.
Changes in v6:
- Fix some wrong define
- Modified the definition of compatible
- The mtd->name set by NAND label property.
- Add some comments.
- Fix compile
Documentation support for Rockchip RK3xxx NAND flash controllers
Signed-off-by: Yifeng Zhao
---
Changes in v6:
- Fix some wrong define
- Modified the definition of compatible
Changes in v5:
- Fix some wrong define
- Add boot-medium define
- Remove some compatible define
Changes in v4:
- The
This driver supports Rockchip NFC (NAND Flash Controller) found on RK3308,
RK2928, RKPX30, RV1108 and other SOCs. The driver has been tested using
8-bit NAND interface on the ARM based RK3308 platform.
Support Rockchip SoCs and NFC versions:
- PX30 and RK3326(NFCv900).
ECC: 16/40/60/70
Add nfc(nand flash controller) node for PX30 Soc.
Signed-off-by: Yifeng Zhao
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/px30.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git
This add the DT binding specification for the Sparx5 temperature
sensor.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
.../bindings/hwmon/microchip,sparx5-temp.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode 100644
This adds a hwmon temperature node sensor to the Sparx5 SoC.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
Add nfc(nand flash controller) node for RV1108 Soc.
Signed-off-by: Yifeng Zhao
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git
Add nfc(nand flash controller) node for RK3036 Soc.
Signed-off-by: Yifeng Zhao
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3036.dtsi | 52 +++
1 file changed, 52 insertions(+)
diff
Add nfc(nand flash controller) node for RK2928, RK3066, RK3168
and RK3188 Soc.
Signed-off-by: Yifeng Zhao
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3xxx.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
This patch adds a temperature sensor driver to the Sparx5 SoC.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
drivers/hwmon/Kconfig | 10 +++
drivers/hwmon/Makefile | 2 +-
drivers/hwmon/sparx5-temp.c | 152
3 files changed,
On Tue, Jun 9, 2020 at 8:20 AM Greg Kroah-Hartman
wrote:
>
> On Sun, Jun 07, 2020 at 07:02:56PM -0700, Guenter Roeck wrote:
> > Hi,
> >
> > On Mon, May 11, 2020 at 01:21:49PM +0900, Masahiro Yamada wrote:
> > > I think all the warnings have been fixed by now. Make it a fatal error.
> > >
> >
> >
Write multiple sectors at once when updating dir-entries.
Add exfat_update_bhs() for that. It wait for write completion once
instead of sector by sector.
It's only effective if sync enabled.
Suggested-by: Namjae Jeon
Signed-off-by: Tetsuhiro Kohada
---
Changes in v2:
- Split into 'write
Add error check when synchronously updating dir-entries.
Suggested-by: Namjae Jeon
Suggested-by: Sungjong Seo
Signed-off-by: Tetsuhiro Kohada
---
Changes in v2:
- Split into 'write multiple sectors at once'
and 'add error check when updating dir-entries'
fs/exfat/dir.c | 3 ++-
wt., 9 cze 2020 o 02:23 Kent Gibson napisał(a):
>
> On Tue, Dec 24, 2019 at 01:07:08PM +0100, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
>
> [snip!]
>
> > +static int lineinfo_changed_notify(struct notifier_block *nb,
> > +unsigned long action,
On Tue, Jun 09, 2020 at 09:51:46AM +0200, Arnd Bergmann wrote:
> On Tue, Jun 9, 2020 at 8:20 AM Greg Kroah-Hartman
> wrote:
> >
> > On Sun, Jun 07, 2020 at 07:02:56PM -0700, Guenter Roeck wrote:
> > > Hi,
> > >
> > > On Mon, May 11, 2020 at 01:21:49PM +0900, Masahiro Yamada wrote:
> > > > I think
Add support for controlling voltage regulator that is connected and
controlled by ChromeOS EC. Kernel controls these regulators through
newly added EC host commands.
Pi-Hsun Shih (2):
dt-bindings: regulator: Add DT binding for cros-ec-regulator
regulator: Add driver for cros-ec-regulator
Add DT binding documentation for cros-ec-regulator, a voltage regulator
controlled by ChromeOS EC.
Signed-off-by: Pi-Hsun Shih
---
.../bindings/regulator/cros-ec-regulator.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode 100644
Add driver for cros-ec-regulator, representing a voltage regulator that
is connected and controlled by ChromeOS EC, and is controlled by kernel
with EC host commands.
Signed-off-by: Pi-Hsun Shih
---
This patch contains function cros_ec_cmd that is copied from the series:
sob., 6 cze 2020 o 03:56 Kent Gibson napisał(a):
>
[snip!]
> >
> > I'd say yes - consolidation and reuse of data structures is always
> > good and normally they are going to be wrapped in some kind of
> > low-level user-space library anyway.
> >
>
> Ok, and I've changed the values field name to
On Monday 08 June 2020 15:40:53 mario.limoncie...@dell.com wrote:
> > dell_wmi: Unknown WMI event type 0x12
> > dell_wmi: Unknown key with type 0x0012 and code 0xe035 pressed
>
> Event type 0x12 is for "System Events". This is the type of events that
> you typically would see come in for things
On Tue, 09 Jun 2020 07:43:06 +0200,
Christoph Hellwig wrote:
>
> On Mon, Jun 08, 2020 at 07:31:47PM -0700, David Rientjes wrote:
> > On Mon, 8 Jun 2020, Alex Xu (Hello71) wrote:
> >
> > > Excerpts from Christoph Hellwig's message of June 8, 2020 2:19 am:
> > > > Can you do a listing using gdb
Hi Yang,
> On Jun 5, 2020, at 6:01 AM, Yang Yingliang wrote:
>
> There is a null-ptr-deref in hfs_find_init():
>
> [ 107.092729] hfs: continuing without an alternate MDB
> [ 107.097632] general protection fault, probably for non-canonical address
> 0xdc08: [#1] SMP KASAN
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
MAINTAINERS
This adds support for the Microchip Sparx5 ARMv8-based SoC family of
TSN-capable gigabit switches.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 8
arch/arm64/Kconfig.platforms | 14 ++
2 files changed, 22 insertions(+)
This add pinctrl support to the Microchip Sparx5 SoC.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 26 +++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
This adds the main Sparx5 SoC DT documentation file, with information
abut the supported board types.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
.../bindings/arm/microchip,sparx5.yaml| 65 +++
.../devicetree/bindings/mfd/syscon.yaml | 1 +
2
This add support for Sparx5 pinctrl, using the ocelot drives as
basis. It adds pinconfig support as well, as supported by the
platform.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
drivers/pinctrl/pinctrl-ocelot.c | 431 ++-
1 file changed, 430
The Sparx5 support 9 different clock outputs. This include file has
defines for each supported clock ordinal.
Reviewed-by: Stephen Boyd
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
include/dt-bindings/clock/microchip,sparx5.h | 23
1 file changed, 23
On Mon, Jun 08, 2020 at 09:07:23PM -0700, Josh Snyder wrote:
> Previously, io_ticks could be under-counted. Consider these I/Os along
> the time axis (in jiffies):
>
> t 012345678
> io1||
> io2|---|
In current way, when io2 is done, io tickes should be 5,
This add the DT bindings documentation for the Sparx5 SoC DPLL clock
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
.../bindings/clock/microchip,sparx5-dpll.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644
This patch adds i2c devices and muxes to the Sparx5 reference boards.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 36 +++
.../boot/dts/microchip/sparx5_pcb125.dts | 4 +
.../dts/microchip/sparx5_pcb134_board.dtsi|
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 37 ++-
1 file changed, 23
This adds a device driver for the Sparx5 SoC DPLL clock
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-sparx5.c | 312 +++
2 files changed, 313 insertions(+)
create mode 100644
On 09/06/20 09:30, Maxim Levitsky wrote:
> And if I understand correctly that bug didn't affect anything I tested
> because your recent patches started to avoid the usage of the interrupt
> window unless L1 clears the usage of the interrupt intercept which is
> rare.
>
> Looks correct to me, and
Add error check when synchronously updating dir-entries.
Furthermore, add exfat_update_bhs(). It wait for write completion once
instead of sector by sector.
This patch can be split into two also ?
I sent a patch split into 'write multiple sectors at once'
and 'add error check when updating
Correct the SoC revision and package bits/mask values for S905D3/X3 to detect
a wider range of observed SoC IDs, and tweak sort order for A311D/S922X.
S905X3 05 0101 (SEI610 initial devices)
S905X3 10 0001 (ODROID-C4 and recent Android boxes)
S905X3 50 0101 (SEI610 later
Fix typo in comment for cross timestamping structure:
syncronized -> synchronized.
Signed-off-by: Kurt Kanzenbach
---
include/linux/timekeeping.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h
index
On Tue, Jun 9, 2020 at 4:07 AM Jason Yan wrote:
>
> In blkdev_get() we call __blkdev_get() to do some internal jobs and if
> there is some errors in __blkdev_get(), the bdput() is called which
> means we have released the refcount of the bdev (actually the refcount of
> the bdev inode). This
On 09.06.20 09:23, Schrempf Frieder wrote:
> From: Uwe Kleine-König
>
> commit 1866541492641c02874bf51f9d8712b5510f2c64 upstream
>
> When using RS485 half duplex the Transmitter Complete irq is needed to
> determine the moment when the transmitter can be disabled. When using
> DMA this irq must
On Monday 08 June 2020 20:58:38 mario.limoncie...@dell.com wrote:
> > -Original Message-
> > From: platform-driver-x86-ow...@vger.kernel.org > ow...@vger.kernel.org> On Behalf Of Pali Rohár
> > Sent: Monday, June 8, 2020 3:48 PM
> > To: Limonciello, Mario
> > Cc: y.li...@paritcher.com;
For mono channel, ssi will switch to normal mode. In normal
mode, the Word Length Control bits control the word length
divider in clock generator, which is different with I2S master
mode, the word length is fixed to 32bit.
So we refine the famula for mono channel, otherwise there
will be sound
Hi Sibi,
Thanks for the review.
On 2020-06-05 17:10, Sibi Sankar wrote:
Hey Pradeep,
Thanks for the patch.
On 2020-06-05 15:00, Pradeep P V K wrote:
Interconnect bandwidth scaling support is now added as a
part of OPP [1]. So, make sure interconnect driver is ready
can you please replace
Hi,
On 6/6/2020 11:05 PM, Pavel Machek wrote:
> Hi!
>
>>> We don't really need if/else to set variable to 1/0.
>>>
>>> Signed-off-by: Pavel Machek (CIP)
>>>
>>> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
>>> index 12b98b466287..f9f6fd470c81 100644
>>> ---
On Monday 08 June 2020 20:43:45 Y Paritcher wrote:
> On 6/8/20 7:55 PM, Pali Rohár wrote:
> > Hello!
> >
> > On Monday 08 June 2020 16:27:10 Randy Dunlap wrote:
> >> Hi--
> >>
> >> On 6/8/20 4:05 PM, Y Paritcher wrote:
> >>> Increase length of bios_to_linux_keycode to 2 bytes (the true size of a
Add interconnect bandwidth scaling supported strings for qcom-sdhci
controller.
Signed-off-by: Pradeep P V K
Acked-by: Rob Herring
Reviewed-by: Bjorn Andersson
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 18 ++
1 file changed, 18 insertions(+)
diff --git
Add interconnect bandwidths for SDHC driver using OPP framework that
is required by SDHC driver based on the clock frequency and bus width
of the card. Otherwise, the system clocks may run at minimum clock
speed and thus affecting the performance.
This change is based on
[1] [Patch v8]
Interconnect bandwidth scaling support is now added as a
part of OPP. So, make sure interconnect driver is ready
before handling interconnect scaling.
Signed-off-by: Pradeep P V K
Reviewed-by: Sibi Sankar
---
This change is based on
[1] [Patch v8] Introduce OPP bandwidth bindings
On Tue, 9 Jun 2020 09:49:40 +0200
Lars Povlsen wrote:
> This patch adds a temperature sensor driver to the Sparx5 SoC.
>
> Reviewed-by: Alexandre Belloni
> Signed-off-by: Lars Povlsen
Hi. Quick drive by review whilst waiting for coffee time...
A few minor suggestions inline.
Thanks,
On Monday 08 June 2020 20:57:38 Y Paritcher wrote:
> On 6/8/20 8:26 PM, mario.limoncie...@dell.com wrote:
> >> -Original Message-
> >> From: Pali Rohár
> >> Sent: Monday, June 8, 2020 6:33 PM
> >> To: Y Paritcher
> >> Cc: linux-kernel@vger.kernel.org; platform-driver-...@vger.kernel.org;
From: xidongwang
ib_uverbs_create_ah() may copy stack allocated
structs to userspace without initializing all members of these
structs. Clear out this memory to prevent information leaks.
Signed-off-by: xidongwang
---
drivers/infiniband/core/uverbs_cmd.c | 1 +
1 file changed, 1 insertion(+)
On Tue, Jun 09, 2020 at 10:05:26AM +0200, Takashi Iwai wrote:
> > >From the disassembly it seems like a vmalloc allocation is NULL, which
> > seems really weird as this patch shouldn't make a difference for them,
> > and I also only see a single places that allocates the field, and that
> > checks
On Tue, Jun 9, 2020 at 4:52 PM Arnd Bergmann wrote:
>
> On Tue, Jun 9, 2020 at 8:20 AM Greg Kroah-Hartman
> wrote:
> >
> > On Sun, Jun 07, 2020 at 07:02:56PM -0700, Guenter Roeck wrote:
> > > Hi,
> > >
> > > On Mon, May 11, 2020 at 01:21:49PM +0900, Masahiro Yamada wrote:
> > > > I think all the
Hi Linus,
This is exfat update pull request for v5.8-rc1. I add description of
this pull request on below. Please pull exfat with following ones.
Thanks!
The following changes since commit 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162:
Linux 5.7 (2020-05-31 16:49:15 -0700)
are available in the
Some PHYs provide Signal Quality Index (SQI) if the link is in active
state. This information can help to diagnose cable and system design
related issues.
Signed-off-by: Oleksij Rempel
Reviewed-by: Florian Fainelli
Reviewed-by: Michal Kubecek
---
netlink/desc-ethtool.c | 2 ++
Update to net-dev:
dc0f3ed1973 ("net: phy: at803x: add cable diagnostics support for ATH9331 and
ATH8032")
Signed-off-by: Oleksij Rempel
---
uapi/linux/ethtool.h | 25 ++-
uapi/linux/ethtool_netlink.h | 326 +++
uapi/linux/genetlink.h | 2 +
On 09.06.20 08:53, SeongJae Park wrote:
> From: SeongJae Park
>
> In many cases, users might use DAMON for simple data access aware
> memory management optimizations such as applying an operation scheme to
> a memory region of a specific size having a specific access frequency
> for a specific
This patch set is extending ethtool to make it more usable on automotive
PHYs like NXP TJA11XX.
They make use of new KAPI (currently in net-next, will go probably to the
kernel 5.8-rc1):
- PHY master-slave role configuration and status informaton. Mostly needed
for 100Base-T1 PHYs due the lack
This UAPI is needed for BroadR-Reach 100BASE-T1 devices. Due to lack of
auto-negotiation support, we needed to be able to configure the
MASTER-SLAVE role of the port manually or from an application in user
space.
The same UAPI can be used for 1000BASE-T or MultiGBASE-T devices to
force MASTER or
This series adds basic support for SoundWire 1.2.
Pierre-Louis Bossart (4):
soundwire: add definitions for 1.2 spec
soundwire: bus_type: convert open-coded while() to for() loop
soundwire: extend SDW_SLAVE_ENTRY
soundwire: bus: initialize bus clock base and scale registers
From: Pierre-Louis Bossart
Add definitions for register offsets and bit fields from the MIPI
SoundWire 1.2 specification (available to MIPI members at
https://members.mipi.org/wg/All-Members/document/download/78371)
Signed-off-by: Pierre-Louis Bossart
Reviewed-by: Kai Vehmanen
Signed-off-by:
From: Pierre-Louis Bossart
No functionality change, just more structured code.
Suggested-by: Guennadi Liakhovetski
Signed-off-by: Pierre-Louis Bossart
Reviewed-by: Rander Wang
Reviewed-by: Guennadi Liakhovetski
Signed-off-by: Bard Liao
---
drivers/soundwire/bus_type.c | 6 ++
1 file
From: Pierre-Louis Bossart
The SoundWire 1.2 specification adds new capabilities that were not
present in previous version, such as the class ID.
To enable support for class drivers, and well as drivers that address
a specific version, all fields of the sdw_device_id structure need to
be
From: Pierre-Louis Bossart
The SoundWire 1.2 specification adds new registers to allow for
seamless clock changes while audio transfers are on-going. Program
them following the specification.
Note that dynamic clock changes are not supported for now, this only
adds the register initialization.
> Write multiple sectors at once when updating dir-entries.
> Add exfat_update_bhs() for that. It wait for write completion once instead of
> sector by sector.
> It's only effective if sync enabled.
>
> Suggested-by: Namjae Jeon
> Signed-off-by: Tetsuhiro Kohada
> ---
> Changes in v2:
> -
On Mon, Jun 08, 2020 at 09:07:24PM -0700, Josh Snyder wrote:
> Previously, we performed truncation of I/O issue/completion times during
> calculation of io_ticks, counting only I/Os which cross a jiffy
> boundary. The effect is a sampling of I/Os: at every boundary between
> jiffies we ask "is
On Tuesday 09 June 2020 00:26:45 mario.limoncie...@dell.com wrote:
> > Mario, are you able to get some official documentation for these 0x0012
> > event types? I think it could be really useful for community so they can
> > understand and add easily new type of code and events. Because currently
>
Hello,
Does the lock taken on line 38 need to be released on line 53?
julia
-- Forwarded message --
Date: Tue, 9 Jun 2020 16:19:41 +0800
From: kernel test robot
To: kbu...@lists.01.org
Cc: l...@intel.com, Julia Lawall
Subject: drivers/staging/wfx/hif_tx.c:53:2-8: preceding
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: d8ad6d39c35d2b44b3d48b787df7f3359381dcbf
Gitweb:
https://git.kernel.org/tip/d8ad6d39c35d2b44b3d48b787df7f3359381dcbf
Author:Bob Haarman
AuthorDate:Tue, 02 Jun 2020 12:30:59 -07:00
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: dbbe2ad02e9df26e372f38cc3e70dab9222c832e
Gitweb:
https://git.kernel.org/tip/dbbe2ad02e9df26e372f38cc3e70dab9222c832e
Author:Anthony Steinhauser
AuthorDate:Sun, 05 Jan 2020 12:19:43 -08:00
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 4d8df8cbb9156b0a0ab3f802b80cb5db57acc0bf
Gitweb:
https://git.kernel.org/tip/4d8df8cbb9156b0a0ab3f802b80cb5db57acc0bf
Author:Anthony Steinhauser
AuthorDate:Sun, 07 Jun 2020 05:44:19 -07:00
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 21998a351512eba4ed5969006f0c55882d995ada
Gitweb:
https://git.kernel.org/tip/21998a351512eba4ed5969006f0c55882d995ada
Author:Anthony Steinhauser
AuthorDate:Tue, 19 May 2020 06:40:42 -07:00
Hi Matt,
On 6/2/20 8:49 PM, Matt Helsley wrote:
Move recordmcount into the objtool directory. We keep this step separate
so changes which turn recordmcount into a subcommand of objtool don't
get obscured.
Signed-off-by: Matt Helsley
---
Documentation/trace/ftrace-design.rst | 4 ++--
Hi Dan,
Le 08/06/2020 à 16:27, Dan Murphy a écrit :
Richard
On 6/8/20 4:43 AM, Richard Genoud wrote:
Since commit f524f829b75a ("can: m_can: Create a m_can platform
framework"), the can peripheral on STM32MP1 wasn't working anymore.
The reason was a bad copy/paste maneuver that added a call
On 6/8/2020 9:37 PM, Guenter Roeck wrote:
On 6/7/20 10:49 PM, Dilip Kota wrote:
Add YAML schemas for the watchdog timer on Intel Lightning
Mountain SoC.
Signed-off-by: Dilip Kota
---
.../bindings/watchdog/intel,lgm-gptc-wdt.yaml | 75 ++
1 file changed, 75
On 6/8/2020 9:36 PM, Guenter Roeck wrote:
On 6/7/20 10:49 PM, Dilip Kota wrote:
On Intel Lightning Mountain SoC, General Purpose Timer Counter(GPTC)
programmable as clocksource, real time clock or watchdog timer.
This driver configures GPTC as Watchdog timer and triggers reset signal
to CPU
Hi Matt,
On 6/2/20 8:49 PM, Matt Helsley wrote:
Rather than a standalone executable merge recordmcount as a sub command
of objtool. This is a small step towards cleaning up recordmcount and
eventually sharing ELF code with objtool.
For the initial step all that's required is a bit of Makefile
On Tue, 09 Jun 2020 10:43:05 +0200,
Christoph Hellwig wrote:
>
> On Tue, Jun 09, 2020 at 10:05:26AM +0200, Takashi Iwai wrote:
> > > >From the disassembly it seems like a vmalloc allocation is NULL, which
> > > seems really weird as this patch shouldn't make a difference for them,
> > > and I
On Mon, Jun 08, 2020 at 05:07:33PM +0200, Markus Elfring wrote:
> > This code calls brelse(bh) and then dereferences "bh" on the next line
> > resulting in a possible use after free.
>
> There is an unfortunate function call sequence.
>
>
> > The brelse() should just be moved down a line.
>
>
On Mon, Jun 08, 2020 at 11:48:24AM +0200, Markus Elfring wrote:
> > Looks good,
> >
> > Reviewed-by: Christoph Hellwig
>
> How does this feedback fit to remaining typos in the change description?
> Do you care for any further improvements of the commit message
> besides the discussed tag
The primary objective of this patch series is to change the behaviour
of pci_alloc_irq_vectors_affinity() such that it forwards the MSI-X enable
error code when appropriate. In the process, though, it was pointed out
that there are multiple places in the kernel which check/ask for message
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