Hi Rob,
On 20/10/2020 5:26 am, Rob Herring wrote:
On Fri, 16 Oct 2020 17:31:33 +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to
Documentation/devicetree/bindings/spi/
Signed-off-by: Ramuthevar Vad
Hi Mathieu,
On 10/19/20 10:34 PM, Mathieu Poirier wrote:
> Introduce __rpmsg{16|32|64} types along with byte order conversion
> functions based on an rpmsg_device operation as a foundation to
> make RPMSG modular and transport agnostic.
>
> Suggested-by: Guennadi Liakhovetski
> Signed-off-by: M
By doing scan as asynchronous way, scsi device scannning can be out of
order execution. It is no problem if there is a ufs host but the scsi
device name of each host can be changed according to the scan sequences.
Ideal Case) host0 scan first
host0 will be started from /dev/sda
-> /dev/sdb (BootL
On 10/19/20 10:34 PM, Mathieu Poirier wrote:
> Use rpmsg byte conversion functions in order for the RPMSG
> headers and generic functions to be used by external entities.
>
> Signed-off-by: Mathieu Poirier
Reviewed-by: Arnaud Pouliquen
Thanks,
Arnaud
> ---
> drivers/rpmsg/virtio_rpmsg_bu
Hi Rob,
Thank you for review comments...
On 20/10/2020 5:35 am, Rob Herring wrote:
On Fri, Oct 16, 2020 at 05:31:34PM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
remove the cadence-quadspi.tx
On 10/19/20 10:34 PM, Mathieu Poirier wrote:
> Move structure rpmsg_ns_msg to its own header file so that
> it can be used by other entities.
>
> Signed-off-by: Mathieu Poirier
Reviewed-by: Arnaud Pouliquen
Thanks,
Arnaud
> ---
> drivers/rpmsg/virtio_rpmsg_bus.c | 32 +
On Mon, 19 Oct 2020 at 17:26, Marc Zyngier wrote:
>
> On 2020-10-14 12:12, Sumit Garg wrote:
> > Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a
> > particular platform doesn't support pseudo NMIs, then request IPI as a
> > regular IRQ.
> >
> > The main motivation for this f
On Tue, 20 Oct 2020 at 06:23, Benjamin Herrenschmidt
wrote:
>
> On Tue, 2020-10-20 at 04:13 +, Joel Stanley wrote:
> > On Mon, 19 Oct 2020 at 23:20, Benjamin Herrenschmidt
> > wrote:
> > >
> > > On Mon, 2020-10-19 at 16:57 +0800, Dylan Hung wrote:
> > > > These rules must be followed when acc
On Tue, Oct 20, 2020 at 09:18:58AM +0300, Kirill A. Shutemov wrote:
> If the protected memory feature enabled, unmap guest memory from
> kernel's direct mappings.
>
> Migration and KSM is disabled for protected memory as it would require a
> special treatment.
How isn't disabling migration a prob
Hi,
On 20-10-2020 00:04, J. Bruce Fields wrote:
> On Mon, Oct 19, 2020 at 03:46:39PM +, Martijn de Gouw wrote:
>> Hi
>>
>> On 19-10-2020 17:23, J. Bruce Fields wrote:
>>> On Mon, Oct 19, 2020 at 01:42:27PM +0200, Martijn de Gouw wrote:
When the passed token is longer than 4032 bytes, the
Hi,
that's apparently hard to solve inside bfq. The the ioc of the task is being
exited while the task is still inside the code for having an I/O request
served. Is still normal?
Thanks,
Polo
> Il giorno 20 ott 2020, alle ore 08:15, Mike Galbraith ha
> scritto:
>
> [ 1917.361401] ===
Hi Alex.
On Mon, Oct 19, 2020 at 08:24:40PM -0500, Alex G. wrote:
> On 9/28/20 12:30 PM, Alexandru Gagniuc wrote:
> > On the SII9022, the IOVCC and CVCC12 supplies must reach the correct
> > voltage before the reset sequence is initiated. On most boards, this
> > assumption is true at boot-up, so
On Mon, 19 Oct 2020 at 17:29, Marc Zyngier wrote:
>
> On 2020-10-14 12:12, Sumit Garg wrote:
> > Allocate an unused IPI that can be turned as NMI using ipi_nmi
> > framework.
>
> This doesn't do any allocation, as far as I can see. It relies on
> the initial grant from the interrupt controller to
Hi Mathieu,
On 10/19/20 10:34 PM, Mathieu Poirier wrote:
> This set starts by making the RPMSG protocol transport agnostic by
> moving the headers it uses to generic types and using those in the
> current implementation. From there it re-uses the work that Arnaud
> published[1] to make the name s
On Tue, Oct 20, 2020 at 09:18:54AM +0300, Kirill A. Shutemov wrote:
> +int __kvm_protect_memory(unsigned long start, unsigned long end, bool
> protect)
> +{
> + struct mm_struct *mm = current->mm;
> + struct vm_area_struct *vma, *prev;
> + int ret;
> +
> + if (mmap_write_lock_killa
> >>> int __dfl_driver_register(struct dfl_driver *dfl_drv, struct module
> >>> *owner)
> >>> {
> >>> - if (!dfl_drv || !dfl_drv->probe || !dfl_drv->id_table)
> >>> + if (!dfl_drv || !dfl_drv->probe)
> >> id_table is still needed for the normal case.
> >>
> >> Instead of removing this check, cou
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 270315b8235e3d10c2e360cff56c2f9e0915a252
commit: d7071743db31b4f6898b1c742e4b451bb4bc4b02 RISC-V: Add EFI stub support.
date: 2 weeks ago
config: riscv-randconfig-s032-20201020 (attached as .config
On Mon, Oct 19, 2020 at 07:06:47PM +, Марков Михаил Александрович wrote:
> rt2800 only gives you survey for current channel.
> .watchdog= rt2800_watchdog,
> +.update_survey= rt2800_update_survey,
Since this feature is rt2800 specific, I would do not add new generic
ca
On Tue, Oct 20, 2020 at 10:49:25AM +0800, Leo Yan wrote:
> I can see there have another potentail customer to use page-size is
> Arm SPE, but Arm SPE is hardware trace based sample but not interrupt
> based sample. For this case, I think this patch set cannot be
> directly applied to the AUX trace
On Mon, Oct 19, 2020 at 04:14:16PM +0200, Dietmar Eggemann wrote:
> On 14/10/2020 21:48, Peter Zijlstra wrote:
>
> [...]
>
> > + switch (prio) {
> > + case CPUPRI_INVALID:
> > + cpupri = CPUPRI_INVALID;/* -1 */
> > + break;
> > +
> > + case 0...98:
>
> kernel/sc
On Mon 2020-10-19 23:58:56, Daniel Scally wrote:
> Use the new software_node_unregister_nodes_reverse() function to
> unwind this array in a cleaner way.
>
> Suggested-by: Andriy Shevchenko
> Signed-off-by: Daniel Scally
If the new API gets accepted:
Acked-by: Petr Mladek
Best Regards,
Petr
In order to reduce the kernel Image size on multi-platform distributions,
make it possible to build the Amlogic GPIO IRQ controller as a module
by switching it to a platform driver.
Signed-off-by: Neil Armstrong
---
drivers/irqchip/Kconfig | 5 +-
drivers/irqchip/irq-meson-gpio.c | 89
In order to reduce the kernel Image size on multi-platform distributions,
make it possible to build the Amlogic GPIO IRQ controller as a module
by switching it to a platform driver.
The second patch removes MESON_IRQ_GPIO selection from ARCH_MESON to allow
building the driver as module.
Neil Arms
On Mon, 19 Oct 2020 at 17:37, Marc Zyngier wrote:
>
> On 2020-10-14 12:12, Sumit Garg wrote:
> > Add support to handle SGIs as regular NMIs. As SGIs or IPIs defaults to
> > a
>
> There is nothing "regular" about NMIs.
Okay, will do s/regular/pseudo/.
> Drop "or IPIs".
> s/defaults/default/
>
Ac
Selecting MESON_IRQ_GPIO forces it as built-in, but we may need to build it
as a module, thus remove it here and let the "default ARCH_MESON" build as
built-in by default with the option to switch it to module.
Signed-off-by: Neil Armstrong
---
arch/arm64/Kconfig.platforms | 1 -
1 file changed,
On Thu, Oct 15, 2020 at 03:50:40PM +0100, Leo Yan wrote:
SNIP
> @@ -1533,6 +1539,7 @@ static struct c2c_header percent_hitm_header[] = {
> [DISPLAY_LCL] = HEADER_BOTH("Lcl", "Hitm"),
> [DISPLAY_RMT] = HEADER_BOTH("Rmt", "Hitm"),
> [DISPLAY_TOT] = HEADER_BOTH("Tot", "Hitm"),
> +
On Thu, Oct 15, 2020 at 03:50:40PM +0100, Leo Yan wrote:
> Except the existed three display options 'tot', 'rmt', 'lcl', this patch
> adds option 'llc' so that can sort on LLC load metrics. The new
> introduced option can work as a choice if the memory event doesn't
> contain HITM tags.
>
> For t
On Thu, Oct 15, 2020 at 03:50:41PM +0100, Leo Yan wrote:
> Since the new display option 'llc' is introduced, this patch is to
> update the documentation to reflect it.
>
> Signed-off-by: Leo Yan
> ---
> tools/perf/Documentation/perf-c2c.txt | 18 ++
> 1 file changed, 14 insertion
On Mon, Oct 19, 2020 at 11:00:05AM -0300, Marcelo Tosatti wrote:
> > So I think it is important to figure out what that driver really wants
> > in the nohz_full case. If it wants to retain N interrupts per CPU, and
> > only reduce the number of CPUs, the proposed interface is wrong.
>
> It wants N
This patch add police action to set flow meter table which is defined
in IEEE802.1Qci. Flow metering is two rates two buckets and three color
marker to policing the frames, we only enable one rate one bucket in
this patch.
Flow metering shares a same policer pool with VCAP policers, it calls
ocelo
This patch series add gate and police action for tc flower offload to
support Per-Stream Filtering and Policing(PSFP), which is defined in
IEEE802.1Qci.
There is also a TC flower offload to set up VCAPs on ocelot driver.
Because VCAPs use chain 1-21255, we set chain 3 to offload to
gate an
Hi,
Changes since v2:
- Extended the block diagram of INTA in the DT documentation
- Use less creative variable names for unmapped events in the driver
- Short comment section to describe the unmapped event handling in driver
- Use u16 array to store the TI-SCI device identifiers instead of u32
-
The new DMA architecture introduced with AM64 introduced new event types:
unampped events.
These events are mapped within INTA in contrast to other K3 devices where
the events with similar function was originating from the UDMAP or ringacc.
The ti,unmapped-event-sources should contain phandle arr
Add ocelot_mact_lookup() function to retrieve the row and column at
which an FDB entry with the given {DMAC, VID} key is found.
This function is needed in felix DSA driver, so export it.
Signed-off-by: Vladimir Oltean
Signed-off-by: Xiaoliang Yang
---
drivers/net/ethernet/mscc/ocelot.c | 33 ++
VSC9959 supports Per-Stream Filtering and Policing(PSFP), which is
processing after VCAP blocks. We set this block on chain 3 and
set vcap IS2 chain to goto PSFP chain if hardware support.
An example set is:
> tc filter add dev swp0 ingress chain 21000 flower
skip_sw ac
On Tue, Oct 20, 2020 at 03:11:58PM +0800, Xu Yilun wrote:
> I think it is normal case that a driver is successfully registered but
> doesn't match any device because it provides no id_table.
How is that "normal"? What would ever cause that driver to be bound to
a device then?
And you better not
VSC9959 supports Per-Stream Filtering and Policing(PSFP). Sream is
identified by Null Stream identification which is defined in
IEEE802.1Qci.
For IEEE 802.1Qci, there are four tables need to set: stream table,
stream filter table, stream gate table, and flow meter table. This
patch is using TC flo
Police action of tc flower now uses index to set an entry. This patch
uses the police index to add or delete vcap policers, so that one
policer can be shared by several rules.
VCAP policers and PSFP policers share a same policer pool, so VCAP policer
add or delete operations can be exported and sh
The DMA (BCDMA/PKTDMA and their rings/flows) events are under the INTA's
supervision as unmapped events in AM64.
In order to keep the current SW stack working, the INTA driver must replace
the dev_id with it's own when a request comes for BCDMA or PKTDMA
resources.
Implement parsing of the option
Peter Zijlstra writes:
> On Fri, Oct 16, 2020 at 07:56:16AM +0100, Christoph Hellwig wrote:
>> On Thu, Oct 15, 2020 at 10:01:54AM -0500, Christopher M. Riedl wrote:
>> > Functions called between user_*_access_begin() and user_*_access_end()
>> > should be either inlined or marked 'notrace' to prev
From: Bartosz Golaszewski
The driver depends on mmio regmap API but doesn't select the appropriate
Kconfig option. This fixes it.
Fixes: 8c7bd5a454ff ("net: ethernet: mtk-star-emac: new driver")
Cc:
Signed-off-by: Bartosz Golaszewski
---
drivers/net/ethernet/mediatek/Kconfig | 1 +
1 file cha
On Tue, Oct 20, 2020 at 02:22:26PM +0800, Joseph Jang wrote:
> Add sleep timer and timeout handler to prevent device stuck during suspend/
> resume process. The timeout handler will dump disk sleep task at first
> round timeout and trigger kernel panic at second round timeout.
> The default timer f
EXT4_KUNIT_TESTS selects EXT4_FS, thus enabling an optional feature the
user may not want to enable. Fix this by making the test depend on
EXT4_FS instead.
Fixes: 1cbeab1b242d16fd ("ext4: add kunit test for decoding extended
timestamps")
Signed-off-by: Geert Uytterhoeven
---
See also "[PATCH] m
On Mon, Oct 19, 2020 at 04:15:01PM +0200, Dietmar Eggemann wrote:
> On 14/10/2020 21:54, Peter Zijlstra wrote:
> >
> > Add CPUPRI_HIGHER above the RT99 priority to denote the CPU is in use
> > by higher priority tasks (specifically deadline).
>
> sugov:X already triggers this now on our !fast-swi
On Mon, Oct 19, 2020 at 10:59:15AM -0700, t...@redhat.com wrote:
> From: Tom Rix
>
> A break is not needed if it is preceded by a return
>
> Signed-off-by: Tom Rix
> ---
> drivers/tty/serial/imx.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/tty/serial/imx.c b/drivers/
MPTCP_IPV6 selects IPV6, thus enabling an optional feature the user may
not want to enable. Fix this by making MPTCP_IPV6 depend on IPV6, like
is done for all other IPv6 features.
Fixes: f870fa0b5768842c ("mptcp: Add MPTCP socket stubs")
Signed-off-by: Geert Uytterhoeven
---
net/mptcp/Kconfig |
GCC 4.9 sometimes fails to build with "m<>" constraint in
inline assembly.
CC lib/iov_iter.o
In file included from ./arch/powerpc/include/asm/cmpxchg.h:6:0,
from ./arch/powerpc/include/asm/atomic.h:11,
from ./include/linux/atomic.h:7,
from
On Mon, Oct 19, 2020 at 10:38 PM Geert Uytterhoeven
wrote:
> On Mon, Oct 19, 2020 at 5:47 PM Matthieu Baerts
> wrote:
> > On 19/10/2020 13:32, Geert Uytterhoeven wrote:
> > > MPTCP_KUNIT_TESTS selects MPTCP, thus enabling an optional feature the
> > > user may not want to enable. Fix this by mak
From: Mathieu Desnoyers
The placeholder for instruction selection should use the second
argument's operand, which is %1, not %0. This could generate incorrect
assembly code if the memory addressing of operand %0 is a different
form from that of operand %1.
Fixes: 9bf2b5cdc5fe ("powerpc: Fixes fo
In several places, inline assembly uses the "%Un" modifier
to enable the use of instruction with update form addressing,
but the associated "<>" constraint is missing.
As mentioned in previous patch, this fails with gcc 4.9, so
"<>" can't be used directly.
Use UPD_CONSTR macro everywhere %Un modi
Am Montag, den 19.10.2020, 19:07 +0200 schrieb Jerome Brunet:
> Commit a4e7279cd1d1 ("cdc-acm: introduce a cool down") is causing
> regression if there is some USB error, such as -EPROTO.
>
> This has been reported on some samples of the Odroid-N2 using the Combee II
> Zibgee USB dongle.
>
> > st
Greetings.
Good day, and I hope you are safe from this pandemic troubling the world.
I work with an online lotto company as the lotto machine coordinator and the
lotto supervisor.
I have discovered a way to fix the winning number with the lotto machine to
make any person win the lotto jackpot
From: Arvind Sankar> Sent: 19 October 2020 16:30
> To: Herbert Xu ; David S. Miller
> ; linux-
> cry...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Subject: [PATCH 4/5] crypto: lib/sha256 - Unroll SHA256 loop 8 times intead
> of 64
>
> This reduces code size substantially (on x86_64 wit
: x86_64-randconfig-s032-20201020 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-dirty
#
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id
On 19-10-20, 21:12, Defang Bo wrote:
> Similar to commit<05829d9431df>("cpufreq: ti-cpufreq: kfree opp_data when
> failure"), opp_data needs to be freed when failure, including fail_put_node.
This is allocated using devm_kzalloc() and so we don't need to free it
explicitly.
> Signed-off-by: Defa
The reserved-memory overlap detection code fails to detect overlaps if
either of the regions starts at address 0x0. For some reason the code
explicitly checks for and ignores such regions, but this check looks
invalid. Remove the check and fix this detection.
For example, no overlap is currently
Le 19/10/2020 à 22:24, Segher Boessenkool a écrit :
On Mon, Oct 19, 2020 at 12:12:48PM +, Christophe Leroy wrote:
In several places, inline assembly uses the "%Un" modifier
to enable the use of instruction with pre-update addressing,
Calling this "pre-update" is misleading: the register
"Kirill A. Shutemov" writes:
> == Background / Problem ==
>
> There are a number of hardware features (MKTME, SEV) which protect guest
> memory from some unauthorized host access. The patchset proposes a purely
> software feature that mitigates some of the same host-side read-only
> attacks.
>
>
On Mon, Oct 19, 2020 at 09:03:54PM -0700, Sowjanya Komatineni wrote:
> VI I2C don't have DMA support and uses PIO mode all the time.
>
> Current driver uses writesl() to fill TX FIFO based on available
> empty slots and with this seeing strange silent hang during any I2C
> register access after fi
15a252
> commit: 077365a941166f3a7f5894017f9d26d17cdec00e pinctrl: Rename sh-pfc to
> renesas
> date: 5 weeks ago
> config: x86_64-randconfig-s032-20201020 (attached as .config)
> compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
> reproduce:
> # apt-get install sparse
> # sparse ver
There now the menu entries for the amlogic clock controllers.
Do not select these when ARM64 is enabled so it possible to ship only the
required.
Signed-off-by: Jerome Brunet
---
arch/arm64/Kconfig.platforms | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/Kconfig.platforms b/arc
Hello,
syzbot found the following issue on:
HEAD commit:e67f4ba8 kmsan_hooks: do not enter/exit runtime on ioremap
git tree: https://github.com/google/kmsan.git master
console output: https://syzkaller.appspot.com/x/log.txt?x=16f3ce9450
kernel config: https://syzkaller.appspot.com/
Hmm,
what prevents us from killing of the last ->readpages instance?
Leaving half-finished API conversions in the tree usually doesn't end
well..
Disable wakeup in flexcan_remove().
Fixes: de3578c198c6 ("can: flexcan: add self wakeup support")
Fixes: 915f9666421c ("can: flexcan: add support for DT property
'wakeup-source'")
Signed-off-by: Joakim Zhang
---
drivers/net/can/flexcan.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/dri
The first patch from Liu Ying aims to export SCU symbols for SoCs w/wo SCU,
so that no need to check CONFIG_IMX_SCU in the specific driver.
The following patches are flexcan fixes and add stop mode support for i.MX8QM.
ChangeLogs:
V2->V3:
* define IMX_SC_R_CAN(x) in rsrc.h
* remov
For SoCs with SCU support, need setup stop mode via SCU firmware,
so this property can help indicate a resource in SCU firmware.
Signed-off-by: Joakim Zhang
---
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devic
Add IMX_SC_R_CAN(x) macro for CAN.
Suggested-by: Marc Kleine-Budde
Signed-off-by: Joakim Zhang
---
include/dt-bindings/firmware/imx/rsrc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/firmware/imx/rsrc.h
b/include/dt-bindings/firmware/imx/rsrc.h
index 54278d5c1856..4
After double check with Layerscape CAN owner (Pankaj Bansal), confirm that
LS1021A doesn't support ECC feature, so remove FLEXCAN_QUIRK_DISABLE_MECR
quirk.
Fixes: 99b7668c04b27 ("can: flexcan: adding platform specific details for
LS1021A")
Cc: Pankaj Bansal
Signed-off-by: Joakim Zhang
---
driv
Correct fsl,clk-source example since flexcan driver uses "of_property_read_u8"
to get this property.
Fixes: 9d733992772d ("dt-bindings: can: flexcan: add PE clock source property
to device tree")
Signed-off-by: Joakim Zhang
---
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt | 2 +-
1
The System Controller Firmware (SCFW) is a low-level system function
which runs on a dedicated Cortex-M core to provide power, clock, and
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
(QM, QP), and i.MX8QX (QXP, DX). SCU driver manages the IPC interface
between host CPU and
From: Liu Ying
Always export SCU symbols for both SCU SoCs and non-SCU SoCs to avoid
build error.
Signed-off-by: Liu Ying
Signed-off-by: Peng Fan
Signed-off-by: Joakim Zhang
---
include/linux/firmware/imx/ipc.h | 15 +++
include/linux/firmware/imx/svc/misc.h | 23 +++
After double check with Layerscape CAN owner (Pankaj Bansal), confirm
that LX2160A indeed supports ECC feature, so correct the feature table.
For SoCs with ECC supported, even use FLEXCAN_QUIRK_DISABLE_MECR quirk to
disable non-correctable errors interrupt and freeze mode, had better use
FLEXCAN_Q
For SoCs with ECC supported, even use FLEXCAN_QUIRK_DISABLE_MECR quirk to
disable non-correctable errors interrupt and freeze mode, had better use
FLEXCAN_QUIRK_SUPPORT_ECC quirk to initialize all memory.
Fixes: cdce844865bea ("can: flexcan: add vf610 support for FlexCAN")
Signed-off-by: Joakim Zh
This patch intends to rename FLEXCAN_QUIRK_SETUP_STOP_MODE quirk
to FLEXCAN_QUIRK_SETUP_STOP_MODE_GRP for non-scu SoCs, coming patch will
add quirk for scu SoCs.
For non-scu SoCs, setup stop mode with GPR register.
For scu SoCs, setup stop mode with SCU firmware.
Signed-off-by: Joakim Zhang
---
FYI Tao, I shared this with Valentin on IRC yesterday evening (we're
both in Europe):
https://paste.debian.net/1167885/
I'll be going over it again this morning with a (hopefully) fresh(er) mind.
> + rc = add_to_page_cache(page, mapping,
> +page->index, gfp);
This trivially fits onto a single line.
From: Joe Perches
> Sent: 19 October 2020 16:47
> On Mon, 2020-10-19 at 03:13 +0800, kernel test robot wrote:
> > Hi Ard,
> >
> > First bad commit (maybe != root cause):
> >
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> > master
> > head: 9d9af1007bc08971953ae9
On Sun, Oct 18, 2020 at 11:14:53PM -0700, Randy Dunlap wrote:
> Fix a build error in drivers/mfd/ioc.o by exporting
> pci_find_host_bridge().
>
> ERROR: modpost: "pci_find_host_bridge" [drivers/mfd/ioc3.ko] undefined!
I think the mfd code should be fixed to not depend on such an internal
symbol i
On Tue, Oct 06, 2020 at 06:05:13PM +0200, Ulf Hansson wrote:
> The avs drivers are all SoC specific drivers that doesn't share any code.
> Instead they are located in a directory, mostly to keep similar
> functionality together. From a maintenance point of view, it makes better
> sense to collect S
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
x86/seves
branch HEAD: b17a45b6e53f6613118b2e5cfc4a992cc50deb2c x86/boot/64: Explicitly
map boot_params and command line
elapsed time: 721m
configs tested: 114
configs skipped: 59
The following configs have been built s
Hi there,
Could someone please comment on the following hard-lock (*). Staring
at the code, I see `nvkm_rd32` calls are enclosed in a timeout
detection, except one.
drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c#L171
...
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x100c80) & 0x0001))
b
On 19/10/20 20:15, Ben Gardon wrote:
> When getting the dirty log, we
> follow the following steps:
> 1. Atomically get and clear an unsigned long of the dirty bitmap
> 2. For each GFN in the range of pages covered by the unsigned long mask:
> 3. Clear the dirty or writable bit on the SPTE
> 4.
NAK. Any virtio implementation that needs special DMA OPS treatment
needs to set the VIRTIO_F_ACCESS_PLATFORM bit. The only reason the
Xen hack existst is because it slipped in a long time ago and we can't
fix that any more.
Hi Lorenzo,
On 19/10/20 9:43 pm, Lorenzo Pieralisi wrote:
> On Mon, Oct 12, 2020 at 04:41:11AM +, Z.q. Hou wrote:
>
> [...]
>
> Yeah, I don't see any registers in the DRA7x PCIe wrapper for
> disabling error forwarding.
It's a DWC port logic register AFAICT, but perhaps not
Hi Jiri,
On Tue, Oct 20, 2020 at 09:25:53AM +0200, Jiri Olsa wrote:
> On Thu, Oct 15, 2020 at 03:50:40PM +0100, Leo Yan wrote:
>
> SNIP
>
> > @@ -1533,6 +1539,7 @@ static struct c2c_header percent_hitm_header[] = {
> > [DISPLAY_LCL] = HEADER_BOTH("Lcl", "Hitm"),
> > [DISPLAY_RMT] = HEADE
On Mon, Oct 19, 2020 at 03:45:56PM -0700, Daniel Latypov wrote:
> Add basic test coverage for files that don't require any config options:
> * gcd.c
> * lcm.c
> * int_sqrt.c
> * reciprocal_div.c
> (Ignored int_pow.c since it's a simple textbook algorithm.)
>
> These tests aren't particularly inter
From: Gene Chen
This change adds the binding doc for the MT6360 ADC.
Signed-off-by: Gene Chen
---
.../bindings/iio/adc/mediatek,mt6360-adc.yaml | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iio/adc/mediatek,mt6360-adc.
In-Reply-To:
This patch series add MT6360 ADC support contains driver, testing document
and binding document
Gene Chen (2)
dt-bindings: iio: adc: add bindings doc for MT6360 ADC
Documentation: ABI: testing: mt6360: Add ADC sysfs guideline
iio: adc: mt6360: Add ADC driver for MT6360
Docum
From: Gene Chen
Add ABI documentation for mt6360 ADC sysfs interfaces.
Signed-off-by: Gene Chen
---
Documentation/ABI/testing/sysfs-bus-iio-adc-mt6360 | 78 ++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-mt6360
diff --gi
From: Gene Chen
Add MT6360 ADC driver including Charger Current, Voltage, and
Temperature.
Signed-off-by: Gene Chen
---
drivers/iio/adc/Kconfig | 11 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/mt6360-adc.c | 372 +++
3 files changed,
On Mon, Oct 19, 2020 at 11:43:53AM +0800, Kever Yang wrote:
> Hi Daniel,
>
> On 2020/10/15 下午11:23, Daniel Vetter wrote:
> > On Wed, Oct 14, 2020 at 09:48:43AM +0800, Kever Yang wrote:
> > > Hi Maintainers,
> > >
> > > Does this patch ready to merge?
> > Would maybe be good to get some acks
Hello,
On Thu, Oct 15, 2020 at 11:51 PM Leo Yan wrote:
>
> If the memory event doesn't contain HITM tag (like Arm SPE), it cannot
> rely on HITM display to report cache false sharing. Alternatively, we
> can use the LLC access and multi-threads info to locate the potential
> false sharing's data
On Tue, Oct 20, 2020 at 09:26:03AM +0200, Jiri Olsa wrote:
> On Thu, Oct 15, 2020 at 03:50:40PM +0100, Leo Yan wrote:
> > Except the existed three display options 'tot', 'rmt', 'lcl', this patch
> > adds option 'llc' so that can sort on LLC load metrics. The new
> > introduced option can work as a
On Tue, Oct 20, 2020 at 02:22:26PM +0800, Joseph Jang wrote:
> Add sleep timer and timeout handler to prevent device stuck during
suspend/
> resume process. The timeout handler will dump disk sleep task at first
> round timeout and trigger kernel panic at second round timeout.
> The default tim
On Tue, 20 Oct 2020 at 08:52, 冯锐 wrote:
>
> Hi All,
>
> A month has passed, do I need to modify these patches?
Unfortunately I didn't get the time to review them before the merge
window opened, but I am looking at them now. Allow me a day or two to
complete the review.
Kind regards
Ufffe
>
> Th
On 10/20/20 11:13 AM, Namhyung Kim wrote:
> Hello,
>
> On Tue, Oct 20, 2020 at 12:42 AM John Garry wrote:
>>
>> There is much duplication in the error handling for directory traversing
>> for processing JSONs.
>>
>> Factor out the common code to tidy a bit.
>>
>> Signed-off-by: John Garry
>>
It will always enable the interrupt after calling plic_set_affinity()
however it should set to it previous setting. Staying disabled or enabled.
This patch can also fix this pwm hang issue in Unleashed board.
[ 919.015783] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 919.020922] rcu:
On Tue, Oct 20, 2020 at 09:19:45AM +0200, Peter Zijlstra wrote:
> On Tue, Oct 20, 2020 at 10:49:25AM +0800, Leo Yan wrote:
> > I can see there have another potentail customer to use page-size is
> > Arm SPE, but Arm SPE is hardware trace based sample but not interrupt
> > based sample. For this ca
Hi,
On 05/10/20 11:27 am, Kishon Vijay Abraham I wrote:
> Hi Jon Mason, Allen Hubbe, Dave Jiang,
>
> On 30/09/20 9:05 pm, Kishon Vijay Abraham I wrote:
>> This series is about implementing SW defined Non-Transparent Bridge (NTB)
>> using multiple endpoint (EP) instances. This series has been test
On Tue, Oct 20, 2020 at 05:13:01PM +0900, Namhyung Kim wrote:
> Hello,
>
> On Thu, Oct 15, 2020 at 11:51 PM Leo Yan wrote:
> >
> > If the memory event doesn't contain HITM tag (like Arm SPE), it cannot
> > rely on HITM display to report cache false sharing. Alternatively, we
> > can use the LLC
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