t;>
> >>>This patch adds an option, CONFIG_FPU, to enable/disable floating
> >>>procedures. Also, some style issues are fixed.
> >>>
> >>>Signed-off-by: Alan Kao
> >>>Cc: Greentime Hu
> >>>Cc: Zong Li
> >>>---
&
- Fix wording, style, etc.
Changes in v3:
- Refactor the whole patch into independent ones.
Changes in v2:
- Various code cleanups and style fixes.
Alan Kao (5):
Extract FPU context operations from entry.S
Refactor FPU code in signal setup/return procedures
Cleanup ISA string setting
All
created and determined
when parsing the hardware capability from device tree during booting.
This variable is used in those FPU-related functions.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/include/asm/hwcap.h | 3 +++
arch/riscv/include
FPU-related logic is separated from normal signal handling path in
this patch. Kernel can easily be configured to exclude those procedures
for no-FPU systems.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv
the MARCH string in AFLAGS and CFLAGS
become the same.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/Makefile | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/risc
We move __fstate_save and __fstate_restore to a new source
file, fpu.S.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/entry.S | 87
FPU codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs, so that a no-FPU
configuration is allowed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/Kconfig | 9
This patch adds an option, CONFIG_FPU, so that we can enable/disable
floating procedures in kernel.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Zong Li
---
arch/riscv/Kconfig | 4
arch/riscv/Makefile| 4
arch/riscv/include/asm/switch_to.h | 4
On Wed, Jun 20, 2018 at 11:39:38PM -0700, Christoph Hellwig wrote:
> > +ifeq ($(CONFIG_FPU),y)
> > KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)fd$(KBUILD_ARCH_C)
> > +else
> > +KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_ARCH_A)$(KBUILD_ARCH_C)
> > +endif
>
> Can we refactor that K
We move __fstate_save and __fstate_restore to a new source
file, fpu.S.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/entry.S | 87
This patch cleanup the MARCH string passing to both compiler and
assembler. Note that the CFLAGS should not contain "fd" before we
have mechnisms like kernel_fpu_begin/end in other architectures.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
created and determined
when parsing the hardware capability from device tree during booting.
This variable is used in those FPU-related functions.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/include/asm/switch_to.h | 8
arch/riscv
FPU codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs, so that a no-FPU
configuration is allowed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch
ndependent ones.
Changes in v2:
- Various code cleanups and style fixes.
Alan Kao (5):
Extract FPU context operations from entry.S
Refactor FPU code in signal setup/return procedures
Cleanup ISA string setting
Allow to disable FPU support
Auto-detect whether a FPU exists
arc
FPU-related logic is separated from normal signal handling path in
this patch. Kernel can easily be configured to exclude those procedures
for no-FPU systems.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv
>
> I don't think it's worth fretting about support for systems with F but
> not D for now: our glibc ABIs are IMAC and IMAFDC so they probably won't
> end up being popular. We can always extend this in the future.
>
> CC: Alan Kao
> Signed-off-by: Palmer
FPU codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs, so that a no-FPU
configuration is allowed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch
FPU-related logic is separated from normal signal handling path in
this patch. Kernel can easily be configured to exclude those procedures
for no-FPU systems.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv
the MARCH string in AFLAGS and CFLAGS
become the same.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/Makefile | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/risc
We move __fstate_save and __fstate_restore to a new source
file, fpu.S.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/entry.S | 87
SPDX header to newly created fpu.S.
- Fix a build error, sorry for that.
- Fix wording, style, etc.
Changes in v3:
- Refactor the whole patch into independent ones.
Changes in v2:
- Various code cleanups and style fixes.
Alan Kao (5):
Extract FPU context operations from entry.S
Refacto
created and determined
when parsing the hardware capability from device tree during booting.
This variable is used in those FPU-related functions.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm
On Wed, Aug 08, 2018 at 11:31:24PM -0700, Christoph Hellwig wrote:
> > extern unsigned long elf_hwcap;
> > +extern bool has_fpu;
> > #endif
>
> Doesn't this conflict with the !CONFIG_CPU stub in switch_to.h?
switch_to.h did include asm/hwcap.h, but the !CONFIG_FPU stub
+#define has_fpu false
On Thu, Aug 09, 2018 at 12:02:58AM -0700, Christoph Hellwig wrote:
> On Thu, Aug 09, 2018 at 02:43:36PM +0800, Alan Kao wrote:
> > It does look a little bit weird. Should I send a v6 for this?
>
> Yes, please resend the series or just this patch.
>
> I think the hswap.h
created and determined
when parsing the hardware capability from device tree during booting.
This variable is used in those FPU-related functions.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/include/asm/switch_to.h | 8
arch/riscv
On Wed, Aug 01, 2018 at 10:55:28AM -0700, Palmer Dabbelt wrote:
> On Tue, 26 Jun 2018 21:22:26 PDT (-0700), alan...@andestech.com wrote:
> >This patch adds an option, CONFIG_FPU, to enable/disable floating
> >procedures. Also, some style issues are fixed.
> >
> >Sig
as always given the riscv64imafdc
MARCH string because there are fld/fsd's in entry.S; compiler was
always given riscv64imac because kernel doesn't need floating point
code generation. After this, the MARCH string in AFLAGS and CFLAGS
become the same.
Signed-off-by: Alan Kao
Cc: Green
This patchset adds an option, CONFIG_FPU, to enable/disable floating-
point procedures.
Changes in v3:
- Refactor the whole patch into independent ones.
Changes in v2:
- Various code cleanups and style fixes.
Alan Kao (4):
Extract FPU context operations from entry.S
Refactor FPU codes in
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/kernel/signal.c | 68 +++---
1 file changed, 41 insertions(+), 27 deletions(-)
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index
FP codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs to support
no-FPU systems.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/Kconfig | 9 +
arch
We move __fstate_save and __fstate_restore to a new source
file, fpu.S.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/entry.S | 87 --
arch/riscv/kernel/fpu.S| 105
On Wed, Jan 10, 2018 at 11:36:43AM -0500, Steven Rostedt wrote:
> On Wed, 10 Jan 2018 15:38:10 +0800
> Alan Kao wrote:
>
> > +static int __ftrace_modify_call(unsigned long hook_pos, unsigned long
> > target,
> > + bool enable)
> &g
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/kernel/ftrace.c | 17 ++
arch/riscv/kernel/mcount-dyn.S | 124 +
3 files changed, 142 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv
ernel text goes wrong (2/6)
- Replace manual comparisons by calling memcmp (2/6)
- Simplify the conditional assignment in the Makefile (1/6)
Alan Kao (6):
riscv/ftrace: Add RECORD_MCOUNT support
riscv/ftrace: Add dynamic function tracer support
riscv/ftrace: Add dynamic function graph trac
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/include/asm/ftrace.h | 1 +
arch/riscv/kernel/mcount-dyn.S | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/ftrace.h b/arch/riscv/include/asm/ftrace.h
index acf0c7d001f3..429a6a156645 100644
--- a/arch/riscv
cal part of ftrace, it is
ignored for now to ease the review process.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/include/asm/ftrace.h | 1 +
arch/riscv/kernel/ftrace.c | 2 +-
arch/riscv/kernel/stacktrace.c | 6 ++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --gi
return
Considering the following DYNAMIC_FTRACE_WITH_REGS feature, it would be
more extendable to have a ftrace_graph_caller function, instead of
calling prepare_ftrace_return directly in ftrace_caller.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/kernel/ftrace.c | 25 -
Now recordmcount.pl recognizes RISC-V object files. For the mechanism to
work, we have to disable the linker relaxation.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/Makefile | 3 +++
scripts/recordmcount.pl | 5 +
3 files changed, 9 insertions
reference implementation once we have the dynamic
ftrace.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/ftrace.h | 45 ++
arch/riscv/kernel/Makefile | 5 +-
arch/riscv/kernel/ftrace.c | 100
This patch set includes the building blocks of dynamic ftraces features
for RISC-V machines.
Alan Kao (6):
riscv/ftrace: Add RECORD_MCOUNT support
riscv/ftrace: Add dynamic function tracer support
riscv/ftrace: Add dynamic function graph tracer support
riscv/ftrace: Add
reference implementation once we have the dynamic
ftrace.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/ftrace.h | 45
arch/riscv/kernel/Makefile | 5 ++-
arch/riscv/kernel/ftrace.c | 94
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/include/asm/ftrace.h | 1 +
arch/riscv/kernel/mcount-dyn.S | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/ftrace.h b/arch/riscv/include/asm/ftrace.h
index acf0c7d001f3..429a6a156645 100644
--- a/arch/riscv
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/kernel/ftrace.c | 17 ++
arch/riscv/kernel/mcount-dyn.S | 124 +
3 files changed, 142 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv
nst. But since it is not a critical part of ftrace and
is a RISC-V-specific behavior, it is ignored for now to ease the
review process.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/include/asm/ftrace.h | 1 +
arch/riscv/kernel/ftrace.c | 2 +-
arch/riscv/kernel/stacktrace.c
Now recordmcount.pl recognizes RISC-V object files. For the mechanism to
work, we have to disable the linker relaxation. This is because
relaxation happens after the script records offsets of _mcount call
sites, resulting in a unreliable record.
Cc: Greentime Hu
Signed-off-by: Alan Kao
r.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/kernel/ftrace.c | 25 +++-
arch/riscv/kernel/mcount-dyn.S | 65 ++
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c
On Wed, Jan 10, 2018 at 08:43:54AM +0100, Christoph Hellwig wrote:
> On Wed, Jan 10, 2018 at 03:38:09PM +0800, Alan Kao wrote:
> > -LDFLAGS_vmlinux :=
> > +ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
> > + LDFLAGS_vmlinux := --no-relax
> > +else
> > + LDFLAGS_v
This patch set includes the building blocks of dynamic ftrace features
for RISC-V machines.
Changes in v2:
- Fix the return value as writing to kernel text goes wrong (2/6)
- Replace manual comparisons by calling memcmp (2/6)
- Simplify the conditional assignment in the Makefile (1/6)
Alan
cal part of ftrace, it is
ignored for now to ease the review process.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/include/asm/ftrace.h | 1 +
arch/riscv/kernel/ftrace.c | 2 +-
arch/riscv/kernel/stacktrace.c | 6 ++
3 files changed, 8 insertions(+), 1 deletion(-)
diff --gi
Now recordmcount.pl recognizes RISC-V object files. For the mechanism to
work, we have to disable the linker relaxation.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/Makefile | 3 +++
scripts/recordmcount.pl | 5 +
3 files changed, 9 insertions
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/include/asm/ftrace.h | 1 +
arch/riscv/kernel/mcount-dyn.S | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/ftrace.h b/arch/riscv/include/asm/ftrace.h
index acf0c7d001f3..429a6a156645 100644
--- a/arch/riscv
implementation once we have the dynamic
ftrace.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/ftrace.h | 45 ++
arch/riscv/kernel/Makefile | 5 +-
arch/riscv/kernel/ftrace.c | 100
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/Kconfig | 1 +
arch/riscv/kernel/ftrace.c | 17 ++
arch/riscv/kernel/mcount-dyn.S | 124 +
3 files changed, 142 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv
return
Considering the following DYNAMIC_FTRACE_WITH_REGS feature, it would be
more extendable to have a ftrace_graph_caller function, instead of
calling prepare_ftrace_return directly in ftrace_caller.
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
arch/riscv/kernel/ftrace.c | 25 +++-
On Sun, Jan 14, 2018 at 11:24:53PM -0800, Stefan O'Rear wrote:
> On Sun, Jan 14, 2018 at 10:47 PM, Alan Kao wrote:
> > + /*
> > +* For the dynamic ftrace to work, here we should reserve at least
> > +* 8 bytes for a functional auipc-jalr pa
On Thu, Mar 01, 2018 at 10:05:07AM +0800, Alan Kao wrote:
> On Wed, Feb 28, 2018 at 05:12:52AM +0800, Steven Rostedt wrote:
> > On Tue, 27 Feb 2018 18:04:26 +0800
> > Alan Kao wrote:
> >
> > > 1. During the final linking stages, do "objdump vmlinux.o | grep
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
Documentation/riscv/pmu.txt | 250
1 file changed, 250 insertions(+)
create mode 100644 Documentation/riscv/pmu.txt
diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.txt
new
This implements the baseline PMU for RISC-V platforms.
To ease the future PMU portings, a guide is also written, containing
perf concepts, arch porting practices and some hints.
Alan Kao (2):
perf: riscv: preliminary RISC-V support
perf: riscv: Add Document for Future Porting Guide
-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
iv-Spec 1.10 yet, but work
> >around should be easy with very small fixes. Please check
> >https://github.com/riscv/riscv-qemu/pull/115 for future updates.
> >
> >Cc: Nick Hu
> >Cc: Greentime Hu
> >Signed-off-by: Alan Kao
>
> We should really be able
This patch adds an option, CONFIG_FPU, to enable/disable floating
procedures. Also, some style issues are fixed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Zong Li
---
arch/riscv/Kconfig | 9
arch/riscv/Makefile| 19 +++
arch/riscv/include/asm
t; >MARCH string because there are fld/fsd's in entry.S; compiler was
> >always given riscv64imac because kernel doesn't need floating point
> >code generation. After this, the MARCH string in AFLAGS and CFLAGS
> >become the same.
> >
> >Signed-off-by: Alan K
Changes in v3:
- Refactor the whole patch into independent ones.
Changes in v2:
- Various code cleanups and style fixes.
Alan Kao (5):
Extract FPU context operations from entry.S
Refactor FPU code in signal setup/return procedures
Cleanup ISA string setting
Allow to disable FPU suppor
FPU codes have been separated from common part in previous patches.
This patch add the CONFIG_FPU option and some stubs, so that a no-FPU
configuration is allowed.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch
FPU-related logic is separated from normal signal handling path in
this patch. Kernel can easily be configured to exclude those procedures
for no-FPU systems.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv
created and determined
when parsing the hardware capability from device tree during booting.
This variable is used in those FPU-related functions.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
---
arch/riscv/include/asm/switch_to.h | 8
arch/riscv
We move __fstate_save and __fstate_restore to a new source
file, fpu.S.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
Reviewed-by: Christoph Hellwig
---
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/entry.S | 87
This patch cleanup the MARCH string passing to both compiler and
assembler. Note that the CFLAGS should not contain "fd" before we
have mechnisms like kernel_fpu_begin/end in other architectures.
Signed-off-by: Alan Kao
Cc: Greentime Hu
Cc: Vincent Chen
Cc: Zong Li
Cc: Nick Hu
On Wed, Oct 31, 2018 at 07:17:45AM -0700, Christoph Hellwig wrote:
> On Wed, Oct 31, 2018 at 04:46:10PM +0530, Anup Patel wrote:
> > I agree that we need a place for vendor-specific ISA extensions and
> > having vendor-specific directories is also good.
>
> The only sensible answer is that we shou
Hi Guenter,
On Sat, Oct 13, 2018 at 05:02:05PM -0700, Guenter Roeck wrote:
> Hi,
>
> With this patch in -next applied, I get the following error
> when building riscv:defconfig.
I guess what you meant was this commit:
commit 0a5bee05fc67ce2044b8d91a18abbf14042da531
The modification in Makefile
r that.
> > - Fix wording, style, etc.
> >
> >Changes in v3:
> > - Refactor the whole patch into independent ones.
> >
> >Changes in v2:
> > - Various code cleanups and style fixes.
> >
> >
> >Alan Kao (5):
> > Extract FPU context operat
On Thu, Nov 01, 2018 at 10:50:04AM -0700, Palmer Dabbelt wrote:
> On Wed, 31 Oct 2018 17:55:42 PDT (-0700), alan...@andestech.com wrote:
> >On Wed, Oct 31, 2018 at 07:17:45AM -0700, Christoph Hellwig wrote:
> >>On Wed, Oct 31, 2018 at 04:46:10PM +0530, Anup Patel wrote:
> >>> I agree that we need a
On Wed, Feb 28, 2018 at 05:12:52AM +0800, Steven Rostedt wrote:
> On Tue, 27 Feb 2018 18:04:26 +0800
> Alan Kao wrote:
>
> > 1. During the final linking stages, do "objdump vmlinux.o | grep ..." [2]
>
> Note, doing it at that stage takes the longest time. It ma
>>> - Fix the bug reported by Alex, which was caused by not sufficient
> >>> initialization. Check https://lkml.org/lkml/2018/3/31/251 for the
> >>> discussion.
> >>>
> >>>Alan Kao (2):
> >>> perf: riscv: preliminary RISC-V su
Hi Alex,
On Tue, Apr 03, 2018 at 07:08:43PM -0700, Alex Solomatnikov wrote:
> Doc fixes:
>
>
Thanks for these fixes. I'll edit this patch and send a v3 once I am done
with the PMU patch.
I suppose a "Reviewed-by: Alex Solomatnikov" appending at the end of the
commit will be great, right?
Alan
# L1 Instruction 32K [2]
> # L1 Data 32K [2]
> # L1 Instruction 32K [3]
> # L1 Data 32K [3]
> # missing features: TRACING_DATA BUILD_ID CPUDESC CPUID NUMA_TOPOLOGY
> BRANCH_STACK GROUP_DESC AUXTRACE STAT
> #
>
>
>
Hi Palmer,
Thanks for the refining work! But a small correction here:
On Mon, Jun 04, 2018 at 01:30:28PM -0700, Palmer Dabbelt wrote:
> From: Alan Kao
>
> The EXPORT_SYMBOL(_mcount) for RISC-V ended up inside a
> CONFIG_FUNCTION_GRAPH_TRACER ifdef. If you enable modules withou
12:27:26 PDT (-0700), atish.pa...@wdc.com wrote:
> >>>>On 4/24/18 11:07 AM, Atish Patra wrote:
> >>>>>On 4/19/18 4:28 PM, Alan Kao wrote:
> >>>>>However, I got an rcu-stall for the test "47: Event times".
> >>>>># ./
On Tue, Aug 20, 2019 at 08:28:36PM +, Atish Patra wrote:
> On Tue, 2019-08-20 at 02:22 -0700, h...@infradead.org wrote:
> > On Tue, Aug 20, 2019 at 08:42:19AM +, Atish Patra wrote:
> > > cmask NULL is pretty common case and we would be unnecessarily
> > > executing bunch of instructions ev
On Tue, Sep 03, 2019 at 11:48:52AM -0700, Palmer Dabbelt wrote:
> On Tue, 27 Aug 2019 23:11:46 PDT (-0700), Christoph Hellwig wrote:
> >On Tue, Aug 27, 2019 at 04:37:16PM -0700, Palmer Dabbelt wrote:
> >>clint0 would be version 0 of the clint, with is the core-local interrupt
> >>controller in rock
On Fri, Sep 27, 2019 at 10:57:45PM +, Atish Patra wrote:
> On Fri, 2019-09-27 at 15:19 -0700, Christoph Hellwig wrote:
> > On Thu, Sep 26, 2019 at 05:09:12PM -0700, Atish Patra wrote:
> > > The Supervisor Binary Interface(SBI) specification[1] now defines a
> > > base extension that provides ex
On Tue, Oct 01, 2019 at 03:10:16AM -0700, h...@infradead.org wrote:
> On Tue, Oct 01, 2019 at 08:22:37AM +, Atish Patra wrote:
> > riscv_of_processor_hartid() or seems to be a better candidate. We
> > already check if "rv" is present in isa string or not. I will extend
> > that to check for rv6
Please ignore the previous mail, I must have missed this part of the patch,
>
> > + csrrt0, CSR_MISA
> > + andit0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
> > + bnezt0, .Lreset_regs_done
> > +
In S-mode we were not able to obtain the ISA information in misa, but now
the
Hi Christoph,
On Tue, Aug 13, 2019 at 05:47:45PM +0200, Christoph Hellwig wrote:
> When we get booted we want a clear slate without any leaks from previous
> supervisors or the firmware. Flush the instruction cache and then clear
> all registers to known good values. This is really important for
A memory save operation to 8-byte variable in RV32 is divided into
two sw instructions in the put_user macro. The current fixup returns
execution flow to the second sw instead of the one after it.
This patch fixes this fixup code according to the load access part.
Signed-off-by: Alan Kao
Cc
Hi Anup,
Sorry for being late to the party. I think one more thing should
move together with setup_vm():
On Mon, Mar 25, 2019 at 03:37:38AM +, Anup Patel wrote:
> The Linux RISC-V 32bit kernel is broken after we moved setup_vm() from
> kernel/setup.c to mm/init.c because Linux RISC-V 32bit k
is first:
* What is the frequency of that "funny number" event? Was that often?
* If you monitor only one hart, will the event disappear?
* What will happen if you change the counter_width to fit U54's counter width?
* Is the test program you used open-sourced?
> Alex
>
Hi Alex,
On Mon, Apr 02, 2018 at 03:36:12PM +0800, Alan Kao wrote:
> On Sat, Mar 31, 2018 at 03:47:10PM -0700, Alex Solomatnikov wrote:
>
> The original guess was that maybe, an counter value on a hart is picked
> as the minusend, and an old counter value on another hart was recor
://lkml.org/lkml/2018/3/31/251 for the
discussion.
Alan Kao (2):
perf: riscv: preliminary RISC-V support
perf: riscv: Add Document for Future Porting Guide
Documentation/riscv/pmu.txt | 249 +++
arch/riscv/Kconfig | 12 +
arch/riscv/include/asm
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
Documentation/riscv/pmu.txt | 249
1 file changed, 249 insertions(+)
create mode 100644 Documentation/riscv/pmu.txt
diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.txt
new
-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
Sorry for the lack of version prefix in the title. This patchset should be
version 2.
On Mon, Apr 02, 2018 at 08:31:22PM +0800, Alan Kao wrote:
> This implements the baseline PMU for RISC-V platforms.
>
> To ease future PMU portings, a guide is also written, containing
> perf co
On Thu, Apr 19, 2018 at 12:46:24PM -0700, Atish Patra wrote:
> On 4/17/18 7:13 PM, Alan Kao wrote:
> >This patch provide a basic PMU, riscv_base_pmu, which supports two
> >general hardware event, instructions and cycles. Furthermore, this
> >PMU serves as a reference imple
Reviewed-by: Alex Solomatnikov
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
Documentation/riscv/pmu.txt | 249
1 file changed, 249 insertions(+)
create mode 100644 Documentation/riscv/pmu.txt
diff --git a/Documentation/riscv/pmu.txt b
, which was caused by not sufficient
initialization. Check https://lkml.org/lkml/2018/3/31/251 for the
discussion.
Alan Kao (2):
perf: riscv: preliminary RISC-V support
perf: riscv: Add Document for Future Porting Guide
Documentation/riscv/pmu.txt | 249 ++
arch/riscv
-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
device-tree-based methods, and set default to the PMU proposed in
this patch.
Changes in v2:
- Fix the bug reported by Alex, which was caused by not sufficient
initialization. Check https://lkml.org/lkml/2018/3/31/251 for the
discussion.
Alan Kao (2):
perf: riscv: preliminary RISC-V
Reviewed-by: Alex Solomatnikov
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
Documentation/riscv/pmu.txt | 249
1 file changed, 249 insertions(+)
create mode 100644 Documentation/riscv/pmu.txt
diff --git a/Documentation/riscv/pmu.txt b
-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu
Cc: Greentime Hu
Signed-off-by: Alan Kao
---
On Tue, May 08, 2018 at 09:11:42AM -0400, Steven Rostedt wrote:
> On Tue, 8 May 2018 11:21:57 +0800
> Alan Kao wrote:
>
> > Enabling ftrace and module support at the same time fails the kernel
> > build process, because modules cannot find the _mcount symbol. This
>
1 - 100 of 127 matches
Mail list logo
