[PATCH v3 15/15] MIPS: OCTEON: irq: add CIB and other fixes

Rosenboim lrosenb...@caviumnetworks.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com Signed-off-by: Peter Swain peter.sw...@cavium.com --- .../devicetree/bindings/mips/cavium/cib.txt| 43 + arch/mips/cavium-octeon/octeon-irq.c | 1049 +++- 2 files

[PATCH v3 04/15] MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

From: Chandrakala Chavva ccha...@caviumnetworks.com Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/kernel/octeon_switch.S

[PATCH v3 07/15] MIPS: OCTEON: Add ability to used an initrd from a named memory block.

resolution] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/setup.c | 37 + arch/mips/include/asm/bootinfo.h | 1 + arch/mips/kernel/setup.c | 19 --- 3 files changed, 50 insertions(+), 7 deletions(-) diff

[PATCH v3 13/15] MIPS: OCTEON: More OCTEONIII support

From: Chandrakala Chavva ccha...@caviumnetworks.com Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII. Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com Signed-off-by: David Daney david.da

[PATCH v3 10/15] MIPS: OCTEON: Update octeon-model.h code for new SoCs.

From: David Daney david.da...@cavium.com Add coverage for OCTEON III models. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/dma-octeon.c | 4 +- .../cavium-octeon/executive/cvmx-helper

[PATCH v3 14/15] MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.

From: David Daney david.da...@cavium.com The acknowledge bits don't exist for level triggered irqs, so setting them causes the simulator to terminate. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Leonid Rosenboim lrosenb...@caviumnetworks.com Signed-off-by: Aleksey Makarov

[PATCH v3 11/15] MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.

From: David Daney david.da...@cavium.com Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/setup.c | 4 +--- .../asm/mach-cavium-octeon/kernel-entry-init.h| 19

[PATCH v3 05/15] MIPS: OCTEON: Delete unused COP2 saving code

Commit 2c952e06e4f5 (MIPS: Move cop2 save/restore to switch_to()) removes assembler code to store COP2 registers. Commit a36d8225bceb (MIPS: OCTEON: Enable use of FPU) mistakenly restores it Fixes: a36d8225bceb (MIPS: OCTEON: Enable use of FPU) Signed-off-by: Aleksey Makarov aleksey.maka

[PATCH v3 03/15] MIPS: OCTEON: Save and restore CP2 SHA3 state

From: David Daney david.da...@cavium.com Allocate new save space, and then save/restore the registers if OCTEON III. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/processor.h | 2 ++ arch/mips/kernel/asm

[PATCH v3 08/15] MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h

From: David Daney david.da...@cavium.com Also update union octeon_cvmemctl with new OCTEON II fields. Signed-off-by: David Daney david.da...@cavium.com [aleksey.maka...@auriga.com: use __BITFIELD_FIELD] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/octeon

[PATCH v3 02/15] MIPS: OCTEON: Fix FP context save.

From: David Daney david.da...@cavium.com It wasn't being saved on task switch. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/kernel/octeon_switch.S | 19 +++ 1 file changed, 7 insertions(+), 12 deletions

[PATCH v3 12/15] MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.

...@caviumnetworks.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 1 file changed, 20 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach

[PATCH v3 06/15] MIPS: OCTEON: Implement the core-16057 workaround

From: David Daney david.da...@cavium.com Disable ICache prefetch for certian Octeon II processors. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- .../asm/mach-cavium-octeon/kernel-entry-init.h | 22 ++ 1

[PATCH v3 00/15] MIPS: OCTEON: Some partial support for Octeon III

__KERNEL__ from asm/processor.h will be sent separately as it is not OCTEON specific Summary: These patches fix some issues in the Cavium Octeon code and introduce some partial support for Octeon III and little-endian. Also irq code was changed to support SATA and some other interrutps. Aleksey

[PATCH 3/3] MIPS: OCTEON: Use device tree to probe for flash chips.

From: David Daney Don't assume they are there, the device tree will tell us. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/flash_setup.c | 42 ++- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/mips

[PATCH 2/3] MIPS: OCTEON: Protect accesses to bootbus flash with octeon_bootbus_sem.

From: David Daney Without this, we get bus errors. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/flash_setup.c | 42 ++- 2 files changed, 42 insertions(+), 1 deletion

[PATCH 0/3] MIPS: OCTEON: flash: syncronize bootbus access

- Use semaphore to protect access to bootbus. - Use device tree to probe for flash chips. David Daney (3): MIPS: OCTEON: Add semaphore to serialize bootbus accesses. MIPS: OCTEON: Protect accesses to bootbus flash with octeon_bootbus_sem. MIPS: OCTEON: Use device tree to probe for

[PATCH 1/3] MIPS: OCTEON: Add semaphore to serialize bootbus accesses.

-by: Aleksey Makarov Signed-off-by: Chandrakala Chavva --- arch/mips/cavium-octeon/setup.c | 3 +++ arch/mips/include/asm/octeon/octeon.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 94f888d..7311338 100644 --- a/arch

[PATCH 0/3] MIPS: OCTEON: flash: syncronize bootbus access

- Use semaphore to protect access to bootbus. - Use device tree to probe for flash chips. David Daney (3): MIPS: OCTEON: Add semaphore to serialize bootbus accesses. MIPS: OCTEON: Protect accesses to bootbus flash with octeon_bootbus_sem. MIPS: OCTEON: Use device tree to probe for

[PATCH 1/3] MIPS: OCTEON: Add semaphore to serialize bootbus accesses.

...@auriga.com: combine the patches] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com --- arch/mips/cavium-octeon/setup.c | 3 +++ arch/mips/include/asm/octeon/octeon.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/mips

[PATCH 3/3] MIPS: OCTEON: Use device tree to probe for flash chips.

From: David Daney david.da...@cavium.com Don't assume they are there, the device tree will tell us. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/flash_setup.c | 42 ++- 1

[PATCH 2/3] MIPS: OCTEON: Protect accesses to bootbus flash with octeon_bootbus_sem.

From: David Daney david.da...@cavium.com Without this, we get bus errors. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/flash_setup.c | 42

[PATCH] MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h

From: David Daney Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/processor.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index f1df4cb..6c10e94 100644 --- a/arch/mips

[PATCH v2 12/12] MIPS: OCTEON: Handle OCTEON III in csrc-octeon.

From: David Daney The clock divisors are kept in different registers on OCTEON III. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/csrc-octeon.c | 34 ++ 1 file changed, 34 insertions(+) diff --git a/arch/mips/cavium

[PATCH v2 11/12] MIPS: OCTEON: Update octeon-model.h code for new SoCs.

From: David Daney Add coverage for OCTEON III models. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/octeon/octeon-model.h | 65 - 1 file changed, 63 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/octeon

[PATCH v2 08/12] MIPS: OCTEON: Add ability to used an initrd from a named memory block.

From: David Daney If 'rd_name=xxx' is passed to the kernel, the named block with name 'xxx' is used for the initrd. Signed-off-by: David Daney Signed-off-by: Leonid Rosenboim [aleksey.maka...@auriga.com: conflict resolution] Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/setup.c

[PATCH v2 09/12] MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h

From: David Daney Also update union octeon_cvmemctl with new OCTEON II fields. Signed-off-by: David Daney [aleksey.maka...@auriga.com: use __BITFIELD_FIELD] Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/octeon/octeon.h | 135 ++ 1 file changed, 105

[PATCH v2 06/12] MIPS: OCTEON: Implement the core-16057 workaround

From: David Daney Disable ICache prefetch for certian Octeon II processors. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- .../asm/mach-cavium-octeon/kernel-entry-init.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/mips/include/asm/mach

[PATCH v2 05/12] MIPS: OCTEON: Delete unused COP2 saving code

Commit 2c952e06e4f5 ("MIPS: Move cop2 save/restore to switch_to()") removes assembler code to store COP2 registers. Commit a36d8225bceb ("MIPS: OCTEON: Enable use of FPU") mistakenly restores it Fixes: a36d8225bceb ("MIPS: OCTEON: Enable use of FPU") Signed-off-

[PATCH v2 04/12] MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

From: Chandrakala Chavva Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by: Chandrakala Chavva Signed-off-by: Aleksey Makarov --- arch/mips/kernel/octeon_switch.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch

[PATCH v2 07/12] MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.

From: David Daney The acknowledge bits don't exist for level triggered irqs, so setting them causes the simulator to terminate. Signed-off-by: David Daney Signed-off-by: Leonid Rosenboim Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/octeon-irq.c | 45

[PATCH v2 03/12] MIPS: OCTEON: Save and restore CP2 SHA3 state

From: David Daney Allocate new save space, and then save/restore the registers if OCTEON III. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/processor.h | 2 ++ arch/mips/kernel/asm-offsets.c| 1 + arch/mips/kernel/octeon_switch.S | 43

[PATCH v2 01/12] MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs

resolution, support for old compilers] Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/setup.c | 37 ++ arch/mips/include/asm/octeon/octeon.h | 13 arch/mips/include/asm/ptrace.h| 4 +- arch/mips/kernel/octeon_switch.S | 128

[PATCH v2 02/12] MIPS: OCTEON: Fix FP context save.

From: David Daney It wasn't being saved on task switch. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/kernel/octeon_switch.S | 19 +++ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel

[PATCH v2 00/12] MIPS: OCTEON: Some partial support for Octeon III

the Cavium Octeon code and introduce some partial support for Octeon III and little-endian. Aleksey Makarov (1): MIPS: OCTEON: Delete unused COP2 saving code Chandrakala Chavva (1): MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register David Daney (10): MIPS: OCTEON: Save/Res

[PATCH v2 00/12] MIPS: OCTEON: Some partial support for Octeon III

Octeon code and introduce some partial support for Octeon III and little-endian. Aleksey Makarov (1): MIPS: OCTEON: Delete unused COP2 saving code Chandrakala Chavva (1): MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register David Daney (10): MIPS: OCTEON: Save/Restore wider

[PATCH v2 03/12] MIPS: OCTEON: Save and restore CP2 SHA3 state

From: David Daney david.da...@cavium.com Allocate new save space, and then save/restore the registers if OCTEON III. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/processor.h | 2 ++ arch/mips/kernel/asm

[PATCH v2 01/12] MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs

...@caviumnetworks.com [aleksey.maka...@auriga.com: conflict resolution, support for old compilers] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/setup.c | 37 ++ arch/mips/include/asm/octeon/octeon.h | 13 arch/mips

[PATCH v2 02/12] MIPS: OCTEON: Fix FP context save.

From: David Daney david.da...@cavium.com It wasn't being saved on task switch. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/kernel/octeon_switch.S | 19 +++ 1 file changed, 7 insertions(+), 12 deletions

[PATCH v2 07/12] MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.

From: David Daney david.da...@cavium.com The acknowledge bits don't exist for level triggered irqs, so setting them causes the simulator to terminate. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Leonid Rosenboim lrosenb...@caviumnetworks.com Signed-off-by: Aleksey Makarov

[PATCH v2 06/12] MIPS: OCTEON: Implement the core-16057 workaround

From: David Daney david.da...@cavium.com Disable ICache prefetch for certian Octeon II processors. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- .../asm/mach-cavium-octeon/kernel-entry-init.h | 22 ++ 1

[PATCH v2 05/12] MIPS: OCTEON: Delete unused COP2 saving code

Commit 2c952e06e4f5 (MIPS: Move cop2 save/restore to switch_to()) removes assembler code to store COP2 registers. Commit a36d8225bceb (MIPS: OCTEON: Enable use of FPU) mistakenly restores it Fixes: a36d8225bceb (MIPS: OCTEON: Enable use of FPU) Signed-off-by: Aleksey Makarov aleksey.maka

[PATCH v2 04/12] MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

From: Chandrakala Chavva ccha...@caviumnetworks.com Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/kernel/octeon_switch.S

[PATCH v2 08/12] MIPS: OCTEON: Add ability to used an initrd from a named memory block.

resolution] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/setup.c | 37 + arch/mips/include/asm/bootinfo.h | 1 + arch/mips/kernel/setup.c | 19 --- 3 files changed, 50 insertions(+), 7 deletions(-) diff

[PATCH v2 09/12] MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h

From: David Daney david.da...@cavium.com Also update union octeon_cvmemctl with new OCTEON II fields. Signed-off-by: David Daney david.da...@cavium.com [aleksey.maka...@auriga.com: use __BITFIELD_FIELD] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/octeon

[PATCH v2 12/12] MIPS: OCTEON: Handle OCTEON III in csrc-octeon.

From: David Daney david.da...@cavium.com The clock divisors are kept in different registers on OCTEON III. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/csrc-octeon.c | 34

[PATCH v2 11/12] MIPS: OCTEON: Update octeon-model.h code for new SoCs.

From: David Daney david.da...@cavium.com Add coverage for OCTEON III models. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/octeon/octeon-model.h | 65 - 1 file changed, 63

[PATCH] MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h

From: David Daney david.da...@cavium.com Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/processor.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips

Re: [PATCH 09/14] MIPS: OCTEON: Add ability to used an initrd from a named memory block.

On 12/15/2014 11:53 PM, Aaro Koskinen wrote: > On Mon, Dec 15, 2014 at 09:03:15PM +0300, Aleksey Makarov wrote: >> From: David Daney >> >> If 'rd_name=xxx' is passed to the kernel, the named block with name >> 'xxx' is used for the initrd. > > Maybe use &quo

Re: [PATCH 09/14] MIPS: OCTEON: Add ability to used an initrd from a named memory block.

On 12/15/2014 11:53 PM, Aaro Koskinen wrote: On Mon, Dec 15, 2014 at 09:03:15PM +0300, Aleksey Makarov wrote: From: David Daney david.da...@cavium.com If 'rd_name=xxx' is passed to the kernel, the named block with name 'xxx' is used for the initrd. Maybe use initrd_name for consistency

[PATCH 06/14] MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h

From: David Daney Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/processor.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index a5b8a7f..728b05a 100644 --- a/arch/mips

[PATCH 07/14] MIPS: OCTEON: Implement the core-16057 workaround

From: David Daney Disable ICache prefetch for certian Octeon II processors. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- .../asm/mach-cavium-octeon/kernel-entry-init.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/mips/include/asm/mach

[PATCH 09/14] MIPS: OCTEON: Add ability to used an initrd from a named memory block.

From: David Daney If 'rd_name=xxx' is passed to the kernel, the named block with name 'xxx' is used for the initrd. Signed-off-by: David Daney Signed-off-by: Leonid Rosenboim [aleksey.maka...@auriga.com: conflict resolution] Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/setup.c

[PATCH 13/14] MIPS: OCTEON: Add register definitions for OCTEON III reset unit.

From: David Daney Needed by follow-on patches. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/octeon/cvmx-rst-defs.h | 441 +++ 1 file changed, 441 insertions(+) create mode 100644 arch/mips/include/asm/octeon/cvmx-rst-defs.h

[PATCH 12/14] MIPS: OCTEON: Update octeon-model.h code for new SoCs.

From: David Daney Add coverage for OCTEON III models. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/octeon/octeon-model.h | 65 - 1 file changed, 63 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/octeon

[PATCH 14/14] MIPS: OCTEON: Handle OCTEON III in csrc-octeon.

From: David Daney The clock divisors are kept in different registers on OCTEON III. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/csrc-octeon.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b

[PATCH 10/14] MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h

From: David Daney Also update union octeon_cvmemctl with new OCTEON II fields. Signed-off-by: David Daney [aleksey.maka...@auriga.com: use __BITFIELD_FIELD] Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/octeon/octeon.h | 135 ++ 1 file changed, 105

[PATCH 08/14] MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.

From: David Daney The acknowledge bits don't exist for level triggered irqs, so setting them causes the simulator to terminate. Signed-off-by: David Daney Signed-off-by: Leonid Rosenboim Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/octeon-irq.c | 45

[PATCH 05/14] MIPS: OCTEON: Delete unused COP2 saving code

Commit 2c952e06e4f5 ("MIPS: Move cop2 save/restore to switch_to()") removes assembler code to store COP2 registers. Commit a36d8225bceb ("MIPS: OCTEON: Enable use of FPU") mistakenly restores it Fixes: a36d8225bceb ("MIPS: OCTEON: Enable use of FPU") Signed-off-

[PATCH 03/14] MIPS: OCTEON: Save and restore CP2 SHA3 state

From: David Daney Allocate new save space, and then save/restore the registers if OCTEON III. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/include/asm/processor.h | 2 ++ arch/mips/kernel/asm-offsets.c| 1 + arch/mips/kernel/octeon_switch.S | 43

[PATCH 02/14] MIPS: OCTEON: Fix FP context save.

From: David Daney It wasn't being saved on task switch. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- arch/mips/kernel/octeon_switch.S | 19 +++ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel

[PATCH 01/14] MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs

resolution, support for old compilers] Signed-off-by: Aleksey Makarov --- arch/mips/cavium-octeon/setup.c | 37 ++ arch/mips/include/asm/octeon/octeon.h | 13 arch/mips/include/asm/ptrace.h| 4 +- arch/mips/kernel/octeon_switch.S | 128

[PATCH 04/14] MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

From: Chandrakala Chavva Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by: Chandrakala Chavva Signed-off-by: Aleksey Makarov --- arch/mips/kernel/octeon_switch.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch

[PATCH 00/14] MIPS: OCTEON: Some partial support for Octeon III

These patches fix some issues in the Cavium Octeon code and introduce some partial support for Octeon III and little-endian. Aleksey Makarov (1): MIPS: OCTEON: Delete unused COP2 saving code Chandrakala Chavva (1): MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register David

[PATCH 00/14] MIPS: OCTEON: Some partial support for Octeon III

These patches fix some issues in the Cavium Octeon code and introduce some partial support for Octeon III and little-endian. Aleksey Makarov (1): MIPS: OCTEON: Delete unused COP2 saving code Chandrakala Chavva (1): MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register David

[PATCH 02/14] MIPS: OCTEON: Fix FP context save.

From: David Daney david.da...@cavium.com It wasn't being saved on task switch. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/kernel/octeon_switch.S | 19 +++ 1 file changed, 7 insertions(+), 12 deletions

[PATCH 01/14] MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs

...@caviumnetworks.com [aleksey.maka...@auriga.com: conflict resolution, support for old compilers] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/setup.c | 37 ++ arch/mips/include/asm/octeon/octeon.h | 13 arch/mips

[PATCH 04/14] MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

From: Chandrakala Chavva ccha...@caviumnetworks.com Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by: Chandrakala Chavva ccha...@caviumnetworks.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/kernel/octeon_switch.S

[PATCH 03/14] MIPS: OCTEON: Save and restore CP2 SHA3 state

From: David Daney david.da...@cavium.com Allocate new save space, and then save/restore the registers if OCTEON III. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/processor.h | 2 ++ arch/mips/kernel/asm

[PATCH 05/14] MIPS: OCTEON: Delete unused COP2 saving code

Commit 2c952e06e4f5 (MIPS: Move cop2 save/restore to switch_to()) removes assembler code to store COP2 registers. Commit a36d8225bceb (MIPS: OCTEON: Enable use of FPU) mistakenly restores it Fixes: a36d8225bceb (MIPS: OCTEON: Enable use of FPU) Signed-off-by: Aleksey Makarov aleksey.maka

[PATCH 08/14] MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.

From: David Daney david.da...@cavium.com The acknowledge bits don't exist for level triggered irqs, so setting them causes the simulator to terminate. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Leonid Rosenboim lrosenb...@caviumnetworks.com Signed-off-by: Aleksey Makarov

[PATCH 12/14] MIPS: OCTEON: Update octeon-model.h code for new SoCs.

From: David Daney david.da...@cavium.com Add coverage for OCTEON III models. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/octeon/octeon-model.h | 65 - 1 file changed, 63

[PATCH 14/14] MIPS: OCTEON: Handle OCTEON III in csrc-octeon.

From: David Daney david.da...@cavium.com The clock divisors are kept in different registers on OCTEON III. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/csrc-octeon.c | 10 ++ 1 file changed, 10

[PATCH 13/14] MIPS: OCTEON: Add register definitions for OCTEON III reset unit.

From: David Daney david.da...@cavium.com Needed by follow-on patches. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/octeon/cvmx-rst-defs.h | 441 +++ 1 file changed, 441 insertions

[PATCH 10/14] MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h

From: David Daney david.da...@cavium.com Also update union octeon_cvmemctl with new OCTEON II fields. Signed-off-by: David Daney david.da...@cavium.com [aleksey.maka...@auriga.com: use __BITFIELD_FIELD] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/octeon

[PATCH 09/14] MIPS: OCTEON: Add ability to used an initrd from a named memory block.

resolution] Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/cavium-octeon/setup.c | 37 + arch/mips/include/asm/bootinfo.h | 1 + arch/mips/kernel/setup.c | 19 --- 3 files changed, 50 insertions(+), 7 deletions(-) diff

[PATCH 06/14] MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h

From: David Daney david.da...@cavium.com Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- arch/mips/include/asm/processor.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips

[PATCH 07/14] MIPS: OCTEON: Implement the core-16057 workaround

From: David Daney david.da...@cavium.com Disable ICache prefetch for certian Octeon II processors. Signed-off-by: David Daney david.da...@cavium.com Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- .../asm/mach-cavium-octeon/kernel-entry-init.h | 22 ++ 1

[PATCH] serial: 8250_dw: Use 64-bit access for OCTEON.

for OCTEON. This code is protected with #ifdef CONFIG_64BIT so it still builds under configurations lacking readq/writeq. We can get rid of the #ifdef __BIG_ENDIAN, as under 64-bit accesses, OCTEON is byte order invariant. Signed-off-by: David Daney Signed-off-by: Aleksey Makarov --- drivers

[PATCH] serial: 8250_dw: Use 64-bit access for OCTEON.

Signed-off-by: Aleksey Makarov aleksey.maka...@auriga.com --- drivers/tty/serial/8250/8250_dw.c | 55 +-- 1 file changed, 41 insertions(+), 14 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index beea6ca..6232d15

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