The goal of this series is to add I2C support to ST SoCs.
The DT definition is added for STiH415 and STiH416 SoCs on
B2000 and B2020 boards.
The series has been tested working on STiH416-B2020 board.
It applies on top of v3.12-rc1.
Changes since v1:
- Anti-glitch filtering simplified (Only HW A
From: Alexandre Torgue
Android expects the RTC to have second resolution.
On ab8540 cut2 RTC block has a new register which
allows setting seconds for wakeup alarms.
Alexandre Torgue (2):
mfd: ab8540: add device for new rtc version on ab8540 cut2
rtc: ab8540: add second resolution to rtc
From: Alexandre Torgue
Android expects the RTC to have second resolution. On ab8540 cut2 RTC
block has a new register which allows setting seconds for wakeup
alarms.
Existing registers (minutes hi, mid and low) have seen their offsets
changed. Here is the new mapping:
* AlarmSec (A) 0x22
From: Alexandre Torgue
AB8540 rtc have changed between AB8540_cut1 and AB8540_cut2.Different
ressources to define for those two version.
Signed-off-by: Julien Delacou
Signed-off-by: Alexandre Torgue
Acked-by: Lee Jones
Acked-by: Linus Walleij
diff --git a/drivers/mfd/ab8500-core.c b
Hi Thomas,
On 09/14/2016 03:44 PM, Alexandre Torgue wrote:
On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
On Wed, 14 Sep 2016, Alexandre Torgue wrote:
On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
Now what really bugs me is that you do that at all. An interrupt
which is
freed must be
Thomas,
On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
On Tue, 20 Sep 2016, Alexandre Torgue wrote:
On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
Well, you just used some function in some context which is not
relevant to
the normal operation. So adding that mask() is just paranoia for no
Thomas,
On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
On Tue, 20 Sep 2016, Alexandre Torgue wrote:
Thomas,
On 09/20/2016 11:51 AM, Thomas Gleixner wrote:
On Tue, 20 Sep 2016, Alexandre Torgue wrote:
On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
Well, you just used some function in some
Thomas,
On 09/20/2016 04:02 PM, Thomas Gleixner wrote:
On Tue, 20 Sep 2016, Alexandre Torgue wrote:
On 09/20/2016 02:44 PM, Thomas Gleixner wrote:
Free will be called when a interrupt in the child domain is torn down,
i.e. when irq_domain_free_irqs() is called. And it will be called for both
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 000..6e7703d
--- /dev/null
+++ b
Changes since v1:
-
- Rebased on top of v4.6-rc1
- Change variable name from virq to irq (Linus W.)
Alexandre TORGUE (4):
Documentation: dt-bindings: Document STM32 EXTI controller bindings
drivers: irqchip: Add STM32 external interrupts support
ARM: STM32: Select external
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d601d7..157cea9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -877,6 +877,7 @@ config ARCH_STM32
select CLKSRC_STM32
select PINCTRL
select
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14
.
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
help
Hi Thomas,
On 09/20/2016 10:16 PM, Thomas Gleixner wrote:
Alexandre,
On Tue, 20 Sep 2016, Alexandre TORGUE wrote:
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt or
Hi Thomas,
On 09/02/2016 09:10 PM, Thomas Gleixner wrote:
> On Fri, 2 Sep 2016, Alexandre TORGUE wrote:
>> +static int stm32_gpio_domain_translate(struct irq_domain *d,
>> + struct irq_fwspec *fwspec,
>> +
Hi Jason,
On 09/06/2016 07:37 PM, Jason Cooper wrote:
On Tue, Sep 06, 2016 at 06:45:34PM +0200, Alexandre TORGUE wrote:
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as
Hi Thomas,
On 09/02/2016 08:57 PM, Thomas Gleixner wrote:
> Alexandre,
>
> On Fri, 2 Sep 2016, Alexandre TORGUE wrote:
>
> This all looks very reasonable. The only complaint I have is your variable
> declaration ordering or the lack thereof.
>
> 1)
>>
Hi Linus,
On 09/07/2016 11:06 PM, Linus Walleij wrote:
On Tue, Sep 6, 2016 at 6:45 PM, Alexandre TORGUE
wrote:
This patch adds IRQ support to STM32 gpios.
The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example
Hi Linus,
On 09/13/2016 10:18 AM, Linus Walleij wrote:
On Fri, Sep 9, 2016 at 4:42 PM, Alexandre TORGUE
wrote:
Signed-off-by: Maxime Coquelin
Acked-by: Rob Herring
Signed-off-by: Alexandre TORGUE
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
b/Documentation
Hi Thomas,
On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *data = irq_get_irq_data(virq
Hi Thomas,
On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
On Tue, 13 Sep 2016, Alexandre Torgue wrote:
On 09/13/2016 05:21 PM, Thomas Gleixner wrote:
On Fri, 9 Sep 2016, Alexandre TORGUE wrote:
+static void stm32_exti_free(struct irq_domain *d, unsigned int virq
On 09/14/2016 03:34 PM, Thomas Gleixner wrote:
On Wed, 14 Sep 2016, Alexandre Torgue wrote:
On 09/14/2016 11:19 AM, Thomas Gleixner wrote:
Now what really bugs me is that you do that at all. An interrupt which is
freed must be masked already. Why is it unmasked in the first place
s since v1:
-
- Rebased on top of v4.6-rc1
- Change variable name from virq to irq (Linus W.)
Alexandre TORGUE (9):
Documentation: dt-bindings: Document STM32 EXTI controller bindings
drivers: irqchip: Add STM32 external interrupts support
ARM: STM32: Select external interrupts controller
ARM
System
Config registers.
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 4c40dae..40d5abc 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -6,6 +6,8 @@ config
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 1e5ec2a..e7b56d4 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -38,7 +38,11 @@ CONFIG_DEVTMPFS_MOUNT=y
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 1a189d4..6824762 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -189,6 +189,8
Signed-off-by: Maxime Coquelin
Acked-by: Rob Herring
Signed-off-by: Alexandre TORGUE
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 587bffb..a0eed99 100644
--- a/Documentation/devicetree
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
index 6bfc595..0fd78e4 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -47,6 +47,7 @@
/dts
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d601d7..157cea9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -877,6 +877,7 @@ config ARCH_STM32
select CLKSRC_STM32
select PINCTRL
select
.
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
help
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
new file mode 100644
index 000..6e7703d
--- /dev/null
+++ b
Hi Amélie,
On 08/28/2017 04:20 PM, Amelie Delaunay wrote:
The STM32F7 MCU family embeds two DWC2 USB OTG cores. One core is USB
OTG FS and the other is USB OTG HS. The USB FS core only works with its
internal phy whilst the USB HS core can work in HS with external ULPI phy
or in FS/LS with the o
Hi
On 09/28/2017 05:36 PM, Pierre-Yves MORDRET wrote:
This patch adds MDMA support for STM32H743 SoC.
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v5:
v4:
v3:
* None
v2:
* Add MDMA support in DT for H7
---
---
arch/arm/boot/dts/stm32h743.dts
hi
On 09/28/2017 05:36 PM, Pierre-Yves MORDRET wrote:
This patch adds MDMA support in STM32 defconfig file
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v5:
v4:
v3:
* None
v2:
* Add MDMA support in STM32 defconfig
---
---
arch/arm/configs/stm
iolib"
interface or "common" interrupt interface.
Changes since v1:
-rebase on 4.12-rc1
-Let gpiochip and irqchip orthogonal in stm32 pinctrl driver
-Don't use gpiolib internal define
Regards
Alex
Alexandre TORGUE (3):
pinctrl: stm32: set pin to gpio input when used as i
This patch ensures that pin is correctly set as gpio input when it is used
as an interrupt.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index d3c5f5d..5a15c7d 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b
Add .get_direction() gpiochip callback in STM32 pinctrl driver.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 5a15c7d..814f76c 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32
This patch set each gpio controller as a interrupt controller. User who
wants to use gpio as interrupt will have choice to use either "gpiolib"
interface or "common" interrupt interface.
Acked-by: Linus Walleij
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/
In stm32_pconf_parse_conf function, stm32_pmx_gpio_set_direction is
called with wrong parameter value. Indeed, using NULL value for range
will raise an oops.
Fixes: aceb16dc2da5 ("pinctrl: Add STM32 MCUs support")
Reported-by: Dan Carpenter
Signed-off-by: Alexandre TORGUE
diff --git
Hi Patrice
On 08/07/2018 01:06 PM, patrice.chot...@st.com wrote:
From: Patrice Chotard
Fix the following DT dtc warnings for stm32h743 boards:
Warning (node_name_chars_strict): /clocks/i2s_ckin: Character '_' not
recommended in node name
Warning (unit_address_vs_reg): /memory: node has a reg
On 08/07/2018 01:06 PM, patrice.chot...@st.com wrote:
From: Patrice Chotard
Fix the following DT dtc warnings for stm32f746 and stm32f769
boards:
Warning (node_name_chars_strict): /soc/pin-controller/sdio_pins_a@0: Character
'_' not recommended in node name
Warning (node_name_chars_strict)
Hi Patrice
On 08/07/2018 01:06 PM, patrice.chot...@st.com wrote:
From: Patrice Chotard
Fix the following DT dtc warnings for stm32f429 and
stm32f469 boards:
Warning (node_name_chars_strict): /soc/pin-controller/usbotg_fs@0: Character
'_' not recommended in node name
Warning (node_name_chars_
Hi Patrice
On 08/07/2018 01:38 PM, Alexandre Torgue wrote:
+ #address-cells = <1>;
+ #size-cells = <1>;
+
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
@@ -60,7 +62,7 @@
clock-frequency = <32768>;
};
-
Hi Amélie,
On 05/09/2018 05:18 PM, Amelie Delaunay wrote:
With the lastest STM32 RTC driver updates, it is mandatory to define
pwrcfg control register and DBP (Disable Backup Protection) bit through
st,syscfg property. This patchset updates RTC nodes on stm32f429 and
stm32f746 accordingly.
Amel
Hi Lionel,
On 05/14/2018 12:00 PM, Lionel Debieve wrote:
This patch add HASH instance of the stm32mp157c SoC
Signed-off-by: Lionel Debieve
---
arch/arm/boot/dts/stm32mp157c.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi
b/arch/arm/
Hi Guenter,
But you are right I forgot to change stm32f429.dtsi.
If I add a commit for stm32f429.dtsi, it's Ok for you ?
Not really. You are imposing a personal preference on others,
and you would make stm32f429.dtsi inconsistent since it doesn't
use clock names for anything else.This in tur
On 06/25/2018 03:15 PM, Guenter Roeck wrote:
On 06/25/2018 05:52 AM, Alexandre Torgue wrote:
Hi Guenter,
But you are right I forgot to change stm32f429.dtsi.
If I add a commit for stm32f429.dtsi, it's Ok for you ?
Not really. You are imposing a personal preference on others,
an
Hi Linus
On 07/29/2018 10:11 PM, Linus Walleij wrote:
On Mon, Jul 16, 2018 at 2:57 PM Alexandre Torgue
wrote:
Register a new GPIO bank only if GPIO bank node is enabled. This patch also
adds checks on ranges which are defined only if a bank is registered.
Signed-off-by: Alexandre Torgue
Hi Rob
On 07/20/2018 06:35 PM, Rob Herring wrote:
On Mon, Jul 16, 2018 at 02:57:36PM +0200, Alexandre Torgue wrote:
In case the exti line is not in line with the bank number (that is the case
when there is an hole between two banks, for example GPIOK and then GPIOZ),
use "st,bank-iopor
Hi Ludovic
On 06/25/2018 05:42 PM, Ludovic Barre wrote:
From: Ludovic Barre
This patch series updates stm32_iwdg driver to manage pclk
clock by compatible. stm32mp1 requires a pclk clock.
v5:
-update stm32f429.dtsi
v4:
-dt-bindings: split and review
v3:
-remove stm32_iwdg_config structure,
Hi Patrice,
On 01/18/2018 03:34 PM, patrice.chot...@st.com wrote:
From: Patrice Chotard
This series reworks patches submitted one year ago by Andrea Merello [1]
but without succeed to merged it.
STM32F4 and STM32F7 SoCs families embeds a variant of the ARM PrimeCell
PL18x SD host controller,
Hi Ludovic
On 01/16/2018 03:56 PM, Ludovic Barre wrote:
From: Ludovic Barre
This patch series extends the existing STM32 microcontrollers (MCUs)
family to microprocessors (MPUs). The MPU platform (based on
Arm Cortex-A) is a continuation of the MCU one (based on Arm
Cortex-M) in that it shares
On 01/22/2018 09:25 AM, Linus Walleij wrote:
On Mon, Dec 11, 2017 at 9:54 AM, Alexandre Torgue
wrote:
This patch which adds STM32F769 pinctrl and GPIO support, relies on the
generic STM32 pinctrl driver.
Signed-off-by: Alexandre Torgue
Patch applied as Patrice poked me.
I hope it works
Hi Pierre-Yves
On 03/12/2018 01:53 PM, Pierre-Yves MORDRET wrote:
Before assigning returned setup structure check if not null
Fixes: 463a9215f3ca7600b5ff ("i2c: stm32f7: fix setup structure")
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
dri
7;t get device data\n");
+ ret = -ENODEV;
+ goto clk_free;
+ }
i2c_dev->setup = *setup;
ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
Acked-by: Alexandre TORGUE
Hi Lee
On 03/07/2018 11:57 AM, Lee Jones wrote:
On Wed, 07 Mar 2018, Patrice CHOTARD wrote:
Hi Lee
On 03/07/2018 09:35 AM, Lee Jones wrote:
On Mon, 05 Mar 2018, Alexandre Torgue wrote:
Hi Patrice,
On 03/01/2018 11:53 AM, patrice.chot...@st.com wrote:
From: Patrice Chotard
This series
Hi Benjamin
On 11/8/18 10:04 AM, Benjamin Gaignard wrote:
Add bindings for STM32 hardware spinlock device
Signed-off-by: Benjamin Gaignard
---
version 2 :
- change clock name from hwspinlock to hsem to be align with hardware
documentation
.../bindings/hwlock/st,stm32-hwspinlock.txt
Hi Fabrice
On 10/3/18 5:11 PM, Fabrice Gasnier wrote:
This series adds dmas description to stm32mp157c device tree file.
But dmas are kept disabled by default on all boards. They are only
necessary for PWM capture. So, spare them for other usage by default.
Fabrice Gasnier (3):
ARM: dts: stm
Hi Benjamin
On 11/12/18 4:23 PM, Benjamin Gaignard wrote:
This serie adds the support of the hardware semaphore block for stm32mp1 SoC.
version 3:
- fix clock name in properties description.
- use postcore_initcall() instead of module_platform_driver()
version 2:
- fix comments done by Bjorn a
Hi Benjamin
On 11/13/18 10:51 AM, Benjamin Gaignard wrote:
Define a hwspinlock to be used by pin-controller
Signed-off-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 1 +
1 file changed, 1 insertion(+)
In commit title please add for which SoC it is targeted. If you
(+), 1 deletion(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index a9bec6e6fdd1..dce9dabaf4d5 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,7 @@
Acked-by: Alexandre TORGUE
Hi Benjamin,
On 11/12/18 4:23 PM, Benjamin Gaignard wrote:
This serie adds the support of the hardware semaphore block for stm32mp1 SoC.
version 3:
- fix clock name in properties description.
- use postcore_initcall() instead of module_platform_driver()
version 2:
- fix comments done by Bjorn
Hi Bich,
On 11/15/18 9:52 AM, Bich HEMON wrote:
This patchset changes the CAN RAM mapping and adds CAN sleep pins.
Bich Hemon (3):
ARM: dts: stm32: change CAN RAM mapping on stm32mp157c
ARM: dts: stm32: add can1 sleep pins muxing
ARM: dts: stm32: add can1 sleep pins muxing on stm32mp15
Hi David,
On 10/5/18 12:08 PM, David HERNANDEZ SANCHEZ wrote:
Add configuration on DT for thermal sensor driver
Signed-off-by: David Hernandez Sanchez
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi
b/arch/arm/boot/dts/stm32mp157c.dtsi
index 661be94..e90b9f6 100644
--- a/arch/arm/boot/dts/s
Hi Fabrice,
On 10/3/18 4:41 PM, Fabrice Gasnier wrote:
This enables drivers for STM32 timer, low power timer and analog hardware
that can be used on STM32MP1 SoC:
- Timer & LP Timer MFD core, PWM, trigger & encoder drivers
- IIO ADC/DAC/DFSDM
- vrefbuf regu driver (voltage reference buffer).
Si
Hi Amélie,
On 05/17/2018 02:07 PM, Amelie Delaunay wrote:
This series adds support for STM32 RTC to stm32mp157c SoC and enables it
on stm32mp157c-ed1 board.
---
Changes in v2:
* Enable STM32 RTC in multi_v7_defconfig
Amelie Delaunay (3):
ARM: dts: stm32: add RTC support to stm32mp157c
AR
Hi Amélie
On 05/17/2018 04:21 PM, Amelie Delaunay wrote:
Enable the STM32 SPI driver, implemented on STM32MP1 SoC.
Signed-off-by: Amelie Delaunay
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/confi
Hi Amélie,
On 05/17/2018 04:36 PM, Amelie Delaunay wrote:
This patch enables USB Host (USBH) EHCI controller on stm32mp157c-ev1.
As a hub is used between USBH and USB connectors, no need to enable
USBH OHCI controller: all low- and full-speed traffic is managed by the
hub.
Signed-off-by: Amelie
Hi, Pierre-Yves
On 05/28/2018 11:08 AM, Pierre-Yves MORDRET wrote:
This enables drivers for STM32:
- DMAv2
- DMMAUX
- MDMA
Signed-off-by: Pierre-Yves MORDRET
---
Version history:
v1:
* Initial
---
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 ins
Hi Amélie
On 05/17/2018 05:47 PM, Amelie Delaunay wrote:
This patchset adds support for USB OTG HS on stm32mp157c SoC.
It also enables USB OTG HS on stm32mp157c-ev1 board in Peripheral mode.
Amelie Delaunay (2):
ARM: dts: stm32: add USB OTG HS support for stm32mp157c SoC
ARM: dts: stm32:
Hi Fabrice
On 05/22/2018 05:45 PM, Fabrice Gasnier wrote:
stm32mp157c has an ADC block with two physical ADCs.
Signed-off-by: Fabrice Gasnier
---
Changes in v3:
- Add dmas since dmamux1 has been added on top of stm32-next
---
arch/arm/boot/dts/stm32mp157c.dtsi | 36 ++
On 06/26/2018 01:47 PM, Amelie DELAUNAY wrote:
Hi Alex
On 06/26/2018 10:44 AM, Alexandre Torgue wrote:
Hi Amélie
On 05/17/2018 04:21 PM, Amelie Delaunay wrote:
Enable the STM32 SPI driver, implemented on STM32MP1 SoC.
Signed-off-by: Amelie Delaunay
---
arch/arm/configs
Hi Fabrice,
On 05/23/2018 11:30 AM, Fabrice Gasnier wrote:
stm32mp157c has DFSDM (Digital Filter For Sigma Delta Modulators) hardware
with 6 filter instances.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157c.dtsi | 70 ++
1 file changed, 70
Hi Amélie,
On 05/17/2018 04:21 PM, Amelie Delaunay wrote:
This patch adds STM32 SPI support on stm32mp157c SoC.
SPI1, available on GPIO expansion connector, is kept disabled, so these
pins can be used as GPIOs by default.
Amelie Delaunay (3):
ARM: dts: stm32: add STM32 SPI support on stm32mp
Hi Guenter
On 06/25/2018 05:42 PM, Ludovic Barre wrote:
From: Ludovic Barre
This patch series updates stm32_iwdg driver to manage pclk
clock by compatible. stm32mp1 requires a pclk clock.
v5:
-update stm32f429.dtsi
v4:
-dt-bindings: split and review
v3:
-remove stm32_iwdg_config structure,
On 05/05/2018 04:45 AM, Stephen Boyd wrote:
Quoting Alexandre Torgue (2018-05-04 00:54:16)
Stephen
On 05/03/2018 08:40 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
Clock driver is mandatory if the machine is selected.
Then don't use 'bool' and 'depen
Hi Ludovic
On 06/20/2018 09:53 AM, Ludovic Barre wrote:
From: Ludovic Barre
This patch series updates stm32_iwdg driver to manage config
by compatible. stm32mp1 config requires a pclk clock.
Ludovic Barre (3):
watchdog: stm32: add pclk feature for stm32mp1
ARM: dts: stm32: add iwdg2 sup
Hi Marc,
On 12/18/18 4:39 PM, Marc Zyngier wrote:
On 17/12/2018 14:22, Benjamin Gaignard wrote:
This series allow to protect STM32 interrupt controller configuration registers
with a hwspinlock to avoid conflicting accesses between processors.
version 3:
- with bindings patch
version 2:
- rew
On 09/17/2018 10:24 AM, Benjamin Gaignard wrote:
Add mailing list for stm32 architecture.
Add "stm" pattern to not miss some drivers/directories when asking for
maintainers.
Signed-off-by: Benjamin Gaignard
---
Thanks Benjamin!
Acked-by: Alexandre TORGUE
MAINTAINERS | 2 +
Register a new GPIO bank only if GPIO bank node is enabled. This patch also
adds checks on ranges which are defined only if a bank is registered.
Signed-off-by: Alexandre Torgue
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index eb6ae14..111225e
Hi,
This series includes two updates for stm32 pinctrl driver:
-Fixes the way to map a gpio bank to an EXTi line.
-Check "status" devicetree entry (in gpio-contriller node) before registering
a new gpio bank.
Regards
Alex
Alexandre Torgue (2):
pinctrl: stm32: fix bank io p
In case the exti line is not in line with the bank number (that is the case
when there is an hole between two banks, for example GPIOK and then GPIOZ),
use "st,bank-ioport" DT property to get the right exti line.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alexandre Torgue
di
c> with:
-(phandle): phandle of pin-controller.
Acked-by: Alexandre TORGUE
kward compatibility, the drivers set
the legacy value by default.
Signed-off-by: Ludovic Barre
Acked-by: Alexandre TORGUE
---
drivers/pinctrl/stm32/pinctrl-stm32.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/dr
Hi Patrice
On 03/01/2018 10:43 AM, patrice.chot...@st.com wrote:
From: Patrice Chotard
Add sdio pins definition for the 2 sdio instances embeds in stm32f746.
Signed-off-by: Patrice Chotard
---
arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 62 ++
1 file changed,
Hi Fabrice,
On 04/17/2018 03:45 PM, Fabrice Gasnier wrote:
This series adds support for STM32 timers to stm32mp157c. These
timers can act PWM, trigger and/or encoder.
Populate stm32mp157c SOC and ed1/ev1 boards.
Fabrice Gasnier (4):
ARM: dts: stm32: add timers support to stm32mp157c
ARM:
Hi Fabrice,
On 04/18/2018 09:47 AM, Fabrice Gasnier wrote:
stm32mp157c has vrefbuf regulator that can provide analog reference
voltage from 1500mV to 2500mV.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157c.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/ar
Hi Fabrice
On 04/18/2018 09:43 AM, Fabrice Gasnier wrote:
Add LPtimer definitions, depending on features they provide:
- lptimer1 & 2 can act as PWM, trigger and encoder/counter
- lptimer3 can act as PWM and trigger
- lptimer4 & 5 can act as PWM
Signed-off-by: Fabrice Gasnier
---
Applied on
Hi Gabriel,
On 04/20/2018 11:09 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch adds reset binding file.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stm32mp157c.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi
b
Hi Fabrice
On 04/18/2018 05:46 PM, Fabrice Gasnier wrote:
Add support for DAC (Digital to Analog Converter) to STM32MP157C.
STM32MP157C DAC has two output channels.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157c.dtsi | 24
1 file changed, 24 insert
On 05/02/2018 04:07 PM, Jose Abreu wrote:
On 02-05-2018 13:36, Kees Cook wrote:
On Wed, May 2, 2018 at 1:54 AM, Jose Abreu wrote:
Hi Kees,
On 01-05-2018 22:01, Kees Cook wrote:
In the quest to remove all stack VLAs from the kernel[1], this switches
the "status" stack buffer to use the ex
Hi
On 04/20/2018 11:14 AM, Pierre-Yves MORDRET wrote:
This patch adds DMAv2 and DMAMUX support on STM32MP157C with configs and device
tree.
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (4):
ARM: configs: stm32: Add DMAv2 support on STM32MP157C machine
ARM:
Hi,
On 04/20/2018 11:15 AM, Pierre-Yves MORDRET wrote:
This patch adds MDMA support on STM32MP157C with configs and device tree.
---
Version history:
v1:
* Initial
---
Pierre-Yves MORDRET (2):
ARM: configs: stm32: Add MDMA support on STM32MP157C
ARM: dts: stm32: Add MDMA
Hi Lionel,
On 04/23/2018 05:19 PM, Lionel Debieve wrote:
Patches serie add support or RNG, CRYP and CRC IPs for stm32mp157c SoC
and add RNG default support for ev1 board.
Lionel Debieve (4):
ARM: dts: stm32: Add RNG support on stm32mp157c
ARM: dts: stm32: Enable RNG for stm32mp157c-ed1
Hi,
On 04/23/2018 11:48 AM, Pierre-Yves MORDRET wrote:
This patch adds STM32MP157C I2C support on STM32MP157C with configs and device
tree.
In the same way I2C4 is enabled for STM32MP157C ED1 Daughter bord.
I2C2/5 is enabled on STM32MP157C EV1 Daughter board on Evaluation board.
---
Version
hi
On 04/24/2018 09:54 AM, yannick fertre wrote:
This patch-set adds display controller & DSI controller support to
stm32mp157c SOC.
Version 1:
- Initial commit
yannick fertre (2):
ARM: dts: stm32: add ltdc support on stm32mp157c
ARM: dts: stm32: add dsi support on stm32mp157c
arch/ar
Hi Amélie,
On 04/24/2018 11:41 AM, Amelie Delaunay wrote:
This series adds support for STM32 USB PHY Controller (USBPHYC) to
stm32mp157c SoC and enables it on stm32mp157c-ev1 board.
---
Changes in v2:
* Add reset dt-bindings include
* Add fixed regulators
* Enable CONFIG_PHY_STM32_USBPHYC in mu
Hi Amélie,
On 04/24/2018 01:24 PM, Amelie Delaunay wrote:
Add support for USBH (USB Host) to STM32MP157C SoC.
USBH is a USB Host controller supporting the standard registers used for
full- and low-speed (OHCI controller) and high-speed (EHCI controller).
Signed-off-by: Amelie Delaunay
---
ar
Hi Stephen
On 05/29/2018 07:52 AM, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the irqchip tree got a conflict in:
arch/arm/boot/dts/stm32mp157c.dtsi
between commit:
3c00436fdb20 ("ARM: dts: stm32: add USBPHYC support to stm32mp157c")
from the arm-soc tree and commit:
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