.
AMD future products will implement the CPUID 0xF.[ECX=1]:EAX.
Signed-off-by: Babu Moger
---
- Sending it second time. Email client had some issues first time.
- Generated the patch on top of
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git (x86/cache).
arch/x86/kernel/cpu/resctrl
ject: Re: [PATCH] x86/resctrl: Fix memory bandwidth counter width for AMD
>
> On Mon, Jun 01, 2020 at 06:00:29PM -0500, Babu Moger wrote:
> > Memory bandwidth is calculated reading the monitoring counter
> > at two intervals and calculating the delta. It is the software’s
> >
.
AMD future products will implement the CPUID 0xF.[ECX=1]:EAX.
Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature")
Signed-off-by: Babu Moger
---
v2:
-Added Fixes tag. The problem was there from the day one when
AMD resctrl feature was added. So, added fixes tag when AMD
From: Stanislav Lanci
This patch allow to enable x86 feature TOPOEXT. This is needed to provide
information about SMT on AMD Zen CPUs to the guest.
Signed-off-by: Stanislav Lanci
Tested-by: Nick Sarnie
Reviewed-by: Paolo Bonzini
Signed-off-by: Babu Moger
---
Rebased on top of linux-next
For example, RDPRU instruction can be used to reading MPERF and APERF at
user level.
Adding this to cpu feature definition, so it is visible in /proc/cpuinfo.
Details are available in AMD64 Architecture Programmer’s Manual.
https://www.amd.com/system/files/TechDocs/24594.pdf
Signed-off-by: Babu
; Borislav Petkov ; H . Peter Anvin
> ; Thomas Gleixner
> Subject: Re: [PATCH v3 02/11] KVM: SVM: Change intercept_cr to generic
> intercepts
>
> On Tue, Jul 28, 2020 at 4:38 PM Babu Moger wrote:
> >
> > Change intercept_cr to generic intercepts in vmcb_contr
; Borislav Petkov ; H . Peter Anvin
> ; Thomas Gleixner
> Subject: Re: [PATCH v3 03/11] KVM: SVM: Change intercept_dr to generic
> intercepts
>
> On Tue, Jul 28, 2020 at 4:38 PM Babu Moger wrote:
> >
> > Modify intercept_dr to generic intercepts in vmcb_contr
; Molnar ; Borislav Petkov ; H . Peter Anvin
> ; Thomas Gleixner
> Subject: Re: [PATCH v3 04/11] KVM: SVM: Modify intercept_exceptions to
> generic intercepts
>
> On Tue, Jul 28, 2020 at 4:38 PM Babu Moger wrote:
> >
> > Modify intercept_exceptions to generic intercepts
; Molnar ; Borislav Petkov ; H . Peter Anvin
> ; Thomas Gleixner
> Subject: Re: [PATCH v3 05/11] KVM: SVM: Modify 64 bit intercept field to two
> 32
> bit vectors
>
> On Tue, Jul 28, 2020 at 4:38 PM Babu Moger wrote:
> >
> > Convert all the intercepts to one array of
; Molnar ; Borislav Petkov ; H . Peter Anvin
> ; Thomas Gleixner
> Subject: Re: [PATCH v3 06/11] KVM: SVM: Add new intercept vector in
> vmcb_control_area
>
> On Tue, Jul 28, 2020 at 4:38 PM Babu Moger wrote:
> >
> > The new intercept bits have been added in vmcb control area
ch/x86
> maintainers ; LKML ; Ingo
> Molnar ; Borislav Petkov ; H . Peter Anvin
> ; Thomas Gleixner
> Subject: Re: [PATCH v3 11/11] KVM:SVM: Enable INVPCID feature on AMD
>
> On Tue, Jul 28, 2020 at 4:39 PM Babu Moger wrote:
> >
> > The following intercept bit has
k...@vger.kernel.org; j...@8bytes.org; x...@kernel.org; linux-
> ker...@vger.kernel.org; mi...@redhat.com; b...@alien8.de; h...@zytor.com;
> t...@linutronix.de
> Subject: Re: [PATCH v3 01/11] KVM: SVM: Introduce __set_intercept,
> __clr_intercept and __is_intercept
>
> On 29/07/20 01:37, Ba
> -Original Message-
> From: Paolo Bonzini
> Sent: Wednesday, July 29, 2020 6:12 PM
> To: Jim Mattson ; Moger, Babu
>
> Cc: Vitaly Kuznetsov ; Wanpeng Li
> ; Sean Christopherson
> ; kvm list ; Joerg
> Roedel ; the arch/x86 maintainers ; LKML
> ; Ingo Molnar ; Borislav
> Petkov ; H .
> -Original Message-
> From: kvm-ow...@vger.kernel.org On Behalf
> Of Babu Moger
> Sent: Thursday, July 30, 2020 11:38 AM
> To: Paolo Bonzini ; Jim Mattson
>
> Cc: Vitaly Kuznetsov ; Wanpeng Li
> ; Sean Christopherson
> ; kvm list ; Joerg
> Roedel ; t
This is in preparation for the future intercept vector additions.
Add new functions __set_intercept, __clr_intercept and __is_intercept
using kernel APIs __set_bit, __clear_bit and test_bit espectively.
Signed-off-by: Babu Moger
---
arch/x86/kvm/svm/svm.h | 15 +++
1 file changed
Change intercept_cr to generic intercepts in vmcb_control_area.
Use the new __set_intercept, __clr_intercept and __is_intercept
where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h | 42 --
arch/x86/kvm/svm/nested.c | 26
2237488867.stgit@bmoger-ubuntu/
Babu Moger (11):
KVM: SVM: Introduce __set_intercept, __clr_intercept and __is_intercept
KVM: SVM: Change intercept_cr to generic intercepts
KVM: SVM: Change intercept_dr to generic intercepts
KVM: SVM: Modify intercept_exceptions to generic
INVPCID instruction handling is mostly same across both VMX and
SVM. So, move the code to common x86.c.
Signed-off-by: Babu Moger
---
arch/x86/kvm/vmx/vmx.c | 62 +--
arch/x86/kvm/x86.c | 69
arch
Modify intercept_exceptions to generic intercepts in vmcb_control_area.
Use the generic __set_intercept, __clr_intercept and __is_intercept to
set the intercept_exceptions bits.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h | 22 +-
arch/x86/kvm/svm/nested.c
Remove set_exception_intercept and clr_exception_intercept.
Replace with generic set_intercept and clr_intercept for these calls.
Signed-off-by: Babu Moger
---
arch/x86/kvm/svm/svm.c | 20 ++--
arch/x86/kvm/svm/svm.h | 18 --
2 files changed, 10 insertions
Modify intercept_dr to generic intercepts in vmcb_control_area.
Use generic __set_intercept, __clr_intercept and __is_intercept
to set/clear/test the intercept_dr bits.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h | 36 ++--
arch/x86/kvm/svm
com/system/files/TechDocs/24593.pdf
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/include/uapi/asm/svm.h |2 +
arch/x86/kvm/svm/svm.c | 64 +++
2 files changed, 66 insertions(+)
diff --git a/arch/x
Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept. Instead
call generic set_intercept, clr_intercept and is_intercept for all
cr intercepts.
Signed-off-by: Babu Moger
---
arch/x86/kvm/svm/svm.c | 34 +-
arch/x86/kvm/svm/svm.h | 25
the links below:
Link: https://www.amd.com/system/files/TechDocs/24593.pdf
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h |7 +++
arch/x86/kvm/svm/nested.c |3 ++-
arch/x86/kvm/trace.h | 13
host_intercept_exceptions is not used anywhere. Clean it up.
Signed-off-by: Babu Moger
---
arch/x86/kvm/svm/nested.c |2 --
arch/x86/kvm/svm/svm.h|1 -
2 files changed, 3 deletions(-)
diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c
index b0e47f474bb6
Convert all the intercepts to one array of 32 bit vectors in
vmcb_control_area. This makes it easy for future intercept vector
additions. Also update trace functions.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h | 14 +++---
arch/x86/kvm/svm/nested.c | 25
> -Original Message-
> From: Reinette Chatre
> Sent: Wednesday, May 6, 2020 6:50 PM
> To: t...@linutronix.de; fenghua...@intel.com; b...@alien8.de;
> tony.l...@intel.com
> Cc: kuo-lang.ts...@intel.com; ravi.v.shan...@intel.com; mi...@redhat.com;
> Moger, Babu ; h...@zytor.com;
> -Original Message-
> From: Reinette Chatre
> Sent: Wednesday, May 6, 2020 6:50 PM
> To: t...@linutronix.de; fenghua...@intel.com; b...@alien8.de;
> tony.l...@intel.com
> Cc: kuo-lang.ts...@intel.com; ravi.v.shan...@intel.com; mi...@redhat.com;
> Moger, Babu ; h...@zytor.com;
> -Original Message-
> From: Reinette Chatre
> Sent: Wednesday, May 6, 2020 6:50 PM
> To: t...@linutronix.de; fenghua...@intel.com; b...@alien8.de;
> tony.l...@intel.com
> Cc: kuo-lang.ts...@intel.com; ravi.v.shan...@intel.com; mi...@redhat.com;
> Moger, Babu ; h...@zytor.com;
gt; h...@zytor.com; x...@kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH V3 1/4] x86/resctrl: Enable user to view and select thread
> throttling mode
>
> Hi Babu,
>
> Thank you very much for taking a look.
>
> On 5/14/2020 9:45 AM, Babu Moger wrote:
> > Hi
mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; linux-kernel@vger.kernel.org; Andy
> Shevchenko
> Subject: Re: [PATCH V3 4/4] x86/resctrl: Use appropriate API for strings
> terminated by newline
>
> On Thu, May 14, 2020 at 10:08 PM Babu Moger
> wrote:
> > > ---
gt; h...@zytor.com; x...@kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH V3 2/4] x86/resctrl: Enumerate per-thread MBA
>
> Hi Babu,
>
> On 5/14/2020 12:04 PM, Babu Moger wrote:
> >
> >
> >> -Original Message-
> >> From: Rei
ject: Re: [PATCH v2 09/10] x86/resctrl: Add arch_has_sparse_bitmaps to
> explain AMD/Intel CAT difference
>
> Hi guys,
>
> On 13/05/2020 21:03, Babu Moger wrote:
> >> From: Reinette Chatre
> >> On 4/30/2020 10:03 AM, James Morse wrote:
> >>> Intel exp
save_state.
v1:
https://lore.kernel.org/lkml/158880240546.11615.2219410169137148044.st...@naples-babu.amd.com/
Babu Moger (3):
arch/x86: Rename config X86_INTEL_MEMORY_PROTECTION_KEYS to generic x86
KVM: x86: Move pkru save/restore to x86.c
KVM: SVM: Add support for MPK feat
AMD's next generation of EPYC processors support the MPK (Memory
Protection Keys) feature.
So, rename X86_INTEL_MEMORY_PROTECTION_KEYS to X86_MEMORY_PROTECTION_KEYS.
No functional changes.
Signed-off-by: Babu Moger
---
Documentation/core-api/protection-keys.rst |3 ++-
arch/x86
PKU feature is supported by both VMX and SVM. So we can
safely move pkru state save/restore to common code.
Also move all the pkru data structure to kvm_vcpu_arch.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/kvm_host.h |1 +
arch/x86/kvm/vmx/vmx.c | 18
tation can be
obtained at the link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/kvm/svm/svm.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 2f379bacbb26..37fb41ad9149 100644
--- a/ar
On 5/8/20 4:55 PM, Sean Christopherson wrote:
> On Fri, May 08, 2020 at 04:10:03PM -0500, Babu Moger wrote:
>> The Memory Protection Key (MPK) feature provides a way for applications
>> to impose page-based data access protections (read/write, read-only or
>> no acces
On 5/9/20 7:59 AM, Paolo Bonzini wrote:
> On 09/05/20 00:09, Jim Mattson wrote:
>>> + if (static_cpu_has(X86_FEATURE_PKU) &&
>>> + kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
>>> + vcpu->arch.pkru != vcpu->arch.host_pkru)
>>> + __write_pkru(vcpu->arch.pkru);
On 5/13/20 10:09 AM, Dave Hansen wrote:
> On 5/12/20 4:58 PM, Babu Moger wrote:
>> +config X86_MEMORY_PROTECTION_KEYS
>> +# Both Intel and AMD platforms support "Memory Protection Keys"
>> +# feature. So add a generic option X86_MEMORY_PROTECTION_KE
On 5/13/20 10:35 AM, Paolo Bonzini wrote:
> On 13/05/20 01:58, Babu Moger wrote:
>> AMD's next generation of EPYC processors support the MPK (Memory
>> Protection Keys) feature.
>>
>> This series enables the feature on AMD and updates config parameters
>> and
Hi James,
Patches all look good. Tested on AMD platform and working as expected.
Reviewed-by: Babu Moger
Thanks
> -Original Message-
> From: James Morse
> Sent: Thursday, April 30, 2020 12:04 PM
> To: x...@kernel.org; linux-kernel@vger.kernel.org
> Cc: Fenghua Yu ;
ecutive' test in cbm_validate().
> >
> > Merging the validate calls causes AMD top gain the min_cbm_bits test
> > needed for Haswell, but as it always sets this value to 1, it will
> > never match.
> >
> > CC: Babu Moger
> > Signed-off-by: James Morse
&
e on other architectures, check the id attribute
> has actually been set.
>
> Signed-off-by: James Morse
Reviewed-by: Babu Moger
> ---
> arch/x86/kernel/cpu/resctrl/core.c | 17 ++---
> include/linux/cacheinfo.h | 21 +
> 2 files change
AMD's next generation of EPYC processors support the MPK (Memory
Protection Keys) feature.
Add a generic X86_MEMORY_PROTECTION_KEYS config shadowing
X86_INTEL_MEMORY_PROTECTION_KEYS and update the kernel
documentation.
No functional changes.
Signed-off-by: Babu Moger
---
v5:
- Just submiting
Hi Reinnette,
The patches did not apply on my tree. I got the latest tree today. You
might want to check again.
Hunk #1 FAILED at 29.
1 out of 7 hunks FAILED -- saving rejects to file
arch/x86/kernel/cpu/resctrl/rdtgroup.c.rej
> -Original Message-
> From: Reinette Chatre
> Sent:
) Bit".
The documentation can be obtained at the link below:
https://bugzilla.kernel.org/show_bug.cgi?id=206537
This series enables the feature on AMD and updates config parameters
to reflect the MPK support on generic x86 platforms.
---
Babu Moger (2):
arch/x86: Rename config X86_INTEL_MEMORY_PROTE
AMD's next generation of EPYC processors support the MPK (Memory
Protection Keys) feature.
So, rename X86_INTEL_MEMORY_PROTECTION_KEYS to X86_MEMORY_PROTECTION_KEYS.
No functional changes.
Signed-off-by: Babu Moger
---
Documentation/core-api/protection-keys.rst |3 ++-
arch/x86
AMD64 Architecture
Programmer’s Manual Volume 2: System Programming, Pub. 24593 Rev. 3.34,
Section 5.6.6 Memory Protection Keys (MPK) Bit". Documentation can be
obtained at the link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/kvm/svm/sv
save_state/kvm_load_guest_xsave_state.
v1:
https://lore.kernel.org/lkml/158880240546.11615.2219410169137148044.st...@naples-babu.amd.com/
Babu Moger (3):
arch/x86: Rename config X86_INTEL_MEMORY_PROTECTION_KEYS to generic x86
KVM: x86: Move pkru save/restore to x86.c
KVM: x86: Move MPK feature
value"
Signed-off-by: Babu Moger
---
arch/x86/include/asm/kvm_host.h |1 +
arch/x86/kvm/vmx/vmx.c | 18 --
arch/x86/kvm/x86.c | 17 +
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h
ystem Programming, Pub. 24593 Rev. 3.34,
Section 5.6.6 Memory Protection Keys (MPK) Bit". Documentation can be
obtained at the link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
Documentation/core-api/protection-keys.rst |3 ++-
arch/x
Both Intel and AMD support (MPK) Memory Protection Key feature.
Move the feature detection from VMX to the common code. It should
work for both the platforms now.
Signed-off-by: Babu Moger
---
arch/x86/kvm/cpuid.c |4 +++-
arch/x86/kvm/vmx/vmx.c |4
2 files changed, 3 insertions
On 5/11/20 6:44 PM, Dave Hansen wrote:
> On 5/11/20 4:32 PM, Babu Moger wrote:
>> AMD's next generation of EPYC processors support the MPK (Memory
>> Protection Keys) feature.
>>
>> So, rename X86_INTEL_MEMORY_PROTECTION_KEYS to X86_MEMORY_PROTECTION_KEYS.
>>
&g
On 5/11/20 6:51 PM, Jim Mattson wrote:
> On Mon, May 11, 2020 at 4:33 PM Babu Moger wrote:
>>
>> Both Intel and AMD support (MPK) Memory Protection Key feature.
>> Move the feature detection from VMX to the common code. It should
>> work for both the platforms now
On 5/12/20 10:19 AM, Dave Hansen wrote:
> On 5/12/20 7:57 AM, Babu Moger wrote:
>>> I was hoping to see at least *some* justification in this changelog. Do
>>> you think having "INTEL_" will confuse users? Is there some technical
>>> merit
On 5/12/20 11:39 AM, Jim Mattson wrote:
> On Mon, May 11, 2020 at 4:33 PM Babu Moger wrote:
>>
>> MPK feature is supported by both VMX and SVM. So we can
>> safely move pkru state save/restore to common code. Also
>> move all the pkru data structure to kvm_
On 5/12/20 12:28 PM, Sean Christopherson wrote:
> On Tue, May 12, 2020 at 09:58:19AM -0700, Jim Mattson wrote:
>> On Tue, May 12, 2020 at 8:12 AM Babu Moger wrote:
>>>
>>>
>>>
>>> On 5/11/20 6:51 PM, Jim Mattson wrote:
>>>> On Mon, Ma
rch. Moved save/restore pkru
to kvm_load_host_xsave_state/kvm_load_guest_xsave_state.
v1:
https://lore.kernel.org/lkml/158880240546.11615.2219410169137148044.st...@naples-babu.amd.com/
Babu Moger (3):
arch/x86: Update config and kernel doc for MPK feature on AMD
KVM: x86: Move
AMD's next generation of EPYC processors support the MPK (Memory
Protection Keys) feature.
Add a generic X86_MEMORY_PROTECTION_KEYS config shadowing
X86_INTEL_MEMORY_PROTECTION_KEYS and update the kernel
documentation.
No functional changes.
Signed-off-by: Babu Moger
---
Documentation/core
Both Intel and AMD support (MPK) Memory Protection Key feature.
Move the feature detection from VMX to the common code. It should
work for both the platforms now.
Signed-off-by: Babu Moger
---
arch/x86/kvm/cpuid.c |9 -
arch/x86/kvm/vmx/vmx.c |4
2 files changed, 8
value"
Signed-off-by: Babu Moger
---
arch/x86/include/asm/kvm_host.h |1 +
arch/x86/kvm/vmx/vmx.c | 18 --
arch/x86/kvm/x86.c | 17 +
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/x86/include/asm/kvm_host.h
On 5/7/20 10:16 AM, Paolo Bonzini wrote:
> On 07/05/20 16:44, Dave Hansen wrote:
>>> You could add a new option (X86_MEMORY_PROTECTION_KEYS) which is
>>> def_bool X86_INTEL_MEMORY_PROTECTION_KEYS and avoiding the prompt line.
>>> Soo it is selected based on the old option and the user isn't
On 5/7/20 11:07 AM, Paolo Bonzini wrote:
> On 07/05/20 18:06, Babu Moger wrote:
>>>> So, for now my preference would be to change the prompt, but leave the
>>>> CONFIG_ naming in place.
>>> I agree.
>>>
>>> What's in a name? An Intel rose b
cation like Intel does.
> So, to avoid any confusion the thread throttling mode would be UNDEFINED
> on AMD systems and the "thread_throttle_mode" file will not be visible.
>
> Cc: Babu Moger
> Signed-off-by: Reinette Chatre
> ---
> Changes since V3:
> - Maintain th
elay value to each hardware thread instead of to
> a core. Per-thread MBA is enumerated by CPUID.
>
> No feature flag is shown in /proc/cpuinfo. User applications need to
> check a resctrl throttling mode info file to know if the feature is
> supported.
>
> Signed-off-by: Fenghua
t; bandwidth is allocated per thread and help them fine tune MBA on thread
> level.
>
> Signed-off-by: Fenghua Yu
> [reinette: transition patch to use membw_throttle_mode enum]
> Signed-off-by: Reinette Chatre
Reviewed-by: Babu Moger
> ---
> Changes since V3:
> - Us
the issue setting the default width to 44 bits by adjusting the
offset.
AMD future products will implement CPUID 0xF.[ECX=1]:EAX.
[ bp: Let the line stick out and drop {}-brackets around a single
statement. ]
Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature")
Signed-off-by:
Vitaly Kuznetsov ;
> Thomas Gleixner ; LKML ;
> kvm list
> Subject: Re: [PATCH v2 2/3] KVM:SVM: Add extended intercept support
>
> On Wed, Jun 17, 2020 at 11:11 AM Babu Moger
> wrote:
> >
> > Jim,
> >
> > > -Original Message-
> >
INVPCID instruction handling is mostly same across both VMX and
SVM. So, move the code to common x86.c.
Signed-off-by: Babu Moger
---
arch/x86/kvm/vmx/vmx.c | 78 +-
arch/x86/kvm/x86.c | 89
arch
e obtained at the links below:
Link: https://www.amd.com/system/files/TechDocs/24593.pdf
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h |3 ++-
arch/x86/kvm/svm/nested.c |6 +-
arch/x86/kvm/svm/svm.c |1 +
ar
cture Programmer’s Manual Volume 2: System Programming,
Pub. 24593 Rev. 3.34(or later)"
The documentation can be obtained at the links below:
Link: https://www.amd.com/system/files/TechDocs/24593.pdf
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/i
ink: https://bugzilla.kernel.org/show_bug.cgi?id=206537
---
babu Moger (3):
KVM: X86: Move handling of INVPCID types to x86
KVM:SVM: Add extended intercept support
KVM:SVM: Enable INVPCID feature on AMD
arch/x86/include/asm/svm.h |7 +++
arch/x86/include/uapi/asm/svm.h |2 +
arch/x
Vitaly Kuznetsov ;
> Thomas Gleixner ; LKML ;
> kvm list
> Subject: Re: [PATCH 3/3] KVM:SVM: Enable INVPCID feature on AMD
>
> On Thu, Jun 11, 2020 at 2:48 PM Babu Moger wrote:
> >
> > The following intercept is added for INVPCID instruction:
> > CodeName
On 6/12/20 1:02 PM, Jim Mattson wrote:
> On Thu, Jun 11, 2020 at 2:48 PM Babu Moger wrote:
>>
>> INVPCID instruction handling is mostly same across both VMX and
>> SVM. So, move the code to common x86.c.
>>
>> Signed-off-by: Babu Moger
>>
On 6/12/20 3:10 PM, Jim Mattson wrote:
> On Fri, Jun 12, 2020 at 12:35 PM Babu Moger wrote:
>>
>>
>>
>>> -Original Message-
>>> From: Jim Mattson
>>> Sent: Thursday, June 11, 2020 6:51 PM
>>> To: Moger, Babu
>>> C
On 6/2/20 12:13 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 6/1/2020 4:00 PM, Babu Moger wrote:
>> Memory bandwidth is calculated reading the monitoring counter
>> at two intervals and calculating the delta. It is the software’s
>> responsibility to read the count o
TCH] x86/resctrl: Fix memory bandwidth counter width for AMD
>
> Hi Babu,
>
> On 6/1/2020 4:00 PM, Babu Moger wrote:
> > Memory bandwidth is calculated reading the monitoring counter
> > at two intervals and calculating the delta. It is the software’s
> > responsibi
ject: Re: [PATCH] x86/resctrl: Fix memory bandwidth counter width for AMD
>
> Hi Babu,
>
> On 6/2/2020 3:12 PM, Babu Moger wrote:
> >
> >
> >> -Original Message-
> >> From: Reinette Chatre
> >> Sent: Tuesday, June 2, 2020 4:51 PM
INVPCID instruction handling is mostly same across both VMX and
SVM. So, move the code to common x86.c.
Signed-off-by: Babu Moger
---
arch/x86/kvm/vmx/vmx.c | 68 +
arch/x86/kvm/x86.c | 79
arch/x86
when tdp is on.
- Reverted the fault priority to original order.sed the
v1:
https://lore.kernel.org/lkml/159191202523.31436.11959784252237488867.stgit@bmoger-ubuntu/
Babu Moger (3):
KVM: X86: Move handling of INVPCID types to x86
KVM:SVM: Add extended intercept support
/24593.pdf
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h |4 +++
arch/x86/include/uapi/asm/svm.h |2 +
arch/x86/kvm/svm/svm.c | 54 +++
3 files changed, 60 insertions(+)
e obtained at the links below:
Link: https://www.amd.com/system/files/TechDocs/24593.pdf
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
arch/x86/include/asm/svm.h |3 ++-
arch/x86/kvm/svm/nested.c |6 +-
arch/x86/kvm/svm/svm.c |1 +
ar
Vitaly Kuznetsov ;
> Thomas Gleixner ; LKML ;
> kvm list
> Subject: Re: [PATCH v2 2/3] KVM:SVM: Add extended intercept support
>
> On Tue, Jun 16, 2020 at 3:03 PM Babu Moger wrote:
> >
> > The new intercept bits have been added in vmcb control
> > area to support th
; mi...@redhat.com; b...@alien8.de;
> h...@zytor.com; pbonz...@redhat.com; t...@linutronix.de;
> jmatt...@google.com
> Subject: Re: [PATCH v2 1/3] KVM: X86: Move handling of INVPCID types to x86
>
> Babu Moger writes:
>
> > INVPCID instruction handling is mostly same across both
; mi...@redhat.com; b...@alien8.de;
> h...@zytor.com; pbonz...@redhat.com; t...@linutronix.de;
> jmatt...@google.com
> Subject: Re: [PATCH v2 2/3] KVM:SVM: Add extended intercept support
>
> Babu Moger writes:
>
> > The new intercept bits have been added in vmcb control
&g
Jim,
> -Original Message-
> From: kvm-ow...@vger.kernel.org On Behalf
> Of Babu Moger
> Sent: Wednesday, June 17, 2020 9:31 AM
> To: Jim Mattson
> Cc: Wanpeng Li ; Joerg Roedel ;
> the arch/x86 maintainers ; Sean Christopherson
> ; Ingo Molnar ;
> Borisl
Vitaly Kuznetsov ;
> Thomas Gleixner ; LKML ;
> kvm list
> Subject: Re: [PATCH 3/3] KVM:SVM: Enable INVPCID feature on AMD
>
> On Fri, Jun 12, 2020 at 2:47 PM Babu Moger wrote:
> >
> >
> >
> > On 6/12/20 3:10 PM, Jim Mattson
> -Original Message-
> From: Paolo Bonzini
> Sent: Monday, June 15, 2020 8:47 AM
> To: Jim Mattson ; Moger, Babu
>
> Cc: Wanpeng Li ; Joerg Roedel ;
> the arch/x86 maintainers ; Sean Christopherson
> ; Ingo Molnar ;
> Borislav Petkov ; H . Peter Anvin ; Vitaly
> Kuznetsov ; Thomas
tic
allocations"). Added new CONFIG_PROVE_LOCKING_PLUS in case someone
needs more entries to debug their large configuration.
Patch 1 : Adjusts the sizes based on the new config parameter
patch 2 : Adds new config parameter
Babu Moger (2):
lockdep: Keep the default static allocations sma
needs to enable more static space for lockdep entries,
lock chains and stack traces to debug large configurations.
Signed-off-by: Babu Moger
---
kernel/locking/lockdep_internals.h | 14 +++---
1 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/kernel/locking/lockdep_internals
Adding the new config parameter CONFIG_PROVE_LOCKING_PLUS in case
someone needs to enable more static space for lockdep entries,
lock chains and stack traces to debug large configurations.
The default size is kept small to cover majority of the configs.
Signed-off-by: Babu Moger
---
lib
On 9/23/2016 2:12 AM, Peter Zijlstra wrote:
On Thu, Sep 22, 2016 at 11:43:34AM -0700, Babu Moger wrote:
These patches adjust the static allocations for lockdep
data structures used for debugging locking correctness. The current
code reserves about 4MB extra space for these data structures. Most
On 9/23/2016 9:34 AM, Peter Zijlstra wrote:
On Fri, Sep 23, 2016 at 09:04:42AM -0500, Babu Moger wrote:
On 9/23/2016 2:12 AM, Peter Zijlstra wrote:
On Thu, Sep 22, 2016 at 11:43:34AM -0700, Babu Moger wrote:
These patches adjust the static allocations for lockdep
data structures used
On 9/23/2016 10:04 AM, Peter Zijlstra wrote:
On Fri, Sep 23, 2016 at 09:50:52AM -0500, Babu Moger wrote:
Why can't you boot? You have that little memories? 4MB doesn't seem like
a worthwhile amount of memory.
Also, you didn't say. This seems a somewhat crucial point.
Correct, We can't
On 9/23/2016 10:40 AM, Peter Zijlstra wrote:
On Fri, Sep 23, 2016 at 10:15:46AM -0500, Babu Moger wrote:
Correct, We can't boot with lockdep. Sorry I did not make that clear.
We have a limit on static size of the kernel.
This stuff should be in .bss not .data. It should not affect
On 9/23/2016 3:17 PM, Peter Zijlstra wrote:
On Fri, Sep 23, 2016 at 02:57:39PM -0500, Babu Moger wrote:
We checked again. Yes, It goes in .bss section. But in sparc we have
to fit .text, .data, .bss in 7 permanent TLBs(that is totally 28MB).
It was fine so far. But the commit
Dave, Gentle reminder to review this patch. Thanks
On 9/30/2016 12:19 AM, David Miller wrote:
From: Babu Moger
Date: Thu, 29 Sep 2016 08:53:24 -0500
On 9/28/2016 3:39 AM, Peter Zijlstra wrote:
On Tue, Sep 27, 2016 at 12:33:27PM -0700, Babu Moger wrote:
This new config parameter limits
in arch specific handlers.
If you think there is a better way to do this. Please advice.
Tested on sparc. Compile tested on x86.
Babu Moger (2):
watchdog: Introduce update_arch_nmi_watchdog
sparc: Implement update_arch_nmi_watchdog
arch/sparc/kernel/nmi.c | 26
watchdog_enabled variable outside
so that arch specific nmi watchdogs can use it to implement
enalbe/disable behavour.
Signed-off-by: Babu Moger
---
include/linux/nmi.h |1 +
kernel/watchdog.c | 16 +---
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/include/linux/nmi.h
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