On Fri, Jul 22, 2016 at 8:24 AM, Michael Turquette
wrote:
> Quoting Chen-Yu Tsai (2016-07-13 20:34:34)
>> On Sat, Jul 9, 2016 at 2:36 AM, Michael Turquette
>> wrote:
>> > Quoting Chen-Yu Tsai (2016-06-30 08:58:48)
>> >> +static long ac100_clkout_round_r
On Mon, Sep 12, 2016 at 6:11 PM, Andre Przywara wrote:
> Hi,
>
> On 10/09/16 03:33, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Sat, Sep 10, 2016 at 4:10 AM, Maxime Ripard
>> wrote:
>>> From: Andre Przywara
>>>
>>> The Pine64 is a cost-ef
On Mon, Sep 19, 2016 at 3:12 AM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Sep 15, 2016 at 11:13:59PM +0800, Chen-Yu Tsai wrote:
>> The 18 or 24 bit parallel RGB LCD panel interface found on Allwinner
>> SoCs matches the description of MIPI DPI. Declare the RGB encoder and
>
On Mon, Sep 19, 2016 at 3:16 AM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Sep 15, 2016 at 11:14:02PM +0800, Chen-Yu Tsai wrote:
>> With display pixel clocks we want to have the closest possible clock
>> rate, to minimize timing and refresh rate skews. Whether the actual
>&
Signed-off-by: Chen-Yu Tsai
---
Changes since v2: none
Changes since v1: none
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index
The AC100's RTC side has 3 clock outputs on external pins, which can
provide a clock signal to the SoC or other modules, such as WiFi or
GSM modules.
Support this with a custom clk driver integrated with the rtc driver.
Signed-off-by: Chen-Yu Tsai
---
Changes since v2: none
Changes sin
Signed-off-by: Chen-Yu Tsai
---
Changes since v2: none
Changes since v1: none
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
The 32.768 kHz clock inside the A80 SoC is fed from an external source,
typically the AC100 RTC module.
Make the osc32k placeholder a fixed-factor clock so board dts files can
specify its source.
Signed-off-by: Chen-Yu Tsai
---
Changes since v2: none
Changes since v1: none
---
arch/arm/boot
thout raw formatting").
Signed-off-by: Chen-Yu Tsai
---
Changes since v2: none
Changes since v1: none
---
drivers/base/regmap/regmap.c | 31 ---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regm
Signed-off-by: Chen-Yu Tsai
---
Changes since v2:
- Fix interrupt line for ac100_codec in provided example.
---
Documentation/devicetree/bindings/mfd/ac100.txt | 42 +
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/ac100.txt
The AC100 is a multifunction device with an audio codec subsystem and
an RTC subsystem. These two subsystems share a common register space
and host interface.
Signed-off-by: Chen-Yu Tsai
Acked-by: Lee Jones
---
Changes since v2:
- Dropped file name
- Added copyright line.
- Changed
o this clk in the board dts files.
I'm hoping we can merge the driver bits (patches 2~5) through the
mfd tree, with acks from the rtc and clk maintainers for patches
4 and 5.
Regards
ChenYu
Chen-Yu Tsai (8):
regmap: Support bulk writes for devices without raw formatting
mfd: ac100:
X-Powers AC100 is a codec / RTC combo chip. This driver supports
the RTC sub-device.
The RTC block also has clock outputs and non-volatile storage.
Non-volatile storage wthin the RTC hardware is not supported.
Clock output support is added in the next patch.
Signed-off-by: Chen-Yu Tsai
On Mon, Jun 20, 2016 at 2:42 PM, Stefan Mavrodiev
wrote:
> A33-OLinuXino is A33 development board designed by Olimex LTD.
>
> It has AXP233 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
> headphone and mic jacks, connector for LiPo battery and optional
> 4GB NAND Flash.
>
> It has two 40-
Hi,
On Mon, Jun 20, 2016 at 11:44 PM, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Jun 14, 2016 at 09:19:58PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Jun 14, 2016 at 8:59 PM, Quentin Schulz
>> wrote:
>> > Hi,
>> >
>> > On 13/06/2016 15:04, Chen-Yu Tsai w
On Tue, Jun 21, 2016 at 2:35 AM, Maxime Ripard
wrote:
> On Tue, Jun 21, 2016 at 12:30:25AM +0800, Chen-Yu Tsai wrote:
>> >> >>> +®_aldo1 {
>> >> >>> + regulator-always-on;
>> >> >>> + regulator-min-microvolt
On Tue, Jun 21, 2016 at 9:14 PM, Rob Herring wrote:
> On Mon, Jun 20, 2016 at 10:52:12AM +0800, Chen-Yu Tsai wrote:
>> Signed-off-by: Chen-Yu Tsai
>> ---
>> Changes since v2:
>>
>> - Fix interrupt line for ac100_codec in provided example.
>>
>>
Hi,
On Thu, Sep 22, 2016 at 2:20 AM, Jean-Francois Moine wrote:
> Use the pointer to the main regulator device instead of the pointer
> to the child platform device.
>
> Signed-off-by: Jean-Francois Moine
> ---
> drivers/regulator/axp20x-regulator.c | 45
> ++--
On Fri, Sep 23, 2016 at 4:58 PM, Jean-Francois Moine wrote:
> This patch series adds support for the X-Powers AXP803 and AXP813 PMICs.
> It is based on the previous patch series
> regulator: axp20x: Simplify various code
>
> v3:
> - put the code of the new devices in new files instead of i
Hi,
On Thu, Jul 28, 2016 at 7:27 PM, Ondřej Jirman wrote:
> Hi Maxime,
>
> I don't have your sunxi-ng clock patches in my mailbox, so I'm replying
> to this.
>
> On 26.7.2016 08:32, Maxime Ripard wrote:
>> On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
>> If so, then yes, tryi
On Sat, Jul 30, 2016 at 1:25 AM, Maxime Ripard
wrote:
> On Thu, Jul 28, 2016 at 04:57:34PM +0200, LABBE Corentin wrote:
>> > > +static int sun8i_mdio_write(struct mii_bus *bus, int phy_addr, int
>> > > phy_reg,
>> > > + u16 data)
>> > > +{
>> > > + struct net_device *ndev = bu
Hi,
On Sun, Jul 31, 2016 at 10:39 PM, Hans de Goede wrote:
> Hi,
>
> On 31-07-16 13:25, Icenowy Zheng wrote:
>>
>> There's something unknown in the pmu part.
>>
>> Signed-off-by: Icenowy Zheng
>
>
> Cool, I really like the work you're doing on A64 support,
> keep up the good work!
>
>> ---
>> d
Hi,
On Mon, Aug 1, 2016 at 9:43 AM, André Przywara wrote:
> Hi Maxime,
>
> On 26/07/16 21:30, Maxime Ripard wrote:
>> Hi,
>>
>> Here is the previous A64 patches made by Andre [1], reworked to use
>> the new sunxi-ng clock framework.
>>
>> This uses the current H3 clock code, as both are really si
On Mon, Aug 1, 2016 at 4:30 PM, Jean-Francois Moine wrote:
> On Mon, 1 Aug 2016 02:43:06 +0100
> André Przywara wrote:
>
>> As this became quite a long read, here a TL;DR:
>> - We consider using an SCPI based clock system for the A64, alongside
>> allwinner,simple-gates and fixed clocks. We try t
On Mon, Aug 1, 2016 at 8:00 PM, Jean-Francois Moine wrote:
> On Mon, 1 Aug 2016 17:13:34 +0800
> Chen-Yu Tsai wrote:
>
>> > But I don't see why you are keeping the simple-gates. The bus gate may
>> > be ungated/gated when the clock is enabled/disabled, and that&
Hi,
On Sat, Jul 30, 2016 at 11:20 PM, maxime.rip...@free-electrons.com
wrote:
> On Sat, Jul 30, 2016 at 10:52:45PM +0800, Icenowy Zheng wrote:
>> > + if (of_device_is_compatible(pdev->dev.of_node,
>> > + "allwinner,sun6i-a31-spdif")) {
>> > + host->rst = devm_reset_control_get_optional(&pdev->dev
On Wed, Sep 7, 2016 at 2:54 AM, Maxime Ripard
wrote:
> On Tue, Sep 06, 2016 at 10:50:09AM +0800, Chen-Yu Tsai wrote:
>> >> The implementation might be along the lines of
>> >>
>> >> 1. having multiple output ports, each for a different interface type.
&
On Tue, Sep 6, 2016 at 8:18 PM, Maxime Ripard
wrote:
> Add support for the class with a single factor, N, being a multiplier.
>
> Signed-off-by: Maxime Ripard
> Acked-by: Chen-Yu Tsai
> ---
[...]
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult
the A23, hence the name of the various header files.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
On Tue, Sep 6, 2016 at 8:18 PM, Maxime Ripard
wrote:
> Add support for the clock unit found in the A23. Due to the similarities
> with the A33, it also shares its clock IDs to allow sharing the DTSI.
>
> Signed-off-by: Maxime Ripard
[...]
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
> b
On Wed, Sep 7, 2016 at 3:58 PM, wrote:
> From: Jorik Jonker
>
> Users using this UART without RTS/CTS should override the association in
> their board specific DTS. All (1) board using this UART uses RTS/CTS, so
> this breaks nothing.
I'd prefer we only do this for peripherals that have absolut
framebuffer destroy callback,
which gets called as part of the framebuffer unregister process.
Note this introduces asymmetry in how the resources are claimed and
released.
Signed-off-by: Chen-Yu Tsai
---
drivers/video/fbdev/simplefb.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
sserand
> Signed-off-by: Maxime Ripard
> ---
> arch/arm/boot/dts/Makefile| 1 +
> arch/arm/boot/dts/ntc-gr8-evb.dts | 342
> ++++++
Acked-by: Chen-Yu Tsai
> arch/arm/boot/dts/ntc-gr8.dtsi| 14 +-
> 3 files changed, 350 in
On Wed, Sep 7, 2016 at 10:53 PM, Maxime Ripard
wrote:
> From: Mylène Josserand
>
> The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
>
> Since it's not clear yet what we can factor out and merge with the A10s and
> A13 support, let's keep it out of the sun5i.dtsi include tree
ns de Goede
Cc: sta...@vger.kernel.org
Signed-off-by: Chen-Yu Tsai
---
drivers/phy/phy-sun4i-usb.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index fcf4d95ecc6d..ae4ac5457c64 100644
--- a/drivers/phy/p
The usbphy and usb_otg nodes in the A23 and A33 dts files only differ
by compatible, and for the usbphy, the size of one of its register
regions.
Move all the common bits to the A23/A33 common dtsi file.
Signed-off-by: Chen-Yu Tsai
---
Hi Maxime,
This patch applies on top of your A23/A33 CCU
Hi,
On Thu, Sep 1, 2016 at 10:16 PM, Maxime Ripard
wrote:
> This commit introduces the clocks found in the Allwinner A33 CCU.
>
> Since this SoC is very similar to the A23, and we share a significant share
> of the DTSI, the clock IDs that are going to be used will also be shared
> with the A23,
On Thu, Sep 8, 2016 at 3:37 AM, Linus Walleij wrote:
> On Wed, Sep 7, 2016 at 4:53 PM, Maxime Ripard
> wrote:
>
>> From: Mylène Josserand
>>
>> The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
>>
>> Since it's not clear yet what we can factor out and merge with the A10s and
On Thu, Sep 8, 2016 at 4:29 PM, Maxime Ripard
wrote:
> On Wed, Sep 07, 2016 at 03:24:11PM +0800, Chen-Yu Tsai wrote:
>> > + [CLK_BUS_MSGBOX]= &bus_msgbox_clk.common.hw,
>>
>> A23 manual and Allwinner sources say there is a bus gate for SPINLOCK.
On Thu, Sep 8, 2016 at 4:32 PM, Chen-Yu Tsai wrote:
> On Thu, Sep 8, 2016 at 4:29 PM, Maxime Ripard
> wrote:
>> On Wed, Sep 07, 2016 at 03:24:11PM +0800, Chen-Yu Tsai wrote:
>>> > + [CLK_BUS_MSGBOX]= &bus_msgbox_clk.common.hw,
>>>
>
On Thu, Sep 8, 2016 at 6:16 PM, Hans de Goede wrote:
> Hi,
>
>
> On 08-09-16 05:14, Chen-Yu Tsai wrote:
>>
>> The musb driver calls into this phy driver to disable/enable squelch
>> detection. This function was introduced in 24fe86a617c5 ("phy: sun4i-usb:
&
the maximum one that
> can be used with the field register width.
>
> Otherwise, we'll use whatever value has been set.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
p;i2c0_pins_a>;
> + status = "okay";
> +
> + axp209: pmic@34 {
> + reg = <0x34>;
> +
> + /*
> + * The interrupt is routed through the "External Fast
> + * Interrupt Request" pin (b
the sun5i.dtsi include tree. We will
> figure out what can be shared when things settle down.
>
> Signed-off-by: Mylène Josserand
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
On Thu, Sep 8, 2016 at 5:48 PM, Maxime Ripard
wrote:
> Add support for the clock unit found in the A23. Due to the similarities
> with the A33, it also shares its clock IDs to allow sharing the DTSI.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
On Fri, Sep 9, 2016 at 4:23 AM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Sep 08, 2016 at 11:25:35AM +0800, Chen-Yu Tsai wrote:
>> The usbphy and usb_otg nodes in the A23 and A33 dts files only differ
>> by compatible, and for the usbphy, the size of one of its register
>&
ns de Goede
Cc: sta...@vger.kernel.org
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Remove the old mutex, since it is no longer used
- Use irqsave/irqrestore variant of spinlock ops
---
drivers/phy/phy-sun4i-usb.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
---
> Immutable branch between MFD and Regualtor due for the v4.9 merge window
>
> ----
> Chen-Yu Tsai (3):
> regulator: axp20x: Support AXP806 variant
> mfd: axp20x: Add bindings f
On Thu, Sep 8, 2016 at 3:41 PM, Maxime Ripard
wrote:
> On Thu, Sep 08, 2016 at 12:32:48AM +0800, Chen-Yu Tsai wrote:
>> On Wed, Sep 7, 2016 at 10:53 PM, Maxime Ripard
>> wrote:
>> > From: Mylène Josserand
>> >
>> > The GR8 is an SoC made by N
Hi Linus,
On Mon, Sep 12, 2016 at 8:40 PM, Linus Walleij wrote:
> On Thu, Sep 8, 2016 at 9:37 AM, Maxime Ripard
> wrote:
>> On Thu, Sep 08, 2016 at 12:46:14PM +0800, Chen-Yu Tsai wrote:
>
>>> Also, I think we are needlessly using pin groups, 1 pin per group.
>>>
Hi Maxime,
On Sat, Aug 27, 2016 at 3:55 PM, Chen-Yu Tsai wrote:
> The AXP806 PMIC is the secondary PMIC. It provides various supply
> voltages for the SoC and other peripherals. The PMIC's interrupt
> line is connected to NMI pin of the SoC.
>
> Signed-off-by: Chen-Yu Tsai
10 Display Engine support")
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_dotclock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index 4332da48b1b3..1b6c2253192e 100644
--- a/
changes the dot clock's behavior to make it round to the closest
clock rate. I think this would make it easier to match the LCD panel's
timings. More on the LCD timings in a later patch set.
Regards
ChenYu
Chen-Yu Tsai (4):
drm/sun4i: rgb: Declare RGB encoder and connector as MIPI DPI
, the varying dividers also influence the difference
between the requested rate and the rounded rate.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_dotclock.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
b/drivers/gpu/drm
The 18 or 24 bit parallel RGB LCD panel interface found on Allwinner
SoCs matches the description of MIPI DPI. Declare the RGB encoder and
connector as MIPI DPI.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On Thu, Sep 15, 2016 at 10:39 PM, Danny Milosavljevic
wrote:
> This patch renames some sun7i-only registers to reflect that fact.
The subject line is way longer than it should be. Perhaps you could use
the above message as the description part of the subject?
ChenYu
>
> Signed-off-by: Danny Mil
On Thu, Sep 15, 2016 at 10:39 PM, Danny Milosavljevic
wrote:
> ASoC: sun4i-codec: Add custom regmap configs for the A10 and A20 variants.
The commit message should be a straight forward description about what
the patch does and why you did it, not a direct copy of the subject.
Something along th
The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.
Make the end condition of the for loop inclusive of 127 in the
round_rate callback.
Signed-off-by: Chen-Yu Tsai
On Thu, Sep 15, 2016 at 10:39 PM, Danny Milosavljevic
wrote:
> ASoC: sun4i-codec: rename "sun4i_codec_widgets" to "sun4i_codec_controls" for
> consistency with the struct field name.
Subject is way too long. The commit messages should be straight
forward sentences,
not in the format of patch subj
On Tue, Aug 30, 2016 at 1:44 PM, Danny Milosavljevic
wrote:
> This distinguishes sun4i from sun7i. It is necessary because they use
> different registers for the audio mixer.
> ---
> sound/soc/sunxi/sun4i-codec.c | 44
> +--
> 1 file changed, 34 insertions
Hi,
On Tue, Aug 30, 2016 at 1:44 PM, Danny Milosavljevic
wrote:
> Note: Mic1 Capture Volume is in a different register on A20 than on A10.
> Note: Mic2 Capture Volume is in a different register on A20 than on A10.
The subject would be better saying "Add support for Line-In, FM-In, Mic 2
and Capt
On Wed, Aug 31, 2016 at 3:40 PM, Danny Milosavljevic
wrote:
>> And what about microphone bias?
>
> Would this be OK?
>
> static int sun4i_codec_handle_mic_bias_event(struct snd_soc_dapm_widget *w,
> struct snd_kcontrol *k, int
> event)
> {
> st
On Wed, Aug 31, 2016 at 3:17 PM, Danny Milosavljevic
wrote:
> Hi Chen-Yu,
>
>> > +static const char * const sun4i_codec_difflinein_capture_source[] = {
>> > + "Non-Differential",
>> > + "Differential",
>>
>> How about "Stereo"? And possibly "Mono Differential"? or just "Mono".
>
>> A d
On Wed, Aug 31, 2016 at 3:49 PM, Danny Milosavljevic
wrote:
> Hi Chen-Yu,
>
>> My apologies. I didn't notice that VMIC was already in the driver.
>> In that your original patch did everything right.
>
> Don't worry about it :)
>
> But I have a question:
>
> If I replace DAPM_INPUT by DAPM_MIC it w
t; index 20bb1d00098c..c6a9e6fda1d0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -982,6 +982,7 @@ M: Chen-Yu Tsai
> L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> N: sun[x456789]i
> +F: arch/arm/boot/dts/gr8*
On Wed, Aug 31, 2016 at 4:25 PM, Milo Kim wrote:
> H3 PA5 pin is assigned for single PWM channel.
>
> Cc: Rob Herring
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
&
On Wed, Aug 31, 2016 at 4:25 PM, Milo Kim wrote:
> H3 has single PWM channel. The second PWM channel is not supported,
> so the pinctrl function should be removed.
>
> Cc: Linus Walleij
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Icenowy Zheng
> Cc: Jens Kuske
>
On Wed, Aug 31, 2016 at 4:25 PM, Milo Kim wrote:
> Cc: Rob Herring
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: devicet...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Milo Kim
Acked-by: Chen-Yu Tsai
On Wed, Aug 31, 2016 at 4:25 PM, Milo Kim wrote:
> H3 PWM controller has same register layout as sun4i driver, so it works
> by adding H3 specific data.
>
> Cc: Thierry Reding
> Cc: Rob Herring
> Cc: Maxime Ripard
> Cc: Alexandre Belloni
> Cc: Chen-Yu Tsai
> Cc
Hi Maxime,
On Tue, Aug 30, 2016 at 11:51 PM, Chen-Yu Tsai wrote:
> On Tue, Aug 30, 2016 at 8:56 PM, Maxime Ripard
> wrote:
>> Hi,
>>
>> On Tue, Aug 30, 2016 at 08:22:23PM +0800, Chen-Yu Tsai wrote:
>>> The KMS helpers (drm_atomic_helper_check_modeset/mod
are listed in the manual, and the interrupts, clocks, resets, pins
all exist, that is good enough for me.
>
> Signed-off-by: Jorik Jonker
Acked-by: Chen-Yu Tsai
On Thu, Sep 1, 2016 at 3:30 AM, wrote:
> From: Jorik Jonker
>
> This adds proper pinmux definitions for i2c0 and i2c1. Although H3 has a third
> i2c controller, these are not exposed on my boards. If someone actually has a
> H3 board with an exposed i2c2, they could add the third.
>
> Signed-off
other drm_bridge functions also follow this pattern of checking
for a non-NULL pointer, we can drop the ifs around the calls and just
pass the pointer directly.
Fixes: 894f5a9f4b4a ("drm/sun4i: Add bridge support")
Signed-off-by: Chen-Yu Tsai
---
Changes since v2:
- Add comments stating encode
On Thu, Sep 1, 2016 at 2:31 PM, Jorik Jonker wrote:
> Hi,
>
> A bit tricky to reply to two mails in one, as I think my reply relates to
> both, but here it goes.
>
> On 1 September 2016 at 04:42, Chen-Yu Tsai wrote:
>>
>> On Thu, Sep 1, 2016 at 3:30 AM,
On Thu, Sep 1, 2016 at 6:56 PM, Danny Milosavljevic
wrote:
> Hi Chen-Yu,
>
>> I have a few patches that introduce SOC_DAPM_DOUBLE, so you can share a
>> control between left/right channels. IMHO it makes the userspace mixer
>> less confusing.
>
> I definitely agree that cutting down on the number
tcon0_rgb666_pins_a: tcon0_rgb666@0 {
This is the only possible combination. You can drop the _a and @0.
Also this can be shared with A23, as they are pin compatible, and I
also matched the datasheets.
Otherwise
Acked-by: Chen-Yu Tsai
> + al
On Thu, Sep 1, 2016 at 11:31 PM, Maxime Ripard
wrote:
> Some Allwinner SoCs, such as the A33, have a variation of the TCON that
> doesn't have a second channel (or it is not wired to anything).
>
> Make sure we can handle that case.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
Hi,
On Thu, Sep 1, 2016 at 11:31 PM, Maxime Ripard
wrote:
> The A33 has a significantly different pipeline, with components that differ
> too.
>
> Make sure we had compatible for them.
>
> Signed-off-by: Maxime Ripard
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 7 +++
Hi,
On Thu, Sep 1, 2016 at 11:32 PM, Maxime Ripard
wrote:
> Add all the needed blocks to the A33 DTSI.
>
> Signed-off-by: Maxime Ripard
> ---
> arch/arm/boot/dts/sun8i-a33.dtsi | 184
> +++
> 1 file changed, 184 insertions(+)
>
> diff --git a/arch/arm/boot/d
Hi,
On Thu, Sep 1, 2016 at 11:32 PM, Maxime Ripard
wrote:
> The A33 pipeline also has some new components called SAT and DRC. Even
> though their exact features and programming model is not known (or
> documented), they need to be clocked for the pipeline to carry the video
> signal all the way.
On Thu, Sep 1, 2016 at 11:32 PM, Maxime Ripard
wrote:
> The SinA33 has an unidentified panel. Add the timings for it under a new
> compatible.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/panel/panel-simple.c | 26 ++
> 1 file changed, 26 insertions(+)
>
> dif
On Thu, Sep 1, 2016 at 10:16 PM, Maxime Ripard
wrote:
> Add some macros to ease the declaration of clocks that are using them.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
> ---
> drivers/clk/sunxi-ng/ccu_div.h | 28 +---
> 1 file chan
On Thu, Sep 1, 2016 at 10:16 PM, Maxime Ripard
wrote:
> Add a new macro to declare muxes based on a table and a gate.
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
On Thu, Aug 25, 2016 at 7:58 AM, Icenowy Zheng wrote:
>
>
> 25.08.2016, 03:36, "Maxime Ripard" :
>> Hi,
>>
>> On Tue, Aug 23, 2016 at 02:44:51PM +0800, Icenowy Zheng wrote:
>>> UART1 is connected to the bluetooth part of RTL8723BS WiFi/BT combo card
>>> on iNet D978 Rev2 board.
>>>
>>> Enable t
gt; Although the vendor U-Boot lets you boot the kernel on one of the
>> > > Cortex-A15 cores, the kernel gpio-regulator driver currently glitches
>> > > the GPIO lines to the OZ80120 regulator such that the system crashes
>> > > during startup. This part needs f
Now that we have a different clock representation, switch to it.
Signed-off-by: Chen-Yu Tsai
---
Changes since v2: none
Changes since v1: none
---
arch/arm/boot/dts/sun6i-a31.dtsi | 424 +--
1 file changed, 97 insertions(+), 327 deletions(-)
diff --git a
Add a new style driver for the clock control unit in Allwinner A31/A31s.
A few clocks are still missing:
- MIPI PLL's HDMI mode support
- EMAC clock
Signed-off-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Changes since v2:
- Fixed _SUNXI_CCU_MUX_TABLE macro name
-
nding interrupts after we stop the timer in the probe
function to avoid this.
Cc: sta...@vger.kernel.org
Signed-off-by: Chen-Yu Tsai
---
Changes since v2:
- Add static helper function to clear interrupts as suggested by Daniel.
Changes since v1:
- Add stable kernel to Cc.
---
dr
Some clocks on the A31 have fixed pre-dividers on multiple parents.
Add support for them.
Signed-off-by: Chen-Yu Tsai
---
Changes since v2:
- Fixed up H3 changes for number of fixed pre-dividers.
Changes since v1:
- Add field for number of fixed pre-dividers.
---
drivers/clk/sunxi-ng/ccu
ck header was
missed.
Fix the macro name so NKM with mux compiles correctly.
Fixes: a36583595c17 ("clk: sunxi-ng: nkm: Add mux to support multiple
parents")
Signed-off-by: Chen-Yu Tsai
---
Changes since v2: new patch
---
drivers/clk/sunxi-ng/ccu_nkm.h | 2 +-
1 f
circumvent this, we temporarily switch the CPU mux clock to another
stable clock before the rate change, and switch it back after the PLL
stabilizes. This is done with clk notifiers registered on the PLL.
This patch adds common functions for notifiers to reparent mux clocks.
Signed-off-by: Chen-Yu Tsa
Some clock muxes have holes, i.e. invalid or unconnected inputs,
between parent mux values.
Add support for specifying a mux table to map clock parents to
mux values.
Signed-off-by: Chen-Yu Tsai
---
Changes since v2:
- Update macro names as changed in commit ad4578dc4cfa ("clk: sun
e main oscillator when
the PLL-CPU clock rate is changed, to avoid any instabilities in the PLL
which result in the CPU crashing. This is similar to what the meson
platform does.
Regards
ChenYu
Chen-Yu Tsai (6):
clk: sunxi-ng: nkm: Correct mux clock macro name
clk: sunxi-ng: mux: Add sup
On Fri, Aug 26, 2016 at 2:53 PM, Danny Milosavljevic
wrote:
>
> This distinguishes sun4i from sun7i. It is necessary because they use
> different registers for the audio mixer.
> ---
> sound/soc/sunxi/sun4i-codec.c | 44
> +--
> 1 file changed, 34 insertio
On Wed, Aug 16, 2017 at 1:37 PM, Viresh Kumar wrote:
> The initial idea of creating the cpufreq-dt-platdev.c file was to keep a
> list of platforms that use the "operating-points" (V1) bindings and
> create cpufreq device for them only, as we weren't sure which platforms
> would want the device to
.compatible = "allwinner,sun7i-a20", },
> { .compatible = "allwinner,sun8i-a23", },
> - { .compatible = "allwinner,sun8i-a33", },
> { .compatible = "allwinner,sun8i-a83t", },
> { .compatible = "allwinner,sun8i-h3", },
&g
are controllable (GB)
- Raspberry Pi 2 compatible GPIO header
Signed-off-by: Chen-Yu Tsai
---
Note that the file name follows the convention of most of the other
bananapi boards, that is the vendor "sinovoip" is not included in
the name. This deviates from what is already in U-b
On Thu, Aug 17, 2017 at 1:11 PM, wrote:
> 在 2017-08-17 11:40，Chen-Yu Tsai 写道：
>>
>> The BPI-M3 is an Allwinner A83T based SBC in the Bananapi/Bpi family.
>> It is roughly the same form factor as the BPI-M1+, with roughly the
>> same peripherals and connectors
On Wed, Aug 16, 2017 at 7:24 PM, Viresh Kumar wrote:
> On 16-08-17, 16:53, Chen-Yu Tsai wrote:
>> On Wed, Aug 16, 2017 at 1:37 PM, Viresh Kumar
>> wrote:
>> > Drop few ARM (32 and 64 bit) platforms from the whitelist which always
>> > use "operating-p
On Tue, Aug 15, 2017 at 8:39 PM, Chen-Yu Tsai wrote:
> On Tue, Aug 15, 2017 at 8:25 PM, Rafael J. Wysocki wrote:
>> On Tuesday, August 15, 2017 7:42:19 AM CEST Chen-Yu Tsai wrote:
>>> On Mon, Jul 24, 2017 at 7:46 PM, Rafael J. Wysocki
>>> wrote:
>>> &g
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