multiple revisions. The module does not have revision
markings. This patch elects to use just BCM4330 for the compatible
string.
Reviewed-by: Rob Herring
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a
in the pin controller node is a good choice without
having to deal with implementation issues.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts| 25 +++
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 18 +
.../boot/dts/sun8i-a
identifies itself as.
Add this to the list of default MAC addresses and leave it to the user
to configure a valid one.
Signed-off-by: Chen-Yu Tsai
---
drivers/bluetooth/btbcm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/bluetooth/btbcm.c b/drivers
will not function correctly.
Tested-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
---
drivers/bluetooth/hci_bcm.c | 41 -
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c
index 1584c95c9c34
27;}'
I followed the existing code's style. If this is undesirable, I can send
a follow-up patch fixing the entire code block.
The first 13 patches should go through the Bluetooth tree, while we, the
sunxi maintainers, will take the last 2.
Thanks
ChenYu
Chen-Yu Tsai (14):
dt-binding
From: Maxime Ripard
The BCM20702A1 chip is a single-chip Bluetooth 4.0 controller and
transceiver. It is found in the AMPAK AP6210 WiFi+BT package.
Signed-off-by: Maxime Ripard
Tested-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
---
drivers/bluetooth/btbcm.c | 6 ++
drivers/bluetooth
line low.
This is shown to be 6.5 sleep cycles, with the sleep clock at 32.768
kHz. This is around 2 ms.
Wait a full 10 ms after the regulators are enabled to account for signal
rising times.
Tested-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
---
drivers/bluetooth/hci_bcm.c | 3 +++
1 file ch
for the compatible string.
Reviewed-by: Rob Herring
Tested-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/net/broadcom-bluetooth.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt
b
"txco" and "lpo".
Tested-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/net/broadcom-bluetooth.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt
b/Doc
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> to reflect this.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c | 29 +
> 1 file changed, 9 insertion
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> Extend the functionality of the driver to include support of 20 and
> 24 bits per sample for the earlier SoCs.
>
> Newer SoCs can also handle 32bit samples.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c |
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> Also add offset to RX channel select
>
> Signed-off-by: Marcus Cooper
Commit log seems a bit lacking. You could probably explain how you
found this, either when comparing datasheet macros, or some actual
error manifested and yo
On Fri, Dec 21, 2018 at 11:21 PM wrote:
>
> From: Marcus Cooper
>
> On the newer SoCs this is set by default to transfer a 0 after
> each sample in each slot. Add the regmap field to configure this
> and set it so that it pads the sample with 0s.
>
> Signed-off-by: Marcus Cooper
The code matche
On Sat, Dec 22, 2018 at 12:48 AM Chen-Yu Tsai wrote:
>
> On Fri, Dec 21, 2018 at 11:21 PM wrote:
> >
> > From: Marcus Cooper
> >
> > Extend the functionality of the driver to include support of 20 and
> > 24 bits per sample for the earlier SoCs.
> >
&g
On Sun, Dec 23, 2018 at 6:12 AM Jonas Karlman wrote:
>
> On 2018-12-21 17:44, Chen-Yu Tsai wrote:
> > On Fri, Dec 21, 2018 at 11:21 PM wrote:
> >> From: Marcus Cooper
> >>
> >> Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
>
unxi-ng
clock driver implicitly depends on the external clock being named
"osc24M".
Add a "clock-output-names" property to restore the previous behavior.
Fixes: acfd5bbe2641 ("ARM: dts: sun6i: Change clock node names to avoid
warnings")
Signed-of
On Mon, Oct 29, 2018 at 9:10 PM Quentin Schulz
wrote:
>
> Hi Jonathan,
>
> On Sun, Oct 28, 2018 at 03:40:11PM +, Jonathan Cameron wrote:
> > On Wed, 24 Oct 2018 08:56:33 -0500
> > Rob Herring wrote:
> >
> > > On Tue, 23 Oct 2018 21:53:23 +0300, Oskari Lemmela wrote:
> > > > The AXP803 ADC is
On Fri, Oct 26, 2018 at 3:08 AM Sebastian Reichel
wrote:
>
> Hi,
>
> Patches 1, 2 & 9 look good to me and do not seem to have any
> dependencies. I plan to merge them after the merge window
> for 4.20 closes.
Patches 2, 3 & 4 aren't needed. They aren't in the correct format
for model-specific + f
On Wed, Oct 24, 2018 at 2:54 AM Oskari Lemmela wrote:
>
> The AXP803 power supplies are compatible with AXP813, but
> add specific compatibles for them.
>
> Signed-off-by: Oskari Lemmela
> ---
> .../devicetree/bindings/power/supply/axp20x_ac_power.txt | 1 +
> .../devicetree/bindings/pow
On Wed, Oct 24, 2018 at 2:54 AM Oskari Lemmela wrote:
>
> AXP813 and AXP803 PMICs can control input current and minimum voltage.
>
> Both of these values are configurable.
>
> Signed-off-by: Oskari Lemmela
> Reviewed-by: Quentin Schulz
Reviewed-by: Chen-Yu Tsai
On Wed, Oct 24, 2018 at 2:54 AM Oskari Lemmela wrote:
>
> The AXP803 GPIO is compatible with AXP813 GPIO, but add
> specific compatible for it.
>
> Signed-off-by: Oskari Lemmela
> ---
> Documentation/devicetree/bindings/gpio/gpio-axp209.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --gi
Khoruzhick
Reviewed-by: Chen-Yu Tsai
s are routed to the baseboard 3-pin battery connector.
>
> Signed-off-by: Oskari Lemmela
> Reviewed-by: Quentin Schulz
Reviewed-by: Chen-Yu Tsai
hes. Otherwise,
Reviewed-by: Chen-Yu Tsai
On Sat, Oct 13, 2018 at 4:09 PM Oskari Lemmela wrote:
>
> Add AC power supply subnode for AXP81X PMIC.
>
> Signed-off-by: Oskari Lemmela
> Reviewed-by: Quentin Schulz
Reviewed-by: Chen-Yu Tsai
On Sat, Oct 13, 2018 at 4:09 PM Oskari Lemmela wrote:
>
> The AXP803/AXP813 AC power supply can limit input current and voltage.
>
> Signed-off-by: Oskari Lemmela
> Reviewed-by: Rob Herring
> Reviewed-by: Quentin Schulz
Reviewed-by: Chen-Yu Tsai
On Sat, Oct 13, 2018 at 4:09 PM Oskari Lemmela wrote:
>
> AXP803 is compatible with AXP813. Add DT nodes ADC, GPIO,
> AC and battery power supplies.
>
> Signed-off-by: Oskari Lemmela
> Reviewed-by: Quentin Schulz
> ---
> arch/arm64/boot/dts/allwinner/axp803.dtsi | 31 +++
>
On Sat, Oct 13, 2018 at 4:09 PM Oskari Lemmela wrote:
>
> Sopine baseboard have ACIN and battery connectors.
The commit message should be more specific, like how the two connections
from the PMIC are routed. In this case ACIN is routed from the SOM to
the DC jack on the baseboard, while the batte
ts on the AXP813.
These include the GPIO, ADC, AC and battery power supplies.
> Signed-off-by: Oskari Lemmela
Otherwise,
Reviewed-by: Chen-Yu Tsai
On Sat, Oct 13, 2018 at 4:09 PM Oskari Lemmela wrote:
>
> As axp20x-ac-power-supply now supports AXP813, add a cell for it.
>
> Signed-off-by: Oskari Lemmela
> Reviewed-by: Quentin Schulz
Reviewed-by: Chen-Yu Tsai
On Sat, Oct 13, 2018 at 4:09 PM Oskari Lemmela wrote:
>
> AXP813 and AXP803 PMICs can control input current and
> minimum voltage.
>
> Both of these values are configurable.
>
> Signed-off-by: Oskari Lemmela
> Reviewed-by: Quentin Schulz
> ---
> drivers/power/supply/axp20x_ac_power.c | 92 +
On Thu, Nov 8, 2018 at 2:42 PM Vasily Khoruzhick wrote:
>
> Add nodes for i2s, digital and analog parts of audiocodec on A64
>
> Signed-off-by: Vasily Khoruzhick
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 58 +++
> 1 file changed, 58 insertions(+)
>
> diff --git a/ar
On Thu, Nov 8, 2018 at 2:42 PM Vasily Khoruzhick wrote:
>
> This commit enables I2S, digital and analog parts of audiocodec on
> Pine64 and SoPine boards.
>
> Signed-off-by: Vasily Khoruzhick
> ---
> .../boot/dts/allwinner/sun50i-a64-pine64.dts | 28 +++
> .../allwinner/sun50i-a
On Thu, Nov 8, 2018 at 2:42 PM Vasily Khoruzhick wrote:
>
> This commit enables I2S, digital and analog parts of audiocodec on
> Pinebook
>
> Signed-off-by: Vasily Khoruzhick
> ---
> .../dts/allwinner/sun50i-a64-pinebook.dts | 42 +++
> 1 file changed, 42 insertions(+)
>
> di
On Tue, Oct 9, 2018 at 2:20 AM Oskari Lemmela wrote:
>
> AXP803 is compatible with AXP813.
> Adding cells for GPIO, ADC, AC and battery power supplies.
>
> Signed-off-by: Oskari Lemmela
> ---
> drivers/mfd/axp20x.c | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> dif
On Sat, Oct 13, 2018 at 4:23 AM Maxime Ripard wrote:
>
> On Fri, Oct 12, 2018 at 04:39:14PM +0300, Aleksandr Aleksandrov wrote:
> > Hi Andreas,
> >
> > Thanks for your feedback!
> >
> > > > + *
> > > > + * Copyright (C) 2018 Aleksandr Aleksandrov
> > > >
> > > > + */
> > > > +
> > > > +/dts-v1/;
On Mon, Oct 8, 2018 at 6:20 PM Maxime Ripard wrote:
>
> On Mon, Oct 08, 2018 at 05:06:45PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Oct 8, 2018 at 4:51 PM Maxime Ripard
> > wrote:
> > >
> > > On Sun, Oct 07, 2018 at 11:39:01AM +0200, Jernej Skrabe
On Sat, Nov 3, 2018 at 6:22 PM Jonathan Cameron
wrote:
>
> On Wed, 31 Oct 2018 10:29:59 +0800
> Chen-Yu Tsai wrote:
>
> > On Mon, Oct 29, 2018 at 9:10 PM Quentin Schulz
> > wrote:
> > >
> > > Hi Jonathan,
> > >
> > > On Sun, Oct 28,
Hi Rob,
On Mon, Oct 15, 2018 at 7:24 PM Rob Herring wrote:
>
> On Thu, 27 Sep 2018 17:18:47 +0530, Jagan Teki wrote:
> > Bananapi S070WV20-CT16 is 800x480, 4-lane MIPI-DSI panel, the
> > same panel PCB comes with parallel RBG which is supported via
> > panel-simple with "bananapi,s070wv20-ct16" c
On Mon, Jul 16, 2018 at 5:13 PM, Florian Fainelli wrote:
>
>
> On 07/15/2018 03:50 PM, Olof Johansson wrote:
>> Thanks Stephen, I keep saying every time you catch these that I need
>> to run the same script. :(
>>
>> Florian, I wonder if this happened when you rebased to squash in the fix?
>
> Hum
Hi,
On Mon, Jan 29, 2024 at 12:09:50PM -0800, Luis Chamberlain wrote:
> On Thu, Dec 21, 2023 at 10:02:46AM +0100, Christophe Leroy wrote:
> > Declaring rodata_enabled and mark_rodata_ro() at all time
> > helps removing related #ifdefery in C files.
> >
> > Signed-off-by: Christophe Leroy
>
> Ve
On Mon, Sep 18, 2023 at 6:32 PM Laura Nao wrote:
>
> > Other than patch 2 and 14, I have applied this set. The remaining patches
> > will
> > have to be resent to Matthias.
>
> > Thanks,
> > Mathieu
>
> Hello,
>
> With patch 2 missing, the SCP is not probed correctly anymore on asurada
> (MT819
s running old device trees working again.
Reported-by: Laura Nao
Fixes: 1fdbf0cdde98 ("remoteproc: mediatek: Probe SCP cluster on multi-core
SCP")
Signed-off-by: Chen-Yu Tsai
---
The patch is based on next-20230918 with a whole bunch of local patches
stacked on top. None of my local pat
On Tue, Sep 19, 2023 at 9:17 AM Mathieu Poirier
wrote:
>
> On Mon, Sep 18, 2023 at 06:44:25PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Sep 18, 2023 at 6:32 PM Laura Nao wrote:
> > >
> > > > Other than patch 2 and 14, I have applied this set. The remaining
> &
On Tue, Sep 19, 2023 at 5:26 PM AngeloGioacchino Del Regno
wrote:
>
> Il 19/09/23 07:03, Chen-Yu Tsai ha scritto:
> > In the just landed multi-core SCP work, detection of single/multi core
> > SCP is done by checking the immediate child node of the SCP complex
> > devi
anged, 7 insertions(+), 11 deletions(-)
> >
>
> Tested on asurada (spherion) and jacuzzi (juniper). The issue was detected by
> KernelCI, so:
>
> Reported-by: "kernelci.org bot"
> Tested-by: Laura Nao
Reviewed-by: Chen-Yu Tsai
Tested-by: Chen-Yu Tsai
on Hayato (MT8192) and Juniper (MT8183).
Hi,
On Wed, Dec 3, 2014 at 3:57 PM, Roger wrote:
> Hi! Heiko
>
> about regulator, power gpio, reset gpio and irq gpio
> please refer to my comment inline, tks.
>
>
> On 2014/12/2 7:44, Heiko Stübner wrote:
>>
>> Hi Roger,
>>
>> the comments inline are a rough first review. I hope to get a cleare
On Wed, Dec 31, 2014 at 8:37 AM, Heinrich Schuchardt wrote:
> When booting Linux 3.19-rc2 on a Merrii Optimusboard using
> arch/arm/boot/dts/sun9i-a80-optimus.dts adn arch/arm/boot/dts/sun9i-a80.dtsi
> I get errors
> [0.061192] /cpus/cpu@0 missing clock-frequency property
> [0.061209] /cpu
On sun9i, there are 3 independent usb phys for EHCI/OHCI.
Add device nodes for them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts
9 enables sun9i USB PHY in multi_v7_defconfig.
Regards,
ChenYu
Chen-Yu Tsai (9):
clk: sunxi: Add support for sun9i a80 usb clocks and resets
ARM: dts: sun9i: Add usb clock nodes to a80 dtsi
phy: Add driver to support individual USB PHYs on sun9i
ARM: dts: sun9i: Add usb phy nodes to a80
index, so we can set different parents for
each gate.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-usb.c | 193 ++
3 files changed
The A80 has 3 EHCI/OHCI USB controllers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 70
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d7ebd9390b01
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/phy/sun9i-usb-phy.txt
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c4de9cb9a5f6..16d30bb3a872 100644
--- a/arch/arm
On sun9i we have a new PHY driver for USB.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 38840a812924..6b271645eb43 100644
--- a/arch/arm/configs
On sun9i we have a new PHY driver for USB.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index eec304487e6d..63fcc5522393 100644
--- a/arch/arm
Some SoCs have a total of 4 possible USB controllers. One such example
is the A80, which has one USB3 dual role device and 3 EHCI/OHCI pairs.
Add a common VBUS regulator for the last host controller.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 10
The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b
Hi,
2015年1月25日 下午11:05 於 "Maxime Ripard" 寫道：
>
> Hi,
>
> On Sun, Jan 25, 2015 at 08:22:02PM +0800, Chen-Yu Tsai wrote:
> > The USB controller/phy clocks and reset controls are in a separate
> > address block, unlike previous SoCs where they were in the clock
Hi,
On Sat, Jan 10, 2015 at 12:20 AM, Gregory CLEMENT
wrote:
> Hi Hans,
>
> On 09/01/2015 16:46, Hans de Goede wrote:
>> Hi,
>>
>> On 09-01-15 11:39, Gregory CLEMENT wrote:
>>> It is now possible to use a regulator property for each port of the
>>> AHCI controller.
>>>
>>> Signed-off-by: Gregory
On Thu, Dec 18, 2014 at 5:15 AM, Alexandre Belloni
wrote:
> This adds a generic PWM framework driver for the PWM controller
> found on Allwinner SoCs.
Hi,
Any news on this series?
ChenYu
> Signed-off-by: Alexandre Belloni
> Acked-by: Maxime Ripard
> ---
> drivers/pwm/Kconfig | 10 ++
>
On sun9i, there are 3 independent usb phys for EHCI/OHCI.
Add device nodes for them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts
On sun9i we have a new PHY driver for USB.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index eec304487e6d..63fcc5522393 100644
--- a/arch/arm
a VBUS regulator for usb3 to sunxi common regulators.
Patch 8 enables USB on the A80 Optimus board.
Patch 9 enables sun9i USB PHY in sunxi_defconfig.
Patch 10 enables sun9i USB PHY in multi_v7_defconfig.
Regards,
ChenYu
Chen-Yu Tsai (10):
clk: sunxi: Move USB clocks to separate file
clk
The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b
address.
Signed-off-by: Chen-Yu Tsai
---
This patch does quite a few cleanups in addition to the code movement.
I'm not sure if it's acceptable.
---
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-sunxi.c | 88 ---
drivers/clk/sunxi/clk-usb
the reset controls, and add the sun9i USB
clocks.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 ++
drivers/clk/sunxi/clk-usb.c | 43 +++
2 files changed, 45 insertions(+)
diff --git a/Documentation/devicetree
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/phy/sun9i-usb-phy.txt
Some SoCs have a total of 4 possible USB controllers. One such example
is the A80, which has one USB3 dual role device and 3 EHCI/OHCI pairs.
Add a common VBUS regulator for the last host controller.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 10
The A80 has 3 EHCI/OHCI USB controllers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 70
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d7ebd9390b01
On sun9i we have a new PHY driver for USB.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 38840a812924..6b271645eb43 100644
--- a/arch/arm/configs
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c4de9cb9a5f6..16d30bb3a872 100644
--- a/arch/arm
From: Boris BREZILLON
Rework the AXP20X_ macros and probe function to support the several chip
families, so that each family can define it's own set of regulators.
Signed-off-by: Boris BREZILLON
[w...@csie.org: Support different DC-DC work frequency ranges]
Signed-off-by: Chen-Yu
ZILLON
[w...@csie.org: Moved variant choosing to multi family support patch]
[w...@csie.org: Add dc-dc work frequency range]
[w...@csie.org: Add "switch" type output regulator DC1SW]
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Mark Brown
---
drivers/regulator/axp
Now that the axp20x-regulators driver supports different variants of the
AXP family, we can enable regulator support for AXP22X without the risk
of incorrectly configuring regulators.
Signed-off-by: Chen-Yu Tsai
Acked-by: Lee Jones
---
drivers/mfd/axp20x.c | 2 ++
1 file changed, 2 insertions
Add AXP221 to the list of supported devices.
Also replace any mention of AXP20x in the document with a
generic "PMIC".
Signed-off-by: Chen-Yu Tsai
Acked-by: Lee Jones
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
Add the list of regulators for AXP22x to the DT bindings.
This includes the names and supply names.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 25
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings
bindings
Regards
ChenYu
Boris BREZILLON (3):
mfd: axp20x: add AXP22x PMIC support
regulator: axp20x: prepare support for multiple AXP chip families
regulator: axp20x: add support for AXP22X regulators
Chen-Yu Tsai (3):
mfd: axp20x: update DT bindings with AXP22x compatibles
mfd: axp
patch]
Signed-off-by: Chen-Yu Tsai
Acked-by: Lee Jones
---
drivers/mfd/axp20x.c | 98 ++
include/linux/mfd/axp20x.h | 86
2 files changed, 184 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp
On Wed, Apr 1, 2015 at 12:12 AM, Lee Jones wrote:
> On Wed, 01 Apr 2015, Chen-Yu Tsai wrote:
>
>> From: Boris BREZILLON
>>
>> Add support for the AXP22x PMIC devices to the existing AXP20x driver.
>> This includes the AXP221 and AXP223, which are identical excep
apbs divider is the same
as the A31 or the A23. The lowest divider is different between those
2 implementations.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/mfd/sun6i-prcm.txt | 3 +-
drivers/mfd/sun6i-prcm.c | 58 ++
2 files changed
This patch adds support for the PRCM apbs clock gates found on the
Allwinner A80 SoC.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-sun6i-apb0-gates.c | 5 +
2 files changed, 6 insertions(+)
diff --git a
dated documents
- Added new cpus clock driver based on updated documents
- Added pll3 clock placeholder
- Added comments about 24M & 32k oscillators
Regards
ChenYu
Chen-Yu Tsai (5):
clk: sunxi: sun6i-apb0: Add support for sun9i A80 apbs gates
clk: sunxi: support the cpus (cpu sp
This adds the PRCM clocks and reset controls to the A80 dtsi.
The list of apbs clock gates is incomplete. Tests show that bits 0~20
are mutable. We will need documents from Allwinner to complete the
support.
Also update clock and reset phandles for r_uart.
Signed-off-by: Chen-Yu Tsai
---
arch
The main (24MHz) clock on the A80 is configurable via the PRCM address
space. The low power/speed (32kHz) clock is from an external chip, the
AC100.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm
The "cpus" clock is the clock for the embedded processor in the A80.
It is also part of the PRCM clock tree.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/Makefile| 2 +-
drivers/clk/sunxi/clk-su
Hi Mark,
On Tue, Mar 31, 2015 at 11:03 PM, Chen-Yu Tsai wrote:
> From: Boris BREZILLON
>
> Rework the AXP20X_ macros and probe function to support the several chip
> families, so that each family can define it's own set of regulators.
>
> Signed-off-by: Boris BREZ
On Thu, Apr 9, 2015 at 12:55 PM, Mark Brown wrote:
> On Thu, Apr 09, 2015 at 10:23:41AM -0700, Chen-Yu Tsai wrote:
>
>> Are you OK with Lee taking the 2 regulator patches through his tree?
>> I realize I'm asking this way too late for this merge window.
>
> Someone wo
CM_PWROFF_GATING_REG(cluster));
> if (sunxi_mc_smp_data[index].is_sun9i)
> reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
> + else
> + reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
> writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
>
On Tue, Apr 3, 2018 at 4:46 PM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 08:18:34AM +0200, Mylène Josserand wrote:
>> To prepare the support of sun8i-a83t, add a field in the smp_data
>> structure to enable the case of sun9i.
>>
>> Start to handle the differences between sun9i-a80 and sun8i-
On Tue, Apr 3, 2018 at 4:47 PM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 08:18:33AM +0200, Mylène Josserand wrote:
>> To prepare the support for sun8i-a83t, move some structures
>> at the beginning of the file.
>>
>> Signed-off-by: Mylène Josserand
>
> I'm not quite sure what would be the b
om a80 and a83t.
>
> Signed-off-by: Mylène Josserand
> Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
On Tue, Apr 3, 2018 at 2:18 PM, Mylène Josserand
wrote:
> The R_CPUCFG is a collection of registers needed for SMP bringup
> on clusters and cluster's reset.
> For the moment, documentation about this register is found in
> Allwinner's code only.
>
> Signed-off-by: Mylène Josserand
> ---
> arch/
ans "Power On Key", much like "PEK" means "Power Enable Key",
instead of "Power OK".
This patch changes the "PWROK" prefix to "POK" for these interrupts.
Signed-off-by: Chen-Yu Tsai
---
drivers/mfd/axp20x.c | 8
includ
The axp20x driver has lots of mfd_cell and resource structs.
These can all be const-ified.
Signed-off-by: Chen-Yu Tsai
---
drivers/mfd/axp20x.c | 44 ++--
include/linux/mfd/axp20x.h | 2 +-
2 files changed, 23 insertions(+), 23 deletions(-)
diff
read one-line DEFINE_RES_IRQ macros.
Patch 3 corrects the prefix for four of the AXP806 interrupt enums.
"POK" was incorrectly expanded to "PWROK".
These are all simple cleanups. No functionality is changed.
Regards
ChenYu
Chen-Yu Tsai (3):
mfd: axp20x: Const-ify struct mfd
Previously we were open coding the interrupts for the various mfd
cells. This made the code somewhat long due to pretty-formatting.
This patch convert those into one-line declarations with DEFINE_RES_IRQ,
making the code shorter and easier to read.
Signed-off-by: Chen-Yu Tsai
---
drivers/mfd
Hi Rob,
On Tue, Apr 17, 2018 at 7:17 AM, Icenowy Zheng wrote:
>
>
> 于 2018年4月17日 GMT+08:00 上午2:47:45, Rob Herring 写到:
>>On Wed, Apr 11, 2018 at 10:16:37PM +0800, Icenowy Zheng wrote:
>>> On some Allwinner SoCs the EMAC clock register needed by dwmac-sun8i
>>is
>>> in another device's memory spac
On Mon, Apr 30, 2018 at 5:47 PM, Andre Przywara wrote:
> Hi Icenowy,
>
> On 27/04/18 08:12, Icenowy Zheng wrote:
>>
>>
>> 于 2018年4月27日 GMT+08:00 上午12:46:26, Andre Przywara
>> 写到:
>>> Hi,
>>>
>>> On 26/04/18 15:07, Icenowy Zheng wrote:
The Pine H64 board have a MicroSD slot connected to MMC0
On Mon, Apr 30, 2018 at 6:44 PM, Andre Przywara wrote:
> Hi,
>
> On 30/04/18 10:51, Icenowy Zheng wrote:
>>
>>
>> 于 2018年4月30日 GMT+08:00 下午5:47:35, Andre Przywara 写到:
>>> Hi Icenowy,
>>>
>>> On 27/04/18 08:12, Icenowy Zheng wrote:
于 2018年4月27日 GMT+08:00 上午12:46:26, Andre Przywara
>
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