From: Claudiu Beznea
Add struct atmel_pwm_data to embed different per controller information. At
this stage, embed a member of type struct atmel_pwm_registers in it.
Signed-off-by: Claudiu Beznea
---
drivers/pwm/pwm-atmel.c | 64 +++--
1 file changed
From: Claudiu Beznea
Add support for SAM9X60's PWM controller.
Signed-off-by: Claudiu Beznea
---
drivers/pwm/pwm-atmel.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 44f4a1c9f60b..44a99ba60e11 100644
--- a/driver
From: Claudiu Beznea
Add bindings for SAM9X60's slow clock controller.
Signed-off-by: Claudiu Beznea
---
Hi Rob,
I didn't added your Reviewed-by tag to this version since I changed
the driver with regards to clock-cells DT binding (and I though you
may want to comment on this).
Thank you,
Cl
From: Claudiu Beznea
Hi,
This series add slow clock support for SAM9X60. Apart from previous IPs, this
one uses different offsets in control register for different functionalities.
The series adapt current driver to work for all IPs using per IP
configurations initialized at probe.
Thank you,
C
From: Claudiu Beznea
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 100
1 file changed, 67 insertions(+), 33 d
From: Claudiu Beznea
Add support for SAM9X60's slow clock.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 2a4ac548de80..2c41
From: Claudiu Beznea
The slow clock of SAMA5D4 has no bypass support thus remove it.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index e76b1d64e905..6c55a7a86f79 100644
---
From: Claudiu Beznea
SAMA5D2 SoC has a suspend mode where SoC's power is cut off. Due to this
the registers content is lost after a suspend/resume cycle. The current
suspend/resume implementation covers some of these registers. However
there are few which were not treated (e.g. SCRT2 and USRIO).
On 18.05.2019 00:13, Alexandre Belloni wrote:
> External E-Mail
>
>
> On 16/05/2019 08:10:34+, claudiu.bez...@microchip.com wrote:
@@ -69,10 +80,11 @@ static int clk_slow_osc_prepare(struct clk_hw *hw)
void __iomem *sckcr = osc->sckcr;
u32 tmp = readl(sckcr);
>>>
From: Claudiu Beznea
Add bindings for SAM9X60's slow clock controller.
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/clock/at91-clock.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/D
From: Claudiu Beznea
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 93 -
1 file changed, 61 insertions(+), 32 d
From: Claudiu Beznea
The slow clock of SAMA5D4 has no bypass support thus remove it.
Signed-off-by: Claudiu Beznea
Acked-by: Alexandre Belloni
---
drivers/clk/at91/sckc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index e76b1d64e
From: Claudiu Beznea
Hi,
This series add slow clock support for SAM9X60. Apart from previous IPs, this
one uses different offsets in control register for different functionalities.
The series adapt current driver to work for all IPs using per IP
configurations initialized at probe.
Thank you,
C
From: Claudiu Beznea
Add support for SAM9X60's slow clock.
Signed-off-by: Claudiu Beznea
Acked-by: Alexandre Belloni
---
drivers/clk/at91/sckc.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sc
On 26.06.2019 21:36, Stephen Boyd wrote:
> Quoting claudiu.bez...@microchip.com (2019-05-21 03:11:33)
>> From: Claudiu Beznea
>>
>> Add support for SAM9X60's slow clock.
>>
>> Signed-off-by: Claudiu Beznea
>> Acked-by: Alexandre Belloni
>> ---
>
> FYI, this patch is base64 encoded and causes
On 27.06.2019 18:03, Stephen Boyd wrote:
> External E-Mail
>
>
> Quoting claudiu.bez...@microchip.com (2019-06-13 08:37:06)
>> From: Claudiu Beznea
>>
>> Hi,
>>
>> This series tries to improve error path for slow clock registrations
>> by adding functions to free resources and using them on fa
On 08.01.2019 13:46, Rafael J. Wysocki wrote:
> On Tue, Jan 8, 2019 at 11:56 AM wrote:
>>
>> From: Claudiu Beznea
>>
>> Hi,
>>
>> AT91 platforms support a power saving mode where SoC's power is cut off (we
>> call
>> it backup mode). The resume is done with the help of bootloaders.
>
> But st
On 09.01.2019 00:08, Uwe Kleine-König wrote:
> On Tue, Jan 08, 2019 at 09:21:34AM +, claudiu.bez...@microchip.com wrote:
>> Hi Uwe,
>>
>> On 08.01.2019 00:10, Uwe Kleine-König wrote:
>>> Hello Claudiu,
>>>
>>> On Mon, Jan 07, 2019 at 09:30:55AM +, claudiu.bez...@microchip.com
>>> wrote:
On 06.02.2019 00:49, Thierry Reding wrote:
> On Sat, Jan 05, 2019 at 10:05:22PM +0100, Uwe Kleine-König wrote:
>> Hello,
>>
>> On Thu, Jan 03, 2019 at 01:29:44PM +, claudiu.bez...@microchip.com wrote:
>>> From: Claudiu Beznea
>>>
>>> Add basic PWM modes: normal and complementary. These mode
On 06.02.2019 10:24, Uwe Kleine-König wrote:
> Hello Thierry,
>
> On Wed, Feb 06, 2019 at 12:01:26AM +0100, Thierry Reding wrote:
>> On Mon, Jan 07, 2019 at 11:10:40PM +0100, Uwe Kleine-König wrote:
>>> On Mon, Jan 07, 2019 at 09:30:55AM +, claudiu.bez...@microchip.com
>>> wrote:
On 05
From: Claudiu Beznea
Add documentation for SAM9X60 shutdown controller.
Signed-off-by: Claudiu Beznea
---
Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
b/D
From: Claudiu Beznea
Add RTT wakeup capability.
Signed-off-by: Claudiu Beznea
Acked-by: Nicolas Ferre
---
drivers/power/reset/at91-sama5d2_shdwc.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c
b/drivers/power/reset/at91-sama5d2_s
From: Claudiu Beznea
Hi,
This series adapt SAMA5D2's shutdown controller driver to work for
SAM9X60's shutdown controller. The difference is that SAM9X60 have
option for RTT timer wakeup.
Thank you,
Claudiu Beznea
Changes in v2:
- collect Acked-by tags
- in patch 3/3 use "optional microchip,sa
From: Claudiu Beznea
Add support for SAM9X60 shutdown controller.
Signed-off-by: Claudiu Beznea
Acked-by: Nicolas Ferre
---
drivers/power/reset/at91-sama5d2_shdwc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c
b/drivers/power/reset
On 21.02.2019 22:45, Uwe Kleine-König wrote:
> On Tue, Feb 19, 2019 at 10:09:00AM +, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Add support for SAM9X60's PWM controller.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>> drivers/pwm/pwm-atmel.c | 19 +++
>>
On 21.02.2019 22:42, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Feb 19, 2019 at 10:08:57AM +, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> New SAM9X60's PWM controller use 32 bits counters thus it could generate
>> signals with higher period and duty cycles than the o
On 18.02.2019 13:01, Nicolas Ferre - M43238 wrote:
> On 14/02/2019 at 12:24, Claudiu Beznea - M18063 wrote:
>> From: Claudiu Beznea
>>
>> Add documentation for SAM9X60 shutdown controller.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>> Documentation/devicetree/bindings/arm/atmel-sysregs.txt |
From: Claudiu Beznea
Remove cfg initialization with zero and read state with
drm_crtc_state_to_atmel_hlcdc_crtc_state() so that cfg to be initialized
with state's output_mode.
Signed-off-by: Claudiu Beznea
Reviewed-by: Sam Ravnborg
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 6 ++
From: Claudiu Beznea
Add compatible for SAM9X60 HLCD controller.
Signed-off-by: Claudiu Beznea
---
drivers/mfd/atmel-hlcdc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c
index e82543bcfdc8..35a9e16f9902 100644
--- a/drivers/mfd/atmel
From: Claudiu Beznea
Add new compatible string for the HLCD controller on SAM9X60 SoC.
Signed-off-by: Claudiu Beznea
---
Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
b/Documentat
From: Claudiu Beznea
Hi,
These patches adds support for SAM9X60's LCD controller.
First patches add option to specify if controller clock source is fixed.
Second patch avoid a variable initialization in
atmel_hlcdc_crtc_mode_set_nofb().
The 3rd one adds specific bindings for SAM9X60 LCD contro
From: Claudiu Beznea
SAM9x60 LCD Controller has no option to select clock source as previous
controllers have. To be able to use the same driver even for this LCD
controller add a config option to know if controller supports this.
Signed-off-by: Claudiu Beznea
Reviewed-by: Sam Ravnborg
---
dr
From: Claudiu Beznea
Add compatible string for SAM9X60 HLCDC's PWM.
Signed-off-by: Claudiu Beznea
Acked-by: Thierry Reding
---
drivers/pwm/pwm-atmel-hlcdc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pwm/pwm-atmel-hlcdc.c b/drivers/pwm/pwm-atmel-hlcdc.c
index 54c6633d9b5d.
From: Sandeep Sheriker Mallikarjun
Add the LCD controller for SAM9X60.
Signed-off-by: Sandeep Sheriker Mallikarjun
[claudiu.bez...@microchip.com: add fixed_clksrc option to
atmel_hlcdc_dc_sam9x60]
Signed-off-by: Claudiu Beznea
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 101 +
From: Sandeep Sheriker Mallikarjun
For SAM9X60 SoC, sys_clk is through lcd_gclk clock source and this
needs to be enabled before enabling lcd_clk.
Signed-off-by: Sandeep Sheriker Mallikarjun
[claudiu.bez...@microchip.com: add fixed_clksrc checks]
Signed-off-by: Claudiu Beznea
---
drivers/gpu
On 09.01.2019 16:14, Pavel Machek wrote:
> Hi!
>
>> Add support to check if platform's power will be cut off in suspend.
>> This will help drivers shared by multiple platforms to take only the
>> necessary actions while suspending/resuming (some platform may not need
>> to save/restore all the
On 09.01.2019 18:57, Mark Brown wrote:
> On Tue, Jan 08, 2019 at 10:56:32AM +, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Add helper to check if regulator will be disabled in suspend.
>>
>> Signed-off-by: Claudiu Beznea
>
> This feels like it's the wrong way round -
On 11.01.2019 14:39, Mark Brown wrote:
> On Thu, Jan 10, 2019 at 10:24:26AM +, claudiu.bez...@microchip.com wrote:
>> On 09.01.2019 18:57, Mark Brown wrote:
>
>>> regulator state which feels fragile. But based on the cover letter
>>> that's kind of like what the initial proposal about targ
Hi Nicolas,
On 13.07.2020 13:05, nicolas.fe...@microchip.com wrote:
> From: Nicolas Ferre
>
> Adapt the Wake-on-Lan feature to the Cadence GEM Ethernet controller.
> This controller has different register layout and cannot be handled by
> previous code.
> We disable completely interrupts on all
On 20.08.2020 08:48, Dinghao Liu wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> When devm_clk_get() returns -EPROBE_DEFER, sdio_priv
> should be freed just like when wilc_cfg80211_init()
> fails.
>
> Fixes: 8692b047e86cf ("staging: wil
Hi Dinghao,
On 20.08.2020 08:52, Dinghao Liu wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> When devm_clk_get() returns -EPROBE_DEFER, spi_priv
> should be freed just like when wilc_cfg80211_init()
> fails.
>
> Fixes: 854d66df74aed ("st
On 03.08.2020 19:11, Codrin Ciubotariu - M19940 wrote:
> On 03.08.2020 16:06, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 03.08.2020 11:18, Codrin Ciubotariu wrote:
>>> The new SPDIF TX controller is a serial port compliant with the IEC-
>>> 60958 standard. It also supports programmable User Data
On 03.08.2020 19:11, Codrin Ciubotariu - M19940 wrote:
> On 03.08.2020 16:06, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 03.08.2020 11:18, Codrin Ciubotariu wrote:
>>> The new SPDIF TX controller is a serial port compliant with the IEC-
>>> 60958 standard. It also supports programmable User Data
On 04.08.2020 14:42, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hello,
>
> On 04/08/2020 14:07:37+0300, Claudiu Beznea wrote:
>> void __init at91rm9200_pm_init(void)
>> {
>> + static const int modes[] __init
On 04.08.2020 18:08, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 04/08/2020 15:00:38+, claudiu.bez...@microchip.com wrote:
>>
>>
>> On 04.08.2020 14:42, Alexandre Belloni wrote:
>>> EXTERNAL EMAIL: Do not cli
On 14.11.2020 23:14, Stephen Boyd wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Quoting Claudiu Beznea (2020-11-06 01:46:23)
>> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c
>> b/drivers/clk/at91/clk-sam9x60-pll.c
>> index 78f458a7b
Hi,
Please ignore this series for the moment as I will have to run few more
tests on it. Sorry for the noise!
Thank you,
Claudiu Beznea
On 04.11.2020 19:45, Claudiu Beznea wrote:
> Hi,
>
> SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be
> obtained from CPU PLL. The hard
On 15.07.2020 14:24, Claudiu Beznea wrote:
> Register slow rc with accuracy option.
>
> Fixes: 04bcc4275e601 ("clk: at91: sckc: add support for SAM9X60")
> Signed-off-by: Claudiu Beznea
> ---
> drivers/clk/at91/sckc.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git
On 17.07.2020 12:12, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 15/07/2020 14:24:15+0300, Claudiu Beznea wrote:
>> In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
>> the fractional part of PLL wasn
On 17.07.2020 18:07, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi,
>
> On 15/07/2020 14:24:18+0300, Claudiu Beznea wrote:
>> Replace conditional operator with double logical not.
>
> I think you need to elaborat
On 22.07.2020 17:43, claudiu.bez...@microchip.com wrote:
>
>
> On 22.07.2020 16:44, cristian.bir...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Instead of trying to match every possible compatible use
>> of_find_matching_node_and_match() and pass the compatible array.
>>
>> Signed-off-b
On 23.07.2020 21:59, Florian Fainelli wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 7/21/20 10:13 AM, Codrin Ciubotariu wrote:
>> The MACB embeds an MDIO bus controller. For this reason, the PHY nodes
>> were represented as sub-node
On 21.07.2020 20:13, Codrin Ciubotariu wrote:
> Adding the PHY nodes directly under the Ethernet node became deprecated,
> so the aim of this patch series is to make MACB use an MDIO node as
> container for MDIO devices.
> This patch series starts with a small patch to use the device-managed
> de
On 22.07.2020 16:44, cristian.bir...@microchip.com wrote:
> From: Claudiu Beznea
>
> Instead of trying to match every possible compatible use
> of_find_matching_node_and_match() and pass the compatible array.
>
> Signed-off-by: Claudiu Beznea
> ---
> drivers/usb/gadget/udc/atmel_usba_udc.c |
On 22.07.2020 14:38, Codrin Ciubotariu - M19940 wrote:
> On 22.07.2020 13:32, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 21.07.2020 20:13, Codrin Ciubotariu wrote:
>>> Adding the PHY nodes directly under the Ethernet node became deprecated,
>>> so the aim of this patch series is to make MACB use
Hi Andrew, Florian,
On 30.06.2020 06:35, Florian Fainelli wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 6/29/2020 5:45 PM, Andrew Lunn wrote:
>> On Mon, Jun 29, 2020 at 10:26:36AM +0300, Claudiu Beznea wrote:
>>> In case of_mdiobus_r
On 27.06.2020 00:03, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 25/06/2020 13:09:28+0300, Claudiu Beznea wrote:
>> Return in clk_main_osc_prepare()/clk_main_rc_osc_prepare() if
>> oscillators are already enabled
From: Claudiu Beznea
Add compatible string for SAM9X60 HLCDC's PWM.
Signed-off-by: Claudiu Beznea
Acked-by: Thierry Reding
---
Hi Thierry,
This patch was initially part of series at [1]. The rest of the patches in
that series were taken though drm-misc-next. Only this one remained.
[1]
htt
Hi Daniel,
On 31.05.2019 13:41, Daniel Lezcano wrote:
>
> Hi Claudiu,
>
>
> On 30/05/2019 09:46, claudiu.bez...@microchip.com wrote:
>> Hi Daniel,
>>
>> Taking into account the discussion on this tread and the fact that we have
>> no answer from Rob on this topic (I'm talking about [1]), what d
From: Claudiu Beznea
Add support to free slow rc oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index c1d7edd33416..492b139a7c15 100644
--- a/drivers/c
From: Claudiu Beznea
Add support to free slow clock oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 492b139a7c15..2a677c56f901 100644
--- a/driver
From: Claudiu Beznea
Improve error path for sama5d4 sck registration.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 43 ---
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
in
From: Claudiu Beznea
Improve error path for sam9x5 slow clock registration.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 50 +++--
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at
From: Claudiu Beznea
Add support to free slow oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 2c410f41b413..c1d7edd33416 100644
--- a/drivers/clk/
From: Claudiu Beznea
Remove unnecessary line.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index a2b905c91085..c61b6c9ddb94 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/a
From: Claudiu Beznea
Hi,
This series tries to improve error path for slow clock registrations
by adding functions to free resources and using them on failures.
It is created on top of patch series at [1].
Thank you,
Claudiu Beznea
[1]
https://lore.kernel.org/lkml/1558433454-27971-1-git-send-
From: Claudiu Beznea
Use at91 specific functions to free all resources in case of error.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index f7ad3e9414dc..42502
Hi,
On 18.06.2019 12:55, Alexandre Belloni wrote:
> On 13/06/2019 15:37:06+, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Hi,
>>
>> This series tries to improve error path for slow clock registrations
>> by adding functions to free resources and using them on failures.
>>
Hi Daniel,
On 20.06.2019 11:53, Daniel Lezcano wrote:
> Hi Claudiu,
>
> sorry for the late reply.
No problem, I understand.
>
>
> On 13/06/2019 16:12, claudiu.bez...@microchip.com wrote:
>> Hi Daniel,
>>
>> On 31.05.2019 13:41, Daniel Lezcano wrote:
>>>
>>> Hi Claudiu,
>>>
>>>
>>> On 30/05/20
On 11.05.2019 00:32, Alexandre Belloni wrote:
> On 10/05/2019 11:23:31+, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Different IPs uses different bit offsets in registers for the same
>> functionality, thus adapt the driver to support this.
>>
>> Signed-off-by: Claudiu
Hi Daniel,
Taking into account the discussion on this tread and the fact that we have
no answer from Rob on this topic (I'm talking about [1]), what do you think
it would be best for this driver to be accepted the soonest? Would it be OK
for you to mimic the approach done by:
drivers/clocksource/
From: Claudiu Beznea
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength and
at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit n
From: Claudiu Beznea
This series adds drive strenght and slew rate support for SAMX60's pin
controller. For drive strenght we could have 2 values: low, high.
For slew rate we could have 2 values: enable, disabled.
Besides this I took the chance and adapt the documentation for at91 pinctrl
driver
From: Claudiu Beznea
Add documentation for at91 pin controller banks.
Signed-off-by: Claudiu Beznea
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt| 23 ++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.tx
From: Claudiu Beznea
Add device tree binding for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,a
From: Claudiu Beznea
Add documentation for slew rate.
Signed-off-by: Claudiu Beznea
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicet
From: Claudiu Beznea
Add slew rate support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 48 ++
drivers/pinctrl/pinctrl-at91.h | 1 +
include/dt-bindings/pinctrl/at91.h | 4
3 files changed, 53
From: Claudiu Beznea
Add drive strength support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 52 ++
drivers/pinctrl/pinctrl-at91.h | 2 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/pinctrl/
From: Claudiu Beznea
Add compatibles for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 46443b97d811..5456a2692b8c 100644
--- a/
On 31.01.2019 14:33, Ludovic Desroches wrote:
> On Thu, Jan 31, 2019 at 01:29:33PM +0100, Claudiu Beznea - M18063 wrote:
>> From: Claudiu Beznea
>>
>> Add compatibles for SAM9X60 pin controller.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>> drivers/pinctrl/pinctrl-at91.c | 2 ++
>> 1 file chan
From: Claudiu Beznea
Add drive strength support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 52 ++
drivers/pinctrl/pinctrl-at91.h | 2 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/pinctrl/
From: Claudiu Beznea
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength and
at91_pinctrl_mux_ops::get_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit n
From: Claudiu Beznea
This series adds drive strenght and slew rate support for SAMX60's pin
controller. For drive strenght we could have 2 values: low, high.
For slew rate we could have 2 values: enable, disabled.
Besides this I took the chance and adapt the documentation for at91 pinctrl
driver
From: Claudiu Beznea
Add device tree binding for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,a
From: Claudiu Beznea
Add slew rate support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 48 ++
drivers/pinctrl/pinctrl-at91.h | 1 +
include/dt-bindings/pinctrl/at91.h | 4
3 files changed, 53
From: Claudiu Beznea
Add documentation for at91 pin controller banks.
Signed-off-by: Claudiu Beznea
---
.../bindings/pinctrl/atmel,at91-pinctrl.txt| 23 ++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.tx
From: Claudiu Beznea
Add documentation for slew rate.
Signed-off-by: Claudiu Beznea
---
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
b/Documentation/devicet
From: Claudiu Beznea
Add compatibles for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 46443b97d811..5456a2692b8c 100644
--- a/
Please ignore this one!
I'll send a v2.
On 24.06.2020 10:26, Claudiu Beznea wrote:
> DMA buffers were not freed on failure path of at91ether_open().
> Along with changes for freeing the DMA buffers the enable/disable
> interrupt instructions were moved to at91ether_start()/at91ether_stop()
> funct
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