Hi Philipp,
On Wed, 2013-02-13 at 16:46 +0100, Philipp Zabel wrote:
> These patches add support to configure on-chip SRAM via device-tree
> node or platform data and to obtain the resulting genalloc pool from
> the struct device pointer or a phandle pointing at the device tree node.
> This allows
On Tue, 2013-08-27 at 23:28 +0200, Sebastian Hesselbarth wrote:
> With arch/arm calling of_clk_init(NULL) from time_init(), we can now
> remove mach specific calls to it.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Cc: Dinh Nguyen
> Cc: Russell King
> Cc: Arnd B
Hi Michal,
On Wed, 2013-09-18 at 17:56 +0200, Michal Simek wrote:
> This new subsystem should unify all fpga drivers which
> do the same things. Load configuration data to fpga
> or another programmable logic through common interface.
> It doesn't matter if it is MMIO device, gpio bitbanging,
> et
Hi Sebastian,
On Tue, 2013-10-08 at 14:24 +0200, Sebastian Hesselbarth wrote:
> This adds initial support for the Marvell Berlin (88DE3xxx) SoC family
> and basic machine setup for Armada 1500 (88DE3100) SoCs.
>
> Signed-off-by: Sebastian Hesselbarth
> Reviewed-by: Jason Cooper
> Reviewed-by: T
t; available.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Cc: Olof Johansson
> Cc: Arnd Bergmann
> Cc: Dinh Nguyen
> Cc: Russell King
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> arch/arm/mach-socfpga/socfpga.c |9 ++
On Wed, 2013-09-18 at 19:53 +0200, Sebastian Hesselbarth wrote:
> With arch/arm calling of_clk_init(NULL) from time_init(), we can now
> remove custom .init_time hooks.
>
> Signed-off-by: Sebastian Hesselbarth
> ---
> Cc: Olof Johansson
> Cc: Arnd Bergmann
> Cc: Dinh Ng
|2 +
> drivers/clocksource/dw_apb_timer_of.c| 95 ++---
> include/linux/dw_apb_timer.h |1 -
> 8 files changed, 84 insertions(+), 39 deletions(-)
>
For all the mach-socfpga parts:
Acked-by: Dinh Nguyen
Hi Soren,
On Mon, 2013-06-10 at 10:10 -0700, Soren Brinkmann wrote:
> Add a DT fragment for the zc706 Zynq platform. Also, adding a
> corresponding target to the Makefile and adding an appropriate
> compatibility string in the BSP.
>
> Signed-off-by: Soren Brinkmann
> ---
> arch/arm/boot/dts/Ma
Hi Stephen,
On Fri, 2012-10-12 at 11:14 +1100, Stephen Rothwell wrote:
> Hi Artem,
>
> After merging the l2-mtd tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> ERROR: "denali_init" [drivers/mtd/nand/denali_pci.ko] undefined!
> ERROR: "denali_remove" [drivers/mtd/nand
<42 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> rst: rstmgr@ffd05000 {
>
Acked-by: Dinh Nguyen
Dinh
<34 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> rst: rstmgr@ffd05000 {
>
Acked-by: Dinh Nguyen
Dinh
0_socdk_sdmmc.dts | 12
> 1 file changed, 12 insertions(+)
>
Acked-by: Dinh Nguyen
Thanks,
Dinh
Hi Philipp,
just a minor nit:
On 08/24/2016 08:28 AM, Philipp Zabel wrote:
> Visible only if COMPILE_TEST is enabled, this allows to include the
> driver in build tests.
>
> Cc: Dinh Nguyen
> Signed-off-by: Philipp Zabel
> ---
> drivers/reset/Kconfig | 6 ++
> dr
abling the over-current condition.
Signed-off-by: Dinh Nguyen
---
drivers/usb/dwc2/core.h | 4
drivers/usb/dwc2/hcd.c| 5 +
drivers/usb/dwc2/params.c | 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 8367d4f9..730d
The dwc2 USB controller in Stratix10 has an additional ECC reset bit that
needs to get de-asserted in order for the controller to work properly.
Signed-off-by: Dinh Nguyen
---
drivers/usb/dwc2/core.h | 1 +
drivers/usb/dwc2/platform.c | 10 ++
2 files changed, 11 insertions
On Tue, 13 Oct 2015, Steffen Trumtrar wrote:
> Hi Alan!
>
> On Tue, Oct 13, 2015 at 01:28:20PM -0500, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > Add FPGA manager to device tree for SoCFPGA.
> >
> > Signed-off-by: Alan Tull
> > ---
> > arch/arm/boot/dts/socfpga.dtsi | 7 ++
On Tue, 13 Oct 2015, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Enable fpga manager framework and low level driver for
> socfpga in socfpga_defconfig
>
> Signed-off-by: Alan Tull
> ---
> arch/arm/configs/socfpga_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied!
T
On Tue, 13 Oct 2015, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add FPGA manager to device tree for SoCFPGA.
>
> Signed-off-by: Alan Tull
> ---
> v2: Remove 0x after @
> No caps in hex numbers
> renamed hps_0_fpgamgr to fpgamgr0
> move node to be in alpha order by nod
On Tue, 13 Oct 2015, Steffen Trumtrar wrote:
> On Tue, Oct 13, 2015 at 02:51:28PM -0500, Dinh Nguyen wrote:
> > On Tue, 13 Oct 2015, at...@opensource.altera.com wrote:
> >
> > > From: Alan Tull
> > >
> > > Add FPGA manager to device tree for SoCF
Hi,
commit "8b63ec1837fa phylib: Make PHYs children of their MDIO bus, not
the bus' parent." seems to have broken ethernet support for the SoCFPGA
platform which is using the stmmac ethernet driver.
It appears that during DHCP, it cannot get an IP address. This only
happens if ethernet was not us
On 10/15/2015 03:03 PM, Florian Fainelli wrote:
> On 15/10/15 12:09, Dinh Nguyen wrote:
>> Hi,
>>
>> commit "8b63ec1837fa phylib: Make PHYs children of their MDIO bus, not
>> the bus' parent." seems to have broken ethernet support for the SoCFPGA
>
On 10/15/2015 03:35 PM, David Daney wrote:
> On 10/15/2015 01:25 PM, Florian Fainelli wrote:
>> On 15/10/15 12:59, Dinh Nguyen wrote:
>>> On 10/15/2015 03:03 PM, Florian Fainelli wrote:
>>>> On 15/10/15 12:09, Dinh Nguyen wrote:
>>>>> Hi,
>>>&g
On Thu, 15 Oct 2015, Florian Fainelli wrote:
> On 15/10/15 13:49, Dinh Nguyen wrote:
> >>
> >> Does this text change with and without the 8b63ec1837fa patch?
> >
> > No, this text does not change with/without the 8b63ec1837fa patch.
>
> Could you instrume
On Thu, 15 Oct 2015, Florian Fainelli wrote:
> On 15/10/15 13:49, Dinh Nguyen wrote:
> >>
> >> Does this text change with and without the 8b63ec1837fa patch?
> >
> > No, this text does not change with/without the 8b63ec1837fa patch.
>
> Could you instrume
On Fri, 16 Oct 2015, Andrew Lunn wrote:
> > Another debugging point, the SoCFPGA board has a Micrel ksz9021 PHY attached
> > to the ethernet port. What I'm seeing is that with 8b63ec1837fa patch, when
> > the call to ksz9021_config_init() is made both of_node and
> > dev->parent->of_node
> > are
On Fri, 16 Oct 2015, Andrew Lunn wrote:
> On Fri, Oct 16, 2015 at 09:38:37AM -0500, Dinh Nguyen wrote:
> > On Fri, 16 Oct 2015, Andrew Lunn wrote:
> >
> > > > Another debugging point, the SoCFPGA board has a Micrel ksz9021 PHY
> > > > attached
> >
On Fri, 16 Oct 2015, David Daney wrote:
> On 10/16/2015 08:56 AM, Andrew Lunn wrote:
> > > So I think I'll move to inspect what Florian had suggested, and that was
> > > to look
> > > at:
> > > drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c::stmmac_mdio_register
> >
> > I have a suspicion. If
On Mon, 19 Oct 2015, Dinh Nguyen wrote:
+CC Giuseppe Cavallaro
+CC STi and Rockchip Maintainers
This is approaching beyond my breadth of knowledge on this subject, so I just
wanted to get some further insight.
>
> On Fri, 16 Oct 2015, Andrew Lunn wrote:
>
> > > > Maybe w
+CC Giuseppe Cavallaro
+CC STi and Rockchip Maintainers
This is approaching beyond my breadth of knowledge on this subject, so I just
wanted to get some further insight.
On Fri, 16 Oct 2015, Andrew Lunn wrote:
> > > Maybe we need to walk up the hierarchy.
> > >
> > > Perhaps something like:
> >
On 06/22/2018 10:58 AM, Richard Weinberger wrote:
> Masahiro,
>
> Am Freitag, 22. Juni 2018, 16:37:21 CEST schrieb Masahiro Yamada:
>> Hi Richard,
>>
>>
>> 2018-06-19 21:07 GMT+09:00 Richard Weinberger :
>>> The denali NAND flash controller needs at least two clocks to operate,
>>> nand_clk and
On 05/10/2017 12:13 AM, yanjiang@windriver.com wrote:
> From: Yanjiang Jin
>
> Kexec's second kernel would hang if CPU1 isn't reset.
>
Can you please be a bit more descriptive on the commit log? Is it
because when kexec starts, the SMP on the kexec's kernel try to run on CPU1?
> Signed-
ent property so we can correct parse
> that interrupt number.
>
> Signed-off-by: Arnd Bergmann
> ---
> If this looks ok, I'd apply it directly to the fixes branch
> for 4.15, as the warning is one that was introduced in this
> release.
Acked-by: Dinh Nguyen
Yes, please feel free to apply it. And thanks alot!
Dinh
On 01/16/2018 03:29 AM, Steffen Trumtrar wrote:
> From: Tim Sander
>
> Add the reset signals for the i2c controllers on Cyclone5-based
> SoCFPGA boards to the dtsi.
>
> Signed-off-by: Tim Sander
> Signed-off-by: Steffen Trumtrar
> ---
> arch/arm/boot/dts/socfpga.dtsi | 4
> 1 file chan
Hi Alan,
On 02/21/2018 02:25 PM, Alan Tull wrote:
> Add clock for i2c
> Enable i2c1
> Set the i2c bus speed to 100KHz
> Add the following i2c peripherals
> * ds1339 RTC
> * 24c32 EEPROM
> * max1619 temperature monitor
> * ltc2497 ADC
> * Add a fixed regulator for the ADC's Vref.
>
> This requir
On 02/20/2018 09:38 AM, Graham Moore wrote:
> The Stratix10 SoCFPGA uses the PL330 DMAC. This patch adds the PL330
> DMAC to the Stratix10 device tree.
>
> Signed-off-by: Graham Moore
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 19 +++
> 1 file changed, 19 inse
tera/socfpga_stratix10_socdk.dts
> @@ -88,7 +88,6 @@
>
> &mmc {
> status = "okay";
> - num-slots = <1>;
> cap-sd-highspeed;
> broken-cd;
> bus-width = <4>;
>
Acked-by: Dinh Nguyen
On 04/11/2018 10:20 AM, Thor Thayer wrote:
> Hi. Any comments on this patch?
>
> On 03/26/2018 02:50 PM, thor.tha...@linux.intel.com wrote:
>> From: Thor Thayer
>>
>> Remove QSPI Sector 4K size force which is causing QSPI boot
>> problems with the JFFS2 root filesystem.
>>
>> Fixes the followin
On 03/23/2018 04:22 AM, Philipp Puschmann wrote:
> Fixes the warning "GIC: PPI13 is secure or misconfigured" by
> changing the interrupt type from level_low to edge_raising
>
> Signed-off-by: Philipp Puschmann
> ---
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 d
Ping?
On 09/17/2018 09:50 AM, Dinh Nguyen wrote:
> Create a separate reset driver that uses the reset operations in reset-simple.
> The reset driver for the SoCFPGA platform needs to register early in order to
> be able bring online timers that needed early in the kernel bootup.
>
Ping?
On 09/17/2018 09:52 AM, Dinh Nguyen wrote:
> Add code to retrieve the reset property for the dw-apb timers.
>
> Signed-off-by: Marek Vasut
> Signed-off-by: Dinh Nguyen
> ---
> drivers/clocksource/dw_apb_timer_of.c | 9 +
> 1 file changed, 9 insertions
On 09/26/2018 10:21 AM, Daniel Lezcano wrote:
> On 17/09/2018 16:52, Dinh Nguyen wrote:
>> Add code to retrieve the reset property for the dw-apb timers.
>
> The patch does more than that. Can you explain why the assert/deassert ?
Can I update the commit message to this?
Add c
On 09/27/2018 09:22 AM, Daniel Lezcano wrote:
> On 27/09/2018 15:52, Dinh Nguyen wrote:
>> Add code to retrieve the reset property from the dw-apb timers and if
>> the property is available, the safe operation is to assert the timer
>> into reset, and followed by a deasse
On 11/15/18 3:32 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-11-05 at 14:05 -0600, Dinh Nguyen wrote:
>> "altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
>>
>> Signed-off-by: Dinh Nguyen
>> ---
>> Documentatio
On 11/15/18 3:33 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-11-05 at 14:05 -0600, Dinh Nguyen wrote:
>> From: Dinh Nguyen
>>
>> The standard reset-simple driver the uses the "altr,rst-mgr" binding is
>> not getting initialized early enough
On 11/15/18 9:34 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Tue, 2018-11-13 at 12:50 -0600, Dinh Nguyen wrote:
>> @@ -120,7 +120,8 @@ static const struct reset_simple_devdata
>> reset_simple_active_low = {
>> };
>>
>> static const
platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.
Signed-off-by: Dinh Nguyen
---
v4: remove !ARCH_STRATIX10 condition in Kconfig
clean up checkpatch.pl errors
v3: use "altr,stratix10-rst-mgr" for Stratix10
remove "altr,modrst-offset" from reset-simple
v
Hi Stephen,
On 12/5/18 1:17 AM, Stephen Boyd wrote:
> (Adding Dinh's korg email)
>
> I also wonder if this driver is even used anymore or maybe we can delete
> it?
>
The armv7 SoCFPGA platforms are using this driver.
Dinh
On 12/5/18 9:55 AM, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2018-12-05 07:17:41)
>> Hi Stephen,
>>
>> On 12/5/18 1:17 AM, Stephen Boyd wrote:
>>> (Adding Dinh's korg email)
>>>
>>> I also wonder if this driver is even used anymore or ma
On 11/29/18 6:56 AM, Clément Péron wrote:
> unit-address does not have a leading "0x" (the number is assumed to be
> hexadecimal).
>
> Signed-off-by: Clément Péron
> ---
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied!
Thanks,
Dinh
On 11/5/18 2:39 PM, Simon Goldschmidt wrote:
> In two of the gen5 socfpga devicetree files, there are some lines
> indented using spaces instead of tabs.
>
> Fix this by correctly indenting them with tabs.
>
> Signed-off-by: Simon Goldschmidt
> ---
> arch/arm/boot/dts/socfpga.dtsi
On 07/01/2018 08:35 PM, Masahiro Yamada wrote:
> Hi Dinh,
>
> 2018-06-27 23:55 GMT+09:00 Dinh Nguyen :
>> Hi Masahiro,
>>
>> On 06/26/2018 09:52 PM, Masahiro Yamada wrote:
>>> 2018-06-27 3:09 GMT+09:00 Miquel Raynal :
>>>> Hi Masahiro,
>&g
Hi Masahiro,
On 06/26/2018 09:52 PM, Masahiro Yamada wrote:
> 2018-06-27 3:09 GMT+09:00 Miquel Raynal :
>> Hi Masahiro,
>>
>> On Tue, 26 Jun 2018 11:38:21 +0900, Masahiro Yamada
>> wrote:
>>
>>> 2018-06-25 23:55 GMT+09:00 Boris Brezillon :
>>>&g
On 08/08/2018 10:42 AM, Alan Tull wrote:
> DesignWare I2C controller was observed running at 105.93kHz rather
> than the specified 100kHz. Adjust device tree settings to bring it
> within spec (a slightly conservative 98 MHz).
>
> Signed-off-by: Alan Tull
> ---
> arch/arm64/boot/dts/altera/s
On 08/08/2018 04:09 AM, Simon Goldschmidt wrote:
> Use stdout-path dts property for kernel console.
>
> There were two socfpga boards left not using stdout-path:
> socrates and vining. Make sure they match the other boards.
>
> Signed-off-by: Simon Goldschmidt
> ---
> arch/arm/boot/dts/socfp
Zabel
> ---
Acked-by: Dinh Nguyen
On 12/13/18 2:59 PM, dwest...@gmail.com wrote:
> From: Dalon Westergreen
>
> Add the stmmac ptp_ref clock as it is configured in the arria10 socdk.
> The stmmac driver defaults the ptp_ref clock to the main stmmac clock
> if the ptp_ref clock is not set in the devicetree. This is inapprotiate
On 12/17/18 7:54 PM, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2018-12-06 07:16:47)
>>
>>
>> On 12/5/18 9:55 AM, Stephen Boyd wrote:
>>> Quoting Dinh Nguyen (2018-12-05 07:17:41)
>>>> Hi Stephen,
>>>>
>>>> On 12/5/18 1:17 AM,
Hi Simon,
On 10/23/2018 02:08 PM, Simon Goldschmidt wrote:
> Follow the recent trend for the license description.
>
> This is also in an effort to fully sync the devicetrees with U-Boot.
>
> Signed-off-by: Simon Goldschmidt
> ---
> arch/arm/boot/dts/socfpga.dtsi| 16 +--
>
Hi Philipp
On 10/17/2018 09:37 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Thu, 2018-10-11 at 08:52 -0500, Dinh Nguyen wrote:
>> Create a separate reset driver that uses the reset operations in
>> reset-simple. The reset driver for the SoCFPGA platform needs to
>> re
Hi Clément,
On 11/2/18 10:58 AM, Clément Péron wrote:
> Hi Dinh,
>
> Could you have a look at this serie ?
>
I've applied 1/3 and 3/3. I need to look over 2/3 to determine if that
patch is still valid. I think a better solution would be to set a clock
as critical so that it doesn't get gated.
, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer.
Signed-off-by: Dinh Nguyen
---
v2: Do not build separate reset driver for STRATIX10
fix warning: symbol 'socfpga_reset_init' was not declared. Should
it be static?
---
author or do you just mention it? in the
> commit log ?
Sure, just keep the original Signed-off-by:.
Thanks,
Dinh
>
> Thanks,
> Clement
>
> From 6f7559407c1fcdb9b31c9493f0da79d614290e91 Mon Sep 17 00:00:00 2001
> From: Dinh Nguyen
> Date: Wed, 27 Feb 2013 18:29:14 -060
On 10/04/2018 04:53 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-09-17 at 09:50 -0500, Dinh Nguyen wrote:
>> Create a separate reset driver that uses the reset operations in
>> reset-simple.
>> The reset driver for the SoCFPGA platform needs to register e
?
Thanks,
Dinh
On 10/05/2018 10:30 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Fri, 2018-10-05 at 10:17 -0500, Dinh Nguyen wrote:
> [...]
>>>> +static int a10_reset_init(struct device_node *np)
>>>> +{
>>>> + struct reset_simple_data *data;
>>&
From: Dinh Nguyen
The standard reset-simple driver the uses the "altr,rst-mgr" binding is
not getting initialized early enough in the boot process, so timers
that the kernel needs are still left in reset. Thus an early
reset driver was created. This early reset driver is only for the
From: Dinh Nguyen
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.
We do not need this early reset driver for Stratix10
"altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
Signed-off-by: Dinh Nguyen
---
Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/socfpga-re
On 11/5/18 2:27 PM, Simon Goldschmidt wrote:
> Follow the recent trend for the license description.
>
> This is also in an effort to fully sync the devicetrees with U-Boot.
>
> Signed-off-by: Simon Goldschmidt
> ---
> Resending this as requested by Dinh. It still applies on top of
> 4.20-rc1
Hi Clément,
On 10/09/2018 06:28 AM, Clément Péron wrote:
> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>
> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for
> Cylone5.
>
I'm not sure the need for this patch. Are there any cyclone5 based
boards that has
On 10/23/2018 09:44 AM, Clément Péron wrote:
> HI Dinh,
>
> On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
>>
>> Hi Clément,
>>
>> On 10/09/2018 06:28 AM, Clément Péron wrote:
>>> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
Hi
On 10/24/2018 09:11 AM, Clément Péron wrote:
> Hi,
>
> On Wed, 24 Oct 2018 at 08:51, Uwe Kleine-König
> wrote:
>>
>> On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
>>>
>>>
>>> On 10/23/2018 09:44 AM, Clément Péron wrote:
&
Create a separate reset driver that uses the reset operations in reset-simple.
The reset driver for the SoCFPGA platform needs to register early in order to
be able bring online timers that needed early in the kernel bootup.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/socfpga.c | 4
Add code to retrieve the reset property for the dw-apb timers.
Signed-off-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource
On 01/05/2015 09:02 PM, Paul Zimmerman wrote:
>> From: Kever Yang [mailto:kever.y...@rock-chips.com]
>> Sent: Monday, January 05, 2015 5:42 PM
>>
>> Hi Paul,
>>
>> I think you need this patch to fix the problem:
>>
>> usb: dwc2: resume root hub when device detect with suspend state
>> https://patch
Hi Walter,
On 3/19/15 4:27 PM, Walter Lozano wrote:
> Hi Dinh,
>
> On Mon, Mar 16, 2015 at 10:10 AM, Walter Lozano
> wrote:
>> On Mon, Jan 5, 2015 at 6:21 AM, Steffen Trumtrar
>> wrote:
>>> Hi!
>>>
>>> On Wed, Dec 24, 2014 at 08:11:52PM -0300, Walter Lozano wrote:
This patch adds the DTS b
On 04/20/2015 11:24 AM, Vince Bridgers wrote:
> Add multicast-filter-bins and perfect-filter-entries configuration properties
> to the socfpga devicetree for the Arria 10 socfpga.
>
> Signed-off-by: Vince Bridgers
> ---
> This patch is based on patches
> http://www.spinics.net/lists/devicetree/ms
Hi Mike, Stephen,
On 04/02/2015 11:40 PM, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> Hi,
>
> This patch series add the clock driver for the Arria10 platform. Although the
> Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the
&
Hi Joe,
On Thu, Apr 16, 2015 at 5:54 PM, Rob Herring wrote:
> +arm-soc
>
> On Thu, Apr 16, 2015 at 5:49 PM, Joe Perches wrote:
>> Change the .dts file permissions from 755 to 644.
>>
>> Signed-off-by: Joe Perches
>
> ARM dts files go in thru arm-soc tree.
>
> Acked-by: Rob Herring
>
Thanks fo
On Mon, Apr 20, 2015 at 10:45 AM, Joe Perches wrote:
> On Mon, 2015-04-20 at 10:37 -0500, Dinh Nguyen wrote:
>> On Thu, Apr 16, 2015 at 5:54 PM, Rob Herring wrote:
>> > +arm-soc
>> > On Thu, Apr 16, 2015 at 5:49 PM, Joe Perches wrote:
>> >> Change th
On 05/27/2015 03:25 PM, atull wrote:
> On Tue, 26 May 2015, Dinh Nguyen wrote:
>
>> Hi Alan,
>>
>> On 5/22/15 1:02 PM, Alan Tull wrote:
>>> Add code that requests that the sdr controller go into
>>> self-refresh mode. This code is run from ocram.
rm from going into suspend.
>
> Example of how to request to suspend to ram:
> $ echo enabled > \
> /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup
>
> $ echo -n mem > /sys/power/state
>
> Signed-off-by: Alan Tull
> Cc: Pavel Machek
> Cc: Arnd Bergmann
On 06/11/2015 04:06 AM, Maxime Ripard wrote:
> Hi Dinh,
>
> On Wed, Jun 10, 2015 at 04:49:24PM -0500, dingu...@opensource.altera.com
> wrote:
>> From: Dinh Nguyen
>>
>> Use of_clk_parent_fill to fill in the parent clock names' array.
>>
>> Signed-o
On 06/04/2015 05:06 PM, Borislav Petkov wrote:
> On Thu, Jun 04, 2015 at 04:34:49PM -0500, Thor Thayer wrote:
>> OK. I'll refactor and resend. I was using Altera's internal for-next branch.
>
> Use this one:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git#for-next
>
This is my mista
Hi Alan,
On 06/02/2015 02:22 PM, Dinh Nguyen wrote:
> On 06/02/2015 01:35 PM, Alan Tull wrote:
>> Support suspend to ram on socfpga.
>> * allocate space in ocram using sram driver.
>> * Add a function in ocram to place DDR in self-refresh
>> and suspend.
>&g
On Thu, Jun 4, 2015 at 5:35 PM, Dinh Nguyen
wrote:
> Hi Alan,
>
> On 06/02/2015 02:22 PM, Dinh Nguyen wrote:
>> On 06/02/2015 01:35 PM, Alan Tull wrote:
>>> Support suspend to ram on socfpga.
>>> * allocate space in ocram using sram driver.
>>> * Ad
Hi Boris,
On 6/5/15 4:17 AM, Borislav Petkov wrote:
> On Thu, Jun 04, 2015 at 05:27:28PM -0500, Dinh Nguyen wrote:
>> This is my mistake. I applied Alan Tull's patch for suspend-to-ram which
>> also touches drivers/edac/altera_edac.c.
>>
>> https://git.kernel.or
On 6/5/15 6:02 AM, Borislav Petkov wrote:
> On Thu, Jun 04, 2015 at 09:28:44AM -0500, ttha...@opensource.altera.com wrote:
>> From: Thor Thayer
>>
>> This series of patches adds support for the Arria10 EDAC. The
>> SDRAM controller and ECC registers are significantly different
>> from the Cyclon
On 6/4/15 4:24 PM, Stephen Boyd wrote:
> On 06/04, dingu...@opensource.altera.com wrote:
>> From: Dinh Nguyen
>>
>> Sprinkled all through the platform clock drivers are code like this to
>> fill the clock parent array:
>>
>> for (i = 0; i <
On 06/02/2015 01:35 PM, Alan Tull wrote:
> Support suspend to ram on socfpga.
> * allocate space in ocram using sram driver.
> * Add a function in ocram to place DDR in self-refresh
> and suspend.
> * Prevent suspend if EDAC is enabled.
> * Add a device tree binding document for the Alt
On 06/04/2015 09:28 AM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> The Arria10 SOC uses a completely different SDRAM controller from the
> earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
> for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.
>
> Signed-off-by: Hiraku Toyooka
> Cc: Dinh Nguyen
> Cc: Russell King
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> arch/arm/mach-socfpga/platsmp.c | 12
> 1 file changed, 12 insertions(+)
>
Applied!
Than
Use platform driver APIs to map memory so that it will automatically free
the memory in case of errors.
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-s10.c | 35 +++
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/socfpga/clk
The Stratix10 clock driver is essential to system operation, so their
removal should never happen.
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-s10.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index c788997
On 05/11/2018 11:10 AM, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Add qspi_clock
>The qspi_clk frequency is updated by U-Boot before starting Linux.
> Add QSPI interface node.
> Add QSPI flash memory child node.
>Setup the QSPI memory in 2 partitions.
>
> Signed-off-by
On 05/15/2018 05:26 PM, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Add qspi_clock
>The qspi_clk frequency is updated by U-Boot before starting Linux.
> Add QSPI interface node.
> Add QSPI flash memory child node.
>Setup the QSPI memory in 2 partitions.
>
> Signed-off-by
Get the reset control for the QSPI controller and bring it out of reset.
Suggested-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
drivers/mtd/spi-nor/cadence-quadspi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
b/drivers/mtd/spi
Add arch/arm64/boot/dts/intel/ under Dinh Nguyen.
Signed-off-by: Dinh Nguyen
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e17ebf70b548..8c90df31aaf0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2189,6 +2189,7 @@ F:arch/arm/mach
Get the reset control for the QSPI controller and bring it out of reset.
Suggested-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
v2: use devm_reset_control_get_optional_exclusive
print an error message
return -EPROBE_DEFER
---
drivers/mtd/spi-nor/cadence-quadspi.c | 14
Hi Andrey,
On 2/22/19 6:21 AM, Andrey Zhizhikin wrote:
> Enable CONFIG_LBDAF, which is required by ext4 fs. This option could
> hanle both ext3 and ext4, and ex4 requires this option to be enabled,
> otherwise the filesystem is mounted RO mode.
>
> Signed-off-by: Andrey Zhizhikin
> ---
> arch/a
Hi Thor,
On 2/19/19 12:59 PM, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Enable the different ECC blocks by default on Cyclone5
> and Arria10.
>
> Signed-off-by: Thor Thayer
> ---
> arch/arm/configs/socfpga_defconfig | 36 ++--
> 1 file changed,
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