Nothing prevents Tegra20 CPUFreq module to be unloaded, hence allow it to
be built as a non-builtin kernel module.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/Kconfig.arm | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq
Remove unneeded blank line and replace whitespaces with a tab in the code
for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers/cpufreq/tegra20
,
other patch will instantiate the actual platform device. And now it makes
sense to wrap cpufreq driver into a platform driver for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 116 +++---
1 file changed, 73 insertions(+), 43 deletions
Tegra20-cpufreq driver require a platform device in order to be loaded,
instantiate a simple platform device for the driver during of the machines
late initialization.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/tegra.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm
Remove unneeded variable initialization solely for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers/cpufreq/tegra20-cpufreq.c
index 797c61c74b65
Don't even try to request the clocks during of module initialization on
non-Tegra20 machines (this is the case for a multi-platform kernel) for
consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers
Remove checking of the CPU number for consistency as it won't ever fail
unless there is a severe bug in the cpufreq core.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers
The EMC driver has been gone 4 years ago, since the commit a7cbe92cef27
("ARM: tegra: remove tegra EMC scaling driver"). Remove the EMC clock
usage as it does nothing. We may consider re-implementing the EMC scaling
later, probably using PM Memory Bandwidth QoS API.
Signed-off-by: Dmitr
Remove unused/unneeded headers and sort them in the alphabet order.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers/cpufreq/tegra20-cpufreq.c
index
Properly put requested clocks in the module init/exit code.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers/cpufreq/tegra20
module to be
loaded on non-Tegra20 machines, by cleaning whitespaces in the code, removing
dead EMC code and in the end by allowing tegra20-cpufreq to be built as a
loadable module.
Please review, thanks.
Dmitry Osipenko (11):
cpufreq: tegra20: Change module description
cpufreq: tegra20: Clean up
Change module description to be in line with the other Tegra drivers, just
for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers/cpufreq/tegra20
Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
that main clk-controller driver could get an actual parent clock for the
CDEV1/2 clocks.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Marcel Ziswiler
CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as
a parent. Add these dividers in order to be able to provide that parent
option.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Marcel Ziswiler
Tested-by: Marcel Ziswiler
Tested-by: Marc Dietrich
Acked-by: Peter De Schrijver
one board and broke the
other, now Tegra's clk driver correctly sets parent for the CDEV2 clock
and hence patch could be reverted safely, restoring USB for all of the
boards.
Signed-off-by: Dmitry Osipenko
Reviewed-by: Marcel Ziswiler
Tested-by: Marcel Ziswiler
Tested-by: Marc Dietrich
---
arch
alleij.
- Addressed v1 review comments: fixed swapped DEV1/2 clk div bits,
made DEV1/2 divs read-only, etc minor changes.
Dmitry Osipenko (4):
clk: tegra20: Add DEV1/DEV2 OSC dividers
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra: Add quirk for getting C
Parents of CDEV1/2 clocks are determined by muxing of the corresponding
pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence
CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the
corresponding muxes to fix the parents.
Signed-off-by: Dmitry Osipenko
Reviewed
to be enabled by the child, so let's return -EPROBE_DEFER
till parent clock appears.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra114.c | 2 +-
drivers/clk/tegra/clk-tegra124.c | 2 +-
drivers/clk/tegra/clk-tegra20.c | 32 +++-
drivers/clk/tegra/clk
Memory Controller driver invokes SMMU driver registration and MC's
registers mapping is shared with SMMU. This mapping goes away if MC
driver probing fails after SMMU registration.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 18 +-
1 file changed, 9 insertions
by a
misbehaving client.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 40 ++
drivers/memory/tegra/tegra114.c | 64 +
drivers/memory/tegra/tegra124.c | 66 +
drivers/memory/tegra/tegra20.c | 52
GART can't handle all devices, ignore devices that aren't related to GART.
Device tree must explicitly assign GART IOMMU to the devices.
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/tegra-gart.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff
GART contains registers needed by the Memory Controller driver. Provide
access to the MC driver by utilizing its GART-integration facility.
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/tegra-gart.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/iommu
GART driver is built-in, hence it can't be unloaded. This patch merely
removes the dead code.
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/tegra-gart.c | 25 +++--
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu
Currently GART writes one page entry at a time. More optimal would be to
aggregate the writes and flush BUS buffer in the end, this gives map/unmap
10-40% (depending on size of mapping) performance boost compared to a
flushing after each entry update.
Signed-off-by: Dmitry Osipenko
---
drivers
Introduce iotlb_sync_map() callback that is invoked in the end of
iommu_map(). This new callback allows IOMMU drivers to avoid syncing
on mapping of each contiguous chunk and sync only when whole mapping
is completed, optimizing performance of the mapping operation.
Signed-off-by: Dmitry Osipenko
t;
domains will stomp on each other.
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/tegra-gart.c | 107 +
1 file changed, 24 insertions(+), 83 deletions(-)
diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
index 5b2d27620350..ebc105c20
dead code,
allowing to have one IOMMU domain at max, etc.
4. This series introduces and utilizes iotlb_sync_map() callback that was
previously suggested by Joerg Roedel in [1].
[1] https://www.spinics.net/lists/linux-tegra/msg32914.html
Dmitry Osipenko (9):
memory: tegra: Provid
Properly clean up allocated resources on driver probe failure.
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/tegra-gart.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
index 08e0de4087d1
In order to report clients name and access direction on GART page fault,
MC driver needs to access GART registers. Add facility that provides
access to the GART.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 26 +++---
include/soc/tegra/mc.h| 13
Remove unneeded 'includes' and sort them in alphabet order. Also remove
pr_fmt since there is no pr_xxx() and it doesn't affect dev_xxx().
Signed-off-by: Dmitry Osipenko
---
drivers/iommu/tegra-gart.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers
On 18.05.2018 04:58, Viresh Kumar wrote:
> On 17-05-18, 21:00, Dmitry Osipenko wrote:
>> Remove unused/unneeded headers and sort them in the alphabet order.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> drivers/cpufreq/tegra20-cpufreq.c | 11 ++-
>&
On 18.05.2018 05:07, Viresh Kumar wrote:
> On 17-05-18, 21:00, Dmitry Osipenko wrote:
>> -static int __init tegra_cpufreq_init(void)
>> +static int tegra20_cpufreq_probe(struct platform_device *pdev)
>> {
>> +struct tegra20_cpufreq_
On 18.05.2018 10:30, Rafael J. Wysocki wrote:
> On Thursday, May 17, 2018 8:00:45 PM CEST Dmitry Osipenko wrote:
>> Hello,
>>
>> Recently Peter Geis (who is working on Tegra30 cpufreq driver) asked me how
>> tegra20-cpufreq driver is getting loaded. After taking a lo
On 18.05.2018 12:07, Thierry Reding wrote:
> On Thu, May 17, 2018 at 09:00:55PM +0300, Dmitry Osipenko wrote:
>> Currently tegra20-cpufreq kernel module isn't getting autoloaded because
>> there is no device associated with the module, this is one of two patches
>> tha
On 18.05.2018 12:13, Thierry Reding wrote:
> On Thu, May 17, 2018 at 09:00:56PM +0300, Dmitry Osipenko wrote:
>> Tegra20-cpufreq driver require a platform device in order to be loaded,
>> instantiate a simple platform device for the driver during of the machines
>>
Remove unnecessary parentheses as suggested by the checkpatch script.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers/cpufreq/tegra20-cpufreq.c
index
,
other patch will instantiate the actual platform device. And now it makes
sense to wrap cpufreq driver into a platform driver for consistency.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
---
drivers/cpufreq/tegra20-cpufreq.c | 145 ++
1 file changed, 86
Remove unused/unneeded headers and sort them in the alphabet order.
Signed-off-by: Dmitry Osipenko
Acked-by: Thierry Reding
---
drivers/cpufreq/tegra20-cpufreq.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers
The EMC driver has been gone 4 years ago, since the commit a7cbe92cef27
("ARM: tegra: remove tegra EMC scaling driver"). Remove the EMC clock
usage as it does nothing. We may consider re-implementing the EMC scaling
later, probably using PM Memory Bandwidth QoS API.
Signed-off-by: Dmitr
Nothing prevents Tegra20 CPUFreq module to be unloaded, hence allow it to
be built as a non-builtin kernel module.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
Acked-by: Thierry Reding
---
drivers/cpufreq/Kconfig.arm | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Remove unneeded variable initialization solely for consistency.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
Acked-by: Thierry Reding
---
drivers/cpufreq/tegra20-cpufreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers
Change module description to be in line with the other Tegra drivers, just
for consistency.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
Acked-by: Thierry Reding
---
drivers/cpufreq/tegra20-cpufreq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpufreq
Don't even try to request the clocks during of module initialization on
non-Tegra20 machines (this is the case for a multi-platform kernel) for
consistency.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
Acked-by: Thierry Reding
---
drivers/cpufreq/tegra20-cpufreq.c | 4
1 file
Remove checking of the CPU number for consistency as it won't ever fail
unless there is a severe bug in the cpufreq core.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
Acked-by: Thierry Reding
---
drivers/cpufreq/tegra20-cpufreq.c | 5 -
1 file changed, 5 deletions(-)
diff --git
Properly put requested clocks in the module init/exit code.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
Acked-by: Thierry Reding
---
drivers/cpufreq/tegra20-cpufreq.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/cpufreq
Remove unneeded blank line and replace whitespaces with a tab in the code
for consistency.
Signed-off-by: Dmitry Osipenko
Acked-by: Viresh Kumar
Acked-by: Thierry Reding
---
drivers/cpufreq/tegra20-cpufreq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/cpufreq
changes for v4.18-rc1" pull request.
Dmitry Osipenko (11):
cpufreq: tegra20: Change module description
cpufreq: tegra20: Clean up whitespaces in the code
cpufreq: tegra20: Clean up included headers
cpufreq: tegra20: Remove EMC clock usage
cpufreq: tegra20: Release clocks properly
Map firewall-copied buffers into Host1x's IOVA space, otherwise Host1x
CDMA can't access the command buffers and all submitted jobs fail if IOMMU
and Host1x firewall are enabled in the kernels config.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/host1x/job.c | 58
On 19.05.2018 02:52, Dmitry Osipenko wrote:
> Map firewall-copied buffers into Host1x's IOVA space, otherwise Host1x
> CDMA can't access the command buffers and all submitted jobs fail if IOMMU
> and Host1x firewall are enabled in the kernels config.
>
> Signed-off-by:
buffer and hence IOMMU isn't needed in this case.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/host1x/dev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index f1d5f76e9c33..d88073e7d22d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b
On 18.05.2018 13:39, Thierry Reding wrote:
> On Tue, May 08, 2018 at 07:26:04PM +0300, Dmitry Osipenko wrote:
>> Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
>> Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
>> that main
On 16.04.2018 21:21, Stefan Agner wrote:
> On 16.04.2018 18:08, Stephen Warren wrote:
>> On 04/16/2018 09:56 AM, Stefan Agner wrote:
>>> On 27.03.2018 14:16, Dmitry Osipenko wrote:
>>>> On 27.03.2018 14:54, Robin Murphy wrote:
>>>>> On 26/03/18 22:20, D
CPU always jumps into the reset handler in ARM-mode from the Trusted
Foundations firmware, hence make CPU to always jump into kernel in
ARM-mode regardless of the firmware presence to support Thumb2 kernel + TF
case.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 1
CPU isn't allowed to touch secure registers while running under secure
monitor. Hence skip applying CPU erratas in the reset handler if Trusted
Foundations firmware presents.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 27 +++
arch/arm/mach
Implement L2 cache initialization firmware callback that should be invoked
early in boot to enable cache HW.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/firmware
Add a helper that provides information about whether Trusted Foundations
firmware operations have been registered.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 5 +
arch/arm/include/asm/trusted_foundations.h | 7 +++
2 files changed, 12 insertions
On Tegra20/30 L2 cache must be initialized using firmware call if CPU
is running in insecure mode. Initialize L2 cache and setup the outer-cache
callbacks in early boot using the firmware API.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/tegra.c | 15 +++
1 file changed
), it is work-in-progress for now.
This patchset is partially based on the work done by Michał Mirosław [0].
Please review, thanks.
[0] https://www.spinics.net/lists/linux-tegra/msg30368.html
Dmitry Osipenko (5):
ARM: trusted_foundations: Implement L2 cache initialization callback
ARM
Hook up Memory Client reset of the Video Decoder to the decoders DT node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 09087b9c5e26
Hook up Memory Client reset of the Video Decoder to the decoders DT node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index
DMA requests must be blocked before resetting VDE HW, otherwise it is
possible to get a memory corruption or a machine hang. Use the reset
control provided by the Memory Controller to block DMA before resetting
the VDE HW.
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/tegra
On 20.05.2018 17:08, Russell King - ARM Linux wrote:
> On Sun, May 20, 2018 at 01:15:38PM +0300, Dmitry Osipenko wrote:
>> Implement L2 cache initialization firmware callback that should be invoked
>> early in boot to enable cache HW.
>>
>> Signed-off-by: Dmitry Os
On 20.05.2018 13:15, Dmitry Osipenko wrote:
> CPU isn't allowed to touch secure registers while running under secure
> monitor. Hence skip applying CPU erratas in the reset handler if Trusted
> Foundations firmware presents.
>
> Signed-off-by: Dmitry Osipenko
> ---
> arch
del
> ---
> drivers/iommu/tegra-gart.c | 26 ++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
> diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
> index 29bafc6..b62f790 100644
> --- a/
On 17.08.2017 16:52, Thierry Reding wrote:
> On Thu, Aug 17, 2017 at 01:21:52AM +0300, Dmitry Osipenko wrote:
>> Hello Joerg,
>>
>> On 10.08.2017 01:29, Joerg Roedel wrote:
>>> From: Joerg Roedel
>>>
>>> Add a struct iommu_device to each tegra-ga
20.
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
--
Dmitry
On 18.10.2017 00:13, Rob Herring wrote:
> On Tue, Oct 17, 2017 at 3:24 PM, Thierry Reding
> wrote:
>> On Tue, Oct 17, 2017 at 03:13:54PM -0500, Rob Herring wrote:
>> [...]
diff --git
a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-vde.txt
On 05.10.2017 23:33, Rob Herring wrote:
> On Tue, Sep 26, 2017 at 02:22:04AM +0300, Dmitry Osipenko wrote:
>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>> on Tegra20/30 SoC's.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> ...
to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Dmitry-Osipenko/staging-Introduce-NVIDIA-Tegra20-video-decoder-driver/20171006-101015
> config: ia64-allmodconfig (attached as .config)
> compiler: ia64-linux-gcc (GCC) 6.2.0
Stephen Warren and Dan Carpenter
- Implemented runtime PM
- Miscellaneous code cleanups
- Changed 'TODO'
- CC'd media maintainers for the review as per Greg K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (2):
staging
Add a device node for the video decoder engine found on Tegra20.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 7c85f97f72ea
Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports
decoding of CAVLC H.264 only.
Signed-off-by: Dmitry Osipenko
---
.../bindings/arm/tegra/nvidia,tegra20-vde.txt | 44 +
drivers/staging/Kconfig
On 11.10.2017 23:47, Nicolas Dufresne wrote:
> Le mercredi 11 octobre 2017 à 23:08 +0300, Dmitry Osipenko a écrit :
>> diff --git a/drivers/staging/tegra-vde/TODO b/drivers/staging/tegra-
>> vde/TODO
>> new file mode 100644
>> index ..e98bbc7b3c19
>&g
On 11.10.2017 11:22, Abbott Liu wrote:
> From: Andrey Ryabinin
>
> This patch initializes KASan shadow region's page table and memory.
> There are two stage for KASan initializing:
> 1. At early boot stage the whole shadow region is mapped to just
>one physical page (kasan_zero_page). It's
On 12.10.2017 11:49, Jon Hunter wrote:
>
> On 11/10/17 21:08, Dmitry Osipenko wrote:
>> Add a device node for the video decoder engine found on Tegra20.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> arch/arm/boot/dts/tegra20.dtsi | 17 +++
On 12.10.2017 13:57, Jon Hunter wrote:
>
> On 12/10/17 11:51, Dmitry Osipenko wrote:
>> On 12.10.2017 11:49, Jon Hunter wrote:
>>>
>>> On 11/10/17 21:08, Dmitry Osipenko wrote:
>>>> Add a device node for the video decoder engine found on Tegra20
Hello Vladimir,
On 12.10.2017 10:43, Vladimir Zapolskiy wrote:
> Hello Dmitry,
>
> On 10/11/2017 11:08 PM, Dmitry Osipenko wrote:
>> Add a device node for the video decoder engine found on Tegra20.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>&g
On 12.10.2017 16:45, Jon Hunter wrote:
>
> On 12/10/17 14:25, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Thu, Oct 12, 2017 at 03:06:17PM +0300, Dmitry Osipenko wrote:
>>> Hello Vladimir,
>>>
>>> On 12.10.2017
On 02.10.2017 20:05, Stephen Warren wrote:
> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:
>> On 29.09.2017 22:30, Stephen Warren wrote:
>>> On 09/27/2017 02:34 AM, Jon Hunter wrote:
>>>>
>>>> On 27/09/17 02:57, Dmitry Osipenko wrote:
&
On 03.10.2017 13:32, Jon Hunter wrote:
>
>
> On 03/10/17 00:02, Dmitry Osipenko wrote:
>> On 02.10.2017 20:05, Stephen Warren wrote:
>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:
>>>> On 29.09.2017 22:30, Stephen Warren wrote:
>>&g
On 03.10.2017 18:38, Stephen Warren wrote:
> On 10/03/2017 04:32 AM, Jon Hunter wrote:
>>
>>
>> On 03/10/17 00:02, Dmitry Osipenko wrote:
>>> On 02.10.2017 20:05, Stephen Warren wrote:
>>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote:
>>>>>
- Miscellaneous code cleanups
- Changed 'TODO'
- CC'd media maintainers for the review as per Greg K-H request,
v1 can be viewed at https://lkml.org/lkml/2017/9/25/606
Dmitry Osipenko (2):
staging: Introduce NVIDIA Tegra20 video decoder driver
ARM: dts: tegra20: Add video
Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of
video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports
decoding of CAVLC H.264 only.
Signed-off-by: Dmitry Osipenko
---
.../bindings/arm/tegra/nvidia,tegra20-vde.txt | 43 +
drivers/staging/Kconfig
Add a device node for the video decoder engine found on Tegra20.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 7c85f97f72ea
AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK
rate results in an increased DMA transfer rate.
Signed-off-by: Dmitry Osipenko
Acked-By: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra20.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
Tegra20 to utilize the 'common' APB DMA
clock gate definition.
Dmitry Osipenko (4):
clk: tegra: Add AHB DMA clock entry
clk: tegra: Correct parent of the APBDMA clock
clk: tegra20: Use common definition of APBDMA clock gate
clk: tegra20: Bump SCLK clock rate to 216MHz
drivers/clk
APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra-periph.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c
b
The APBDMA clock is defined in the common clock gates table that is used
by Tegra30+. Tegra20 can use it too, let's remove the custom definition
and use the common one.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra20.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions
AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that
driver for the AHB DMA controller could be implemented.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-id.h | 1 +
drivers/clk/tegra/clk-tegra-periph.c | 1 +
drivers/clk/tegra/clk-tegra20.c | 1
On 28.09.2017 10:23, Dan Carpenter wrote:
> On Thu, Sep 28, 2017 at 02:28:04AM +0300, Dmitry Osipenko wrote:
>>>> + if (is_baseline_profile)
>>>> + frame->aux_paddr = 0xF4DEAD00;
>>>
>>> The handling of is_baseline_profile is strange
On 28.09.2017 12:29, Vinod Koul wrote:
> On Tue, Sep 26, 2017 at 02:22:05AM +0300, Dmitry Osipenko wrote:
>
>> +config TEGRA20_AHB_DMA
>> +tristate "NVIDIA Tegra20 AHB DMA support"
>> +depends on ARCH_TEGRA
>
> Can we add COMPILE_TEST,
On 28.09.2017 12:31, Vinod Koul wrote:
> On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote:
>> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,
>> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master
>>
On 28.09.2017 12:29, Vinod Koul wrote:
>> +default:
>> +return -EINVAL;
>> +}
>> +
>> +ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
>> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
>> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_INTR_ENB;
>> +
>> +
On 28.09.2017 17:06, Dmitry Osipenko wrote:
> On 28.09.2017 12:29, Vinod Koul wrote:
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +
>>> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
>>>
On 28.09.2017 19:22, Vinod Koul wrote:
> On Thu, Sep 28, 2017 at 05:35:59PM +0300, Dmitry Osipenko wrote:
>> On 28.09.2017 17:06, Dmitry Osipenko wrote:
>>> On 28.09.2017 12:29, Vinod Koul wrote:
>>>>> + default:
>>>>> + return -EI
n submitting a job. Syncpoints are currently never unassigned from
> channels since that would require extra work and is unnecessary with
> the current channel allocation model.
>
> Signed-off-by: Mikko Perttunen
> ---
Reviewed-by: Dmitry Osipenko
Only one minor comment be
On 28.09.2017 15:50, Mikko Perttunen wrote:
> The disassembler for debug dumps was missing some newer host1x opcodes.
> Add disassembly support for these.
>
> Signed-off-by: Mikko Perttunen
> ---
Reviewed-by: Dmitry Osipenko
And for older Tegra's:
Tested-by: Dmitry Osipenko
;
> Signed-off-by: Mikko Perttunen
> ---
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
> drivers/gpu/drm/tegra/drm.c | 29 +++--
> 1 file changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm
On 29.09.2017 22:30, Stephen Warren wrote:
> On 09/27/2017 02:34 AM, Jon Hunter wrote:
>>
>> On 27/09/17 02:57, Dmitry Osipenko wrote:
>>> On 26.09.2017 17:50, Jon Hunter wrote:
>>>>
>>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>>&g
On 18.12.2017 15:22, Ming Lei wrote:
> When merging one bvec into segment, if the bvec is too big
> to merge, current policy is to move the whole bvec into another
> new segment.
>
> This patchset changes the policy into trying to maximize size of
> front segments, that means in above situation,
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