t;,
Maybe you should just say "spinlock not owned by us (actual owner is
%d)" so that this driver is agnostic to the processor it runs on?
+ __func__, lock_owner);
+ }
+
+ writel_relaxed(0, lock_addr);
+ smp_mb();
+}
Jeffrey Hugo
--
On 7/28/2017 12:09 PM, Jeffrey Hugo wrote:
In summary, our system is harmed by the code branch, and our analysis
indicates the branch has no benefit to the scheduler as it sits today,
we feel justified in removing it.
Ping?
Peter, did you find the additional information we provided useful
On 6/13/2017 8:32 AM, Jeffrey Hugo wrote:
On 6/7/2017 1:18 PM, Jeffrey Hugo wrote:
Co-authored-by: Austin Christ
Signed-off-by: Jeffrey Hugo
[V5]
-updated comment to explain the "why" behind the redo check
-fixed panic triggered from active_load_balance_cpu_stop()
[V4]
-restric
On 6/20/2017 5:46 PM, Paul E. McKenney wrote:
On Mon, Mar 27, 2017 at 11:17:11AM -0700, Paul E. McKenney wrote:
On Mon, Mar 27, 2017 at 12:02:27PM -0600, Jeffrey Hugo wrote:
Hi Paul.
Thanks for the quick reply.
On 3/26/2017 5:28 PM, Paul E. McKenney wrote:
On Sun, Mar 26, 2017 at 05:10:40PM
nce() path.
Patch 2 removes a branch that does not make sense with the current
load_balance() algorithm because it has no scenario where it benifits the
"group_imbalance" case in calculate_imbalance() and which causes problems
in systems with affined workloads and many idle or lightly loaded
st case, this can result in idle cpus.
Since the group imbalance path in calculate_imbalance() is at best a NOP
but otherwise harmful, remove it.
Signed-off-by: Austin Christ
Signed-off-by: Jeffrey Hugo
Tested-by: Tyler Baicar
---
kernel/sched/fair.c | 9 -
1 file changed, 9 deletions
removing cpus not in the current domain and the dst_cpu
from considertation, thus limiting the evaluation to valid remaining cpus
from which load might be migrated.
Signed-off-by: Austin Christ
Signed-off-by: Dietmar Eggemann
Signed-off-by: Jeffrey Hugo
Tested-by: Tyler Baicar
---
kernel
On 5/12/2017 11:23 AM, Peter Zijlstra wrote:
On Fri, May 12, 2017 at 11:01:37AM -0600, Jeffrey Hugo wrote:
Signed-off-by: Austin Christ
Signed-off-by: Dietmar Eggemann
Signed-off-by: Jeffrey Hugo
So per that Chain Austin wrote the patch, who handed it to Dietmar, who
handed it to you
On 5/12/2017 2:44 PM, Peter Zijlstra wrote:
On Fri, May 12, 2017 at 11:29:05AM -0600, Jeffrey Hugo wrote:
On 5/12/2017 11:23 AM, Peter Zijlstra wrote:
On Fri, May 12, 2017 at 11:01:37AM -0600, Jeffrey Hugo wrote:
Signed-off-by: Austin Christ
Signed-off-by: Dietmar Eggemann
Signed-off-by
On 5/12/2017 2:47 PM, Peter Zijlstra wrote:
On Fri, May 12, 2017 at 11:01:37AM -0600, Jeffrey Hugo wrote:
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index d711093..8f783ba 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -8219,8 +8219,19 @@ static int load_balance(int
ucky I saw this then.
I should be able to test within a week.
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
On 9/27/2018 8:19 AM, Timur Tabi wrote:
On 9/27/18 9:04 AM, Jeffrey Hugo wrote:
I guess its lucky I saw this then.
Did you not get this email:
https://lore.kernel.org/patchwork/patch/989545/#1173771
Apparently I did. I found it in my deleted items. I must have
accidentally done that
sysfs
for such caches, resulting in the information missing from utilities like
lstopo and lscpu, thus degrading the user experience.
Fixes: 2bd00bcd73e5 (ACPI/PPTT: Add Processor Properties Topology Table parsing)
Reported-by: Vijaya Kumar K
Signed-off-by: Jeffrey Hugo
---
drivers/acpi/pptt.c | 30
fo per Sudeep's suggestion
-Integrated the PPTT fix into existing PPTT code per Sudeep's suggestion
Jeffrey Hugo (2):
drivers: base: cacheinfo: Do not populate sysfs for unknown cache
types
ACPI/PPTT: Handle architecturally unknown cache types
drivers/acpi/pptt.c | 15
output.
lscpu: cannot open /sys/devices/system/cpu/cpu0/cache/index3/type: No such
file or directory
Suggested-by: Sudeep Holla
Signed-off-by: Jeffrey Hugo
Reviewed-by: Jeremy Linton
---
drivers/base/cacheinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/base/cacheinfo.c b
On 9/27/2018 8:04 AM, Jeffrey Hugo wrote:
On 9/27/2018 6:19 AM, Timur Tabi wrote:
On 9/27/18 1:51 AM, Stephen Boyd wrote:
Looks OK to me visually. I haven't tested it because I don't have access
to the locked down hardware anymore.
Same here. Please wait for Jeff Hugo to test
On 11/20/2018 4:11 AM, Sudeep Holla wrote:
On Thu, Nov 15, 2018 at 11:31:33AM -0700, Jeffrey Hugo wrote:
[...]
I was interested in testing these on QDF2400, an ARM64 platform, since this
series touches core ARM64 code and I'd hate to see a regression. However, I
can't figur
SubSystem
I couldn't find gcc_lpass_at_clk in the downstream 4.4 kernel...
LPASS = Low Power Audio Subsystem
Regards.
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
The SDC2 control pins are typically used to manage sleep.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998-pins.dtsi | 78 ++
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +
2 files changed, 80 insertions(+)
create mode 100644 arch/arm64/boot/dts
A short series to enable the SD card slot on the msm8998 MTP so that there
is some storage media to play with.
Jeffrey Hugo (4):
arm64: dts: qcom: msm8998: correct xo clock name
arm64: dts: qcom: msm8998: Add SDCC2
arm64: dts: qcom: msm8998: Add SDC2 control pins
arm64: dts: qcom: msm8998
#x27;t turn on clocks
for peripherals like SD, so init usually fails.
Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/
The externally accessible SD card slot on the MTP is driven by SDCC2.
Wire it up for use.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 13 +
arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm64
SDCC2 is typically used as the controller for an external SD card slot.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi
b/arch/arm64/boot/dts/qcom
t patches cause different conflicts of a variety of baselines I
attempted.
What are these intended to apply to?
Also, you might want to run them through checkpatch next time. There
are several whitespace errors.
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Te
On 11/15/2018 12:05 PM, Andy Gross wrote:
On Thu, Nov 15, 2018 at 10:18:11AM -0700, Jeffrey Hugo wrote:
The externally accessible SD card slot on the MTP is driven by SDCC2.
Wire it up for use.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 13
On 11/15/2018 12:16 PM, Bjorn Andersson wrote:
On Thu 15 Nov 09:18 PST 2018, Jeffrey Hugo wrote:
The SDC2 control pins are typically used to manage sleep.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998-pins.dtsi | 78 ++
Rather than adding a
SDCC2 is typically used as the controller for an external SD card slot.
Reviewed-by: Bjorn Andersson
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998
#x27;t turn on clocks
for peripherals like SD, so init usually fails.
Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support)
Reviewed-by: Bjorn Andersson
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
A short series to enable the SD card slot on the msm8998 MTP so that there
is some storage media to play with.
[v2]
-Added Bjorn's reviewed by tags
-Fixed white space issues in patch 4
-Refactored pin declarations
-Squashed patches 3 and 4
Jeffrey Hugo (3):
arm64: dts: qcom: msm8998: co
The externally accessible SD card slot on the MTP is driven by SDCC2.
Wire it up for use.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 65 +++
arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 +
2 files changed, 66 insertions(+)
diff
400.
Tested-by: Jeffrey Hugo
I did see that git am complained about patch #2 -
patch:103: space before tab in indent.
};
patch:114: space before tab in indent.
};
warning: 2 lines add whitespace errors.
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affili
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
drivers/clk/qcom/clk-smd-rpm.c | 62 ++
include/dt-bindings/clock/qcom
On 12/6/2018 2:55 PM, Stephen Boyd wrote:
Quoting Jeffrey Hugo (2018-12-06 13:11:06)
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
drivers/clk/qcom/clk
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v2
-fix compatible ordering nits per Stephen
.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
drivers/clk/qcom/clk-smd-rpm.c | 62
On 12/7/2018 3:30 AM, Marc Gonzalez wrote:
On 06/12/2018 23:11, Jeffrey Hugo wrote:
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v2
-fix compatible ordering nits per Stephen
.../devicetree/bindings/clock/qcom
On 12/7/2018 7:23 AM, Marc Gonzalez wrote:
On 06/12/2018 23:11, Jeffrey Hugo wrote:
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v2
-fix compatible ordering nits per Stephen
.../devicetree/bindings/clock/qcom
On 12/7/2018 8:10 AM, Jeffrey Hugo wrote:
On 12/7/2018 3:30 AM, Marc Gonzalez wrote:
On 06/12/2018 23:11, Jeffrey Hugo wrote:
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v2
-fix compatible ordering nits per
The offsets for the defined BCR reset registers does not match the hardware
documentation. Update the values to match the hardware documentation.
Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/gcc-msm8998.c | 38
On 12/3/2018 8:55 AM, Bjorn Andersson wrote:
On Mon 03 Dec 07:34 PST 2018, Jeffrey Hugo wrote:
The offsets for the defined BCR reset registers does not match the hardware
documentation. Update the values to match the hardware documentation.
Sorry for not spotting this before.
Fixes
The offsets for the defined BCR reset registers does not match the hardware
documentation. Update the values to match the hardware documentation.
Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo
Reviewed-by: Bjorn Andersson
---
v2
On 12/3/2018 10:02 AM, Stephen Boyd wrote:
Quoting Jeffrey Hugo (2018-12-03 08:08:46)
On 12/3/2018 8:55 AM, Bjorn Andersson wrote:
On Mon 03 Dec 07:34 PST 2018, Jeffrey Hugo wrote:
The offsets for the defined BCR reset registers does not match the hardware
documentation. Update the values
On 12/3/2018 10:52 AM, Stephen Boyd wrote:
Quoting Jeffrey Hugo (2018-12-03 09:19:20)
On 12/3/2018 10:02 AM, Stephen Boyd wrote:
Quoting Jeffrey Hugo (2018-12-03 08:08:46)
On 12/3/2018 8:55 AM, Bjorn Andersson wrote:
On Mon 03 Dec 07:34 PST 2018, Jeffrey Hugo wrote:
The offsets for the
The current list of defined resets is incomplete compared to what the
hardware implements. Enumerate the remaining resets according to the
hardware documentation.
Signed-off-by: Jeffrey Hugo
---
Based upon "Merge branch 'clk-qcom-8998-resets' into clk-next" to hopef
ur UIDs to be sequential 0-N numbering to workaround
the issue.
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
Jeff said it works, so I guess v5 will be good to go.
Yes posting that right now. It would be great if you folks can test
again on ACPI systems
Thanks
I might need a day, but I'll get to it.
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
gcc_lpass_trig_clk is not used downstream, therefore there is no reason to
expect it to be needed for clients. Lets remove it because messing with
the clock has been observed to cause Linux hangs when the qdss_clk is
initialized by rpmcc.
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/gcc
.
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/gcc-msm8998.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 4b75a09..b371308 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -2014,6 +2014,7
gcc_lpass_trig_clk is not used downstream, therefore there is no reason to
expect it to be needed for clients. Let's remove it because messing with
the clock has been observed to cause Linux hangs when the qdss_clk is
initialized by rpmcc.
Signed-off-by: Jeffrey Hugo
Reviewed-by: Marc Gon
On 12/13/2018 12:38 PM, Stephen Boyd wrote:
Quoting Jeffrey Hugo (2018-12-13 09:09:09)
gcc_lpass_trig_clk is not used downstream, therefore there is no reason to
expect it to be needed for clients. Let's remove it because messing with
the clock has been observed to cause Linux hangs whe
.
Signed-off-by: Jeffrey Hugo
---
v2:
-Switch to CLK_IS_CRITICAL and add comment per Stephen
drivers/clk/qcom/gcc-msm8998.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index f3c2ab4..b0c4b38 100644
--- a/drivers/clk/qcom/gcc
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v3
-Ensure Marc's hang was addressed by GCC fixes
-Renamed the bb clks to ln_bb to match the schematics
v2
-fix compatible ordering nits per Stephen
.../devic
On 12/17/2018 5:21 PM, Jeffrey Hugo wrote:
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v3
-Ensure Marc's hang was addressed by GCC fixes
-Renamed the bb clks to ln_bb to match the schematics
v2
-fix compa
CI to reliably support "fast" cards such as SDR104.
Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/gcc-msm8998.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/drive
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v4
-Fix compile issue
v3
-Ensure Marc's hang was addressed by GCC fixes
-Renamed the bb clks to ln_bb to match the schematics
v2
-fix compatible ordering nit
rates of a
selected rcg in a convenient format.
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/clk-rcg2.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 6e3bd19..e4b1d35 100644
--- a/drivers/cl
l21 is used as sdcard vmmc, and needs the load increased to prevent
voltage drop issues with some sdcards. This addresses -84 errors seen
during sdcard init with SDR104 cards.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 2 ++
1 file changed, 2 insertions
msm8998 has a dozen i2c controllers which can be used to connect to board
specific peripherals. Enumerate the controllers so that boards can wire
up as needed.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 180 ++
1 file changed, 180
On 12/7/2018 8:13 AM, Jeffrey Hugo wrote:
On 12/7/2018 7:23 AM, Marc Gonzalez wrote:
On 06/12/2018 23:11, Jeffrey Hugo wrote:
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: Jeffrey Hugo
---
v2
-fix compatible ordering nits per
commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets")
missed two USB2 resets. Add them.
Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets")
Signed-off-by: Jeffrey Hugo
---
Sorry, noticed this when working on USB. I double checked the docu
On 1/7/2019 11:18 AM, Jack Pham wrote:
Hi Jeff,
Spotted a typo below:
On Fri, Jan 04, 2019 at 09:50:29AM -0700, Jeffrey Hugo wrote:
MSM8998 contains one QUSB2 PHY which is very similar to the existing
sdm845 support.
Signed-off-by: Jeffrey Hugo
---
.../devicetree/bindings/phy/qcom-qusb2
This series provides basic USB support for MSM8998. Currently missing is
wiring up the Type-C detection logic so that the controller can correctly
switch between host and peripheral modes. Work to implement that is
ongoing, and expected to appear soon in followup patches.
Jeffrey Hugo (6
result, skip the checks to avoid the troubling situation.
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/gcc-msm8998.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 42de947..1a1806a 100644
--- a/drivers
The usb30_master_clk supports a 60Mhz frequency, but that is missing from
the table of supported frequencies. Add it.
Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/gcc-msm8998.c | 1 +
1 file changed, 1 insertion
MSM8998 contains one QUSB2 PHY which is very similar to the existing
sdm845 support.
Signed-off-by: Jeffrey Hugo
---
.../devicetree/bindings/phy/qcom-qusb2-phy.txt | 1 +
drivers/phy/qualcomm/phy-qcom-qusb2.c | 41 ++
2 files changed, 42 insertions(+)
diff
MSM8998 contains a single QMP v3 USB3 phy similar to the existing sdm845
support, however MSM8998 does not have display port (DP) support.
Signed-off-by: Jeffrey Hugo
---
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 5 +
drivers/phy/qualcomm/phy-qcom-qmp.c| 142
Add a MSM8998 specific DT compatible so that we can properly bind to the
device and enable the USB controller.
Signed-off-by: Jeffrey Hugo
---
Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 1 +
drivers/usb/dwc3/dwc3-qcom.c| 1 +
2 files changed, 2 insertions
Add nodes for USB and related PHYs.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 22
arch/arm64/boot/dts/qcom/msm8998.dtsi | 90 +++
2 files changed, 112 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
On 10/5/2018 10:54 AM, Timur Tabi wrote:
On 10/05/2018 11:17 AM, Jeffrey Hugo wrote:>
Looks like the driver is initing just fine to me. Is setting up the
jumpers and running gpio-test warranted?
Well, that test only makes sure that input/output is actually working
on the hardware level,
Seems like the majority of the other qcom pinctrl
bindings docs mention that gpio-reserved-ranges is optional.
In any case,
Reviewed-by: Jeffrey Hugo
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
On 10/17/2018 4:05 PM, Andrew Morton wrote:
On Wed, 17 Oct 2018 16:03:10 +0200 Anders Roxell
wrote:
Cc: Arnd Bergmann
Co-developed-by: Arnd Bergmann
Signed-off-by: Anders Roxell
This should have Arnd's Signed-off-by: as well.
I'm just interested to know, why?
--
Jeffrey Hug
On 10/17/2018 4:32 PM, Andrew Morton wrote:
On Wed, 17 Oct 2018 16:21:08 -0600 Jeffrey Hugo wrote:
On 10/17/2018 4:05 PM, Andrew Morton wrote:
On Wed, 17 Oct 2018 16:03:10 +0200 Anders Roxell
wrote:
Cc: Arnd Bergmann
Co-developed-by: Arnd Bergmann
Signed-off-by: Anders Roxell
This
output.
lscpu: cannot open /sys/devices/system/cpu/cpu0/cache/index3/type: No such
file or directory
Suggested-by: Sudeep Holla
Signed-off-by: Jeffrey Hugo
Reviewed-by: Jeremy Linton
Reviewed-by: Sudeep Holla
---
drivers/base/cacheinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a
sysfs
for such caches, resulting in the information missing from utilities like
lstopo and lscpu, thus degrading the user experience.
Fixes: 2bd00bcd73e5 (ACPI/PPTT: Add Processor Properties Topology Table parsing)
Reported-by: Vijaya Kumar K
Signed-off-by: Jeffrey Hugo
Reviewed-by: Sudeep Holla
BUTES
[v3]
-removed valid flag in PPTT
-Added Jeremy Linton's reviewed-by
[v2]
-Updated cacheinfo per Sudeep's suggestion
-Integrated the PPTT fix into existing PPTT code per Sudeep's suggestion
Jeffrey Hugo (2):
drivers: base: cacheinfo: Do not populate sysfs for unknown cache
On 10/2/2018 9:21 AM, Jeffrey Hugo wrote:
On 10/2/2018 8:08 AM, Ricardo Ribalda Delgado wrote:
Current code assumes that the direction is input if direction_input
function is set.
This might not be the case on GPIOs with programmable direction.
Signed-off-by: Ricardo Ribalda Delgado
I&#x
On 10/5/2018 12:52 AM, Ricardo Ribalda Delgado wrote:
Hi
On Fri, Oct 5, 2018 at 12:26 AM Jeffrey Hugo wrote:
On 10/2/2018 9:21 AM, Jeffrey Hugo wrote:
On 10/2/2018 8:08 AM, Ricardo Ribalda Delgado wrote:
Current code assumes that the direction is input if direction_input
function is set
7.433218] gpiochip_setup_dev: registered GPIOs 362 to 511 on
device: gpiochip0 (QCOM8002:00)
[7.433222] gpio gpiochip0: (QCOM8002:00): created GPIO range 0->149
==> QCOM8002:00 PIN 0->149
Looks like the driver is initing just fine to me. Is setting up the
jumpers and runni
On 9/17/2018 10:17 AM, Sudeep Holla wrote:
On 14/09/18 17:28, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural mechanisms (ie
system registers), but its type might be specified in the PPTT. In this
case, we should populate the type of the cache, rather than
On 10/13/2023 3:52 AM, Krishna chaitanya chundru wrote:
This change adds ftrace support for following functions which
helps in debugging the issues when there is Channel state & MHI
state change and also when we receive data and control events:
1. mhi_intvec_threaded_handler
2. mhi_process_data_e
On 10/23/2023 1:11 AM, Krishna Chaitanya Chundru wrote:
On 10/20/2023 8:33 PM, Jeffrey Hugo wrote:
On 10/13/2023 3:52 AM, Krishna chaitanya chundru wrote:
This change adds ftrace support for following functions which
helps in debugging the issues when there is Channel state & MHI
state ch
ents to drivers/bus/mhi/host/ so
that
- we can include driver header files.
- Use macros directly in the trace events as suggested Jeffrey Hugo.
- Reorder the structure in the events as suggested by steve to avoid holes in
the buffer.
- removed the mhi_to_physical function as this can give secu
On 2/16/2021 10:36 AM, Bhaumik Bhatt wrote:
On 2021-02-15 11:32 PM, Manivannan Sadhasivam wrote:
On Fri, Feb 12, 2021 at 05:40:14PM -0700, Jeffrey Hugo wrote:
The intvec handler stores the caches ee in a local variable for use in
processing the intvec. When determining if a syserr is a fatal
From: Fan Wu
Currently ENOMEM is returned when MHI ring is full. This error code is
very misleading. Change to EBUSY instead.
Signed-off-by: Fan Wu
Signed-off-by: Jeffrey Hugo
---
drivers/bus/mhi/core/main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/bus/mhi
e the device hits the ready state before the host
completes its reset processing.
Signed-off-by: Jeffrey Hugo
---
drivers/bus/mhi/core/pm.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index ef
On 2/16/2021 1:22 PM, Bhaumik Bhatt wrote:
On 2021-02-16 10:48 AM, Jeffrey Hugo wrote:
From: Fan Wu
Currently ENOMEM is returned when MHI ring is full. This error code is
very misleading. Change to EBUSY instead.
Signed-off-by: Fan Wu
Signed-off-by: Jeffrey Hugo
---
drivers/bus/mhi/core
From: Fan Wu
Currently ENOMEM is returned when MHI ring is full. This error code is
very misleading. Change to EAGAIN instead.
Signed-off-by: Fan Wu
Signed-off-by: Jeffrey Hugo
---
v2: Change from EBUSY to EAGAIN
drivers/bus/mhi/core/main.c | 2 +-
1 file changed, 1 insertion(+), 1
: Jeffrey Hugo
---
drivers/bus/mhi/core/pm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index 56ba3ab..dc69074 100644
--- a/drivers/bus/mhi/core/pm.c
+++ b/drivers/bus/mhi/core/pm.c
@@ -1144,6 +1144,7 @@ int mhi_async_power_up(struct
_region by looking it up at init time? It does not seem like it
would be possible to support that with this binding.
--
Jeffrey Hugo
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
--
To unsubsc
mem_remove,
+ .driver = {
+ .name = "qcom_smem",
+ .of_match_table = qcom_smem_of_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+static int __init qcom_smem_init(void)
+{
+ return platform_driver_register(&qcom_smem_driv
ecessary, and considering that such a calculation would
run for every interrupt, I'd like to avoid the extra cost.
--
Jeffrey Hugo
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum, a Linux Foundation Collaborative Project
--
To unsubscrib
hwspinlocks". Would to please determine which of the
two labels you most prefer, and change things so that label is used in
both the description and the example? Thanks
+ };
--
Jeffrey Hugo
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member
n it working? An
example of the API, how it would be used, future usecases that might be
covered by it, etc. That would give us specifics we can discuss and
weigh the merits of.
Thanks.
--
Jeffrey Hugo
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member
member for hwspinlock_device. The hwcaps represents the
Technically you added it to the hwspinlock struct, not
hwspinlock_device. Mentioning that the hwcaps member was added to
hwspinlock_device in the description here may be slightly confusing.
--
Jeffrey Hugo
Qualcomm Innovation Center, Inc.
Th
ribe from this list: send the line "unsubscribe linux-efi" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
: e1a58320a38d ("x86/mm: Warn on W^X mappings")
Signed-off-by: Jeffrey Hugo
---
v1:
-was "arm64: mm: Fix false positives in W+X checking" (see [1])
-moved to common code based on review and confirmation of issue on x86
[1] http://lists.infradead.org/pipermail/linux-arm-kern
On 4/28/2018 12:14 AM, Ingo Molnar wrote:
* Jeffrey Hugo wrote:
load_module() creates W+X mappings via __vmalloc_node_range() (from
layout_and_allocate()->move_module()->module_alloc()) by using
PAGE_KERNEL_EXEC. These mappings are later cleaned up via
"call_rcu_sched(&am
: e1a58320a38d ("x86/mm: Warn on W^X mappings")
Signed-off-by: Jeffrey Hugo
Acked-by: Kees Cook
Acked-by: Ingo Molnar
Acked-by: Will Deacon
---
v3:
-added comment to module code to establish matching connection
-added acks by Kees, Ingo, and Will
v2:
-was "arm64: mm: Fix fa
On 4/30/2018 12:40 PM, Kees Cook wrote:
On Mon, Apr 30, 2018 at 10:19 AM, Laura Abbott wrote:
On 04/30/2018 08:59 AM, Jeffrey Hugo wrote:
load_module() creates W+X mappings via __vmalloc_node_range() (from
layout_and_allocate()->move_module()->module_alloc()) by using
PAGE_KERNE
ll. All clocks from old and new (ie
8998 mmcc rebased onto this) drivers end up as orphans.
Is there some data I can provide to help you figure out the issue?
Cc: Miquel Raynal
Cc: Jerome Brunet
Cc: Russell King
Cc: Michael Turquette
Cc: Jeffrey Hugo
Cc: Chen-Yu Tsai
Signed-of
On Thu, Apr 18, 2019 at 3:51 AM Hans de Goede wrote:
>
> Hi,
>
> On 18-04-19 11:34, Benjamin Tissoires wrote:
> > On Mon, Apr 15, 2019 at 6:11 PM Jeffrey Hugo
> > wrote:
> >>
> >> Following up on commit 2bafa1e96254 ("HID: quirks: Fix key
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