On 13/11/17 21:19, Brian Norris wrote:
> + others
>
> On Mon, Nov 13, 2017 at 09:05:39PM +0000, Jon Hunter wrote:
>> On the Tegra124 Nyan-Big chromebook the very first SPI message sent to
>> the EC is failing.
>>
>> The Tegra SPI driver configures the SPI chi
Hi Shawn,
On 26/09/17 16:40, Jon Hunter wrote:
> On 26/09/17 00:15, Shawn N wrote:
...
>> From: Shawn Nematbakhsh
>> Date: Mon, 25 Sep 2017 14:32:38 -0700
>> Subject: [PATCH] mfd: cros ec: spi: Fix "in progress" error signaling
>>
>> For host command
-DMA. This version is no longer
derived from the APB-DMA driver and has been updated to use the
virt-dma helpers.
V2 changes:
- Re-worked device-tree binding
[0] https://lkml.org/lkml/2015/8/18/237
Jon Hunter (2):
Documentation: DT: Add binding documentation for NVIDIA ADMA
dmaengine: tegra-adma
Add device-tree binding documentation for the Tegra210 Audio DMA
controller.
Signed-off-by: Jon Hunter
---
.../devicetree/bindings/dma/tegra210-adma.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt
+
+ return ret;
+}
+
+static int tegra_adma_remove(struct platform_device *pdev)
+{
+ struct tegra_adma *tdma = platform_get_drvdata(pdev);
+ struct tegra_adma_chan *tdc;
+ int i;
+
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ for (i = 0; i < tdma-&
On 05/10/15 14:12, Mark Rutland wrote:
> On Mon, Oct 05, 2015 at 01:10:06PM +0100, Jon Hunter wrote:
>> Add device-tree binding documentation for the Tegra210 Audio DMA
>> controller.
>>
>> Signed-off-by: Jon Hunter
>> ---
>> .../devicetree/b
On 06/10/15 10:32, Arnd Bergmann wrote:
> On Monday 05 October 2015 13:10:07 Jon Hunter wrote:
>> Add support for the Tegra210 Audio DMA controller that is used for
>> transferring data between system memory and the Audio sub-system.
>> The driver only supports cyclic tran
On 07/10/15 00:04, Stephen Warren wrote:
> On 10/05/2015 06:10 AM, Jon Hunter wrote:
>> Add device-tree binding documentation for the Tegra210 Audio DMA
>> controller.
>
>> diff --git a/Documentation/devicetree/bindings/dma/tegra210-adma.txt
>> b/Documentation/de
On 06/10/15 23:57, Stephen Warren wrote:
> On 10/06/2015 03:16 AM, Jon Hunter wrote:
>>
>> On 05/10/15 14:12, Mark Rutland wrote:
>>> On Mon, Oct 05, 2015 at 01:10:06PM +0100, Jon Hunter wrote:
>>>> Add device-tree binding documentation for the Tegra210 Audio D
On 07/10/15 17:09, Stephen Warren wrote:
> On 10/07/2015 02:43 AM, Jon Hunter wrote:
>>
>> On 07/10/15 00:04, Stephen Warren wrote:
>>> On 10/05/2015 06:10 AM, Jon Hunter wrote:
>>>> Add device-tree binding documentation for the Tegra210 Audio DMA
&g
On 25/08/15 23:46, Rafael J. Wysocki wrote:
> On 8/25/2015 11:37 AM, Jon Hunter wrote:
[snip]
>> Vinod, thinking about this some more, I am wondering if it is just
>> better to get rid of the suspend/resume callbacks and simply handling
>> the state in the runtime suspen
On 09/10/15 16:26, Stephen Warren wrote:
> On 10/09/2015 04:20 AM, Jon Hunter wrote:
>>
>> On 08/10/15 15:27, Stephen Warren wrote:
>>> On 10/08/2015 03:58 AM, Jon Hunter wrote:
>>
>> [snip]
>>
>>>> That's fine. From my perspective I do
On 12/10/15 18:51, Stephen Warren wrote:
> On 10/12/2015 07:55 AM, Jon Hunter wrote:
>>
>> On 09/10/15 16:26, Stephen Warren wrote:
>>> On 10/09/2015 04:20 AM, Jon Hunter wrote:
>>>>
>>>> On 08/10/15 15:27, Stephen Warren wrote:
>>>>
On 14/10/15 12:27, Vinod Koul wrote:
> On Mon, Oct 05, 2015 at 01:10:07PM +0100, Jon Hunter wrote:
>
>> +static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
>> +dma_cookie_t cookie,
>> +
On 04/09/15 02:14, Grant Grundler wrote:
> On Thu, Sep 3, 2015 at 8:10 AM, Jon Hunter wrote:
>
>>
>> On 02/09/15 23:08, Grant Grundler wrote:
>>> [resending text-only]
>>>
>>> On Wed, Sep 2, 2015 at 3:07 PM, Grant Grundler
>> wrote:
&
Hi Ulf,
On 09/09/15 13:42, Ulf Hansson wrote:
> On 3 September 2015 at 17:08, Jon Hunter wrote:
>> Hi Olof,
>>
>> On 02/09/15 19:28, Olof Johansson wrote:
>>> Hi,
>>>
>>> On Wed, Sep 2, 2015 at 7:21 AM, Jon Hunter wrote:
>>>> From:
commands to multi commands. Updated patch based upon
feedback review comments received. Updated commit message ]
Signed-off-by: Jon Hunter
---
drivers/mmc/card/block.c | 198 -
include/uapi/linux/mmc/ioctl.h | 17 +++-
2 files changed, 170 insertions
On 09/09/15 16:56, Arnd Bergmann wrote:
> On Wednesday 09 September 2015 16:06:01 Jon Hunter wrote:
>> +
>> + idata = kcalloc(mcci.num_of_cmds, sizeof(*idata), GFP_KERNEL);
>> + if (!idata) {
>> + err = -ENOMEM;
>
Add device-tree binding documentation for the Tegra210 Audio DMA
controller.
Signed-off-by: Jon Hunter
---
.../devicetree/bindings/dma/tegra210-adma.txt | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt
/237
Jon Hunter (2):
Documentation: DT: Add binding documentation for NVIDIA ADMA
dmaengine: tegra-adma: Add support for Tegra210 ADMA
.../devicetree/bindings/dma/tegra210-adma.txt | 50 ++
drivers/dma/Kconfig| 13 +
drivers/dma/Makefile
rm_device *pdev)
+{
+ struct tegra_adma *tdma = platform_get_drvdata(pdev);
+ struct tegra_adma_chan *tdc;
+ int i;
+
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ for (i = 0; i < tdma->nr_channels; ++i) {
+ tdc = &tdma->channels[i];
+
The tegra20-apb-dma driver currently uses the flag GFP_ATOMIC when
allocating memory for structures used in conjunction with the DMA
descriptors. It is preferred that dmaengine drivers use GFP_NOWAIT
instead and so the emergency memory pool will not be used by these
drivers.
Signed-off-by: Jon
Newer tegra devices have a separate word count register per channel that
contains the number of words to be transferred. This register is not
saved or restored by the suspend/resume helpers for these newer devices
and so ensure that it is.
Signed-off-by: Jon Hunter
---
drivers/dma/tegra20-apb
On driver removal, before killing any tasklets, ensure that the channel
interrupts are disabled so that the tasklet will not try to run during
or after the removal of the driver.
Signed-off-by: Jon Hunter
---
drivers/dma/tegra20-apb-dma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
A few updates for the tegra-apb driver. Build tested for ARM and ARM64 and
the driver has been tested on tegra124 with the HSUART driver that uses
DMA.
Jon Hunter (6):
dmaengine: tegra-apb: Correct runtime-pm usage
dmaengine: tegra-apb: Use dev_get_drvdata()
dmaengine: tegra-apb: Save and
Currently the tegra-apb DMA driver suspend/resume helpers, save and
restore the registers for all channels regardless of whether they are
in use or not. Change this so that only channels that have been
allocated and configured are saved and restored.
Signed-off-by: Jon Hunter
---
drivers/dma
In the tegra_dma_runtime_suspend/resume functions, the pdev structure
is not needed, and so just call dev_get_drvdata() to get the device
data structure.
Signed-off-by: Jon Hunter
---
drivers/dma/tegra20-apb-dma.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers
-off-by: Jon Hunter
---
drivers/dma/tegra20-apb-dma.c | 50 ---
1 file changed, 18 insertions(+), 32 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index c8f79dcaaee8..fe4a006adeb0 100644
--- a/drivers/dma/tegra20
0
pcie2 x1 (option2): pcie2
usb3 port 0:pcie0
usb3 port 1 (option 1): pcie1
usb3 port 1 (option 2): sata0
sata: sata0
Signed-off-by: Jon Hunter
---
drivers/pinctrl/pinctrl-tegra-xusb.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/pinctrl/pin
On 16/10/15 09:53, Lars-Peter Clausen wrote:
> On 10/16/2015 10:25 AM, Jon Hunter wrote:
>> On driver removal, before killing any tasklets, ensure that the channel
>> interrupts are disabled so that the tasklet will not try to run during
>> or after the removal of the driver
On 16/10/15 11:40, Lars-Peter Clausen wrote:
> On 10/16/2015 11:29 AM, Jon Hunter wrote:
>>
>> On 16/10/15 09:53, Lars-Peter Clausen wrote:
>>> On 10/16/2015 10:25 AM, Jon Hunter wrote:
>>>> On driver removal, before killing any tasklets, ensure that the cha
the device
atomically as proposed here. These combo commands are simple array of
the existing mmc_ioc_cmd structure.
Signed-off-by: Seshagiri Holi
[ jonath...@nvidia.com: Rebased on linux-next from v3.18 and updated
commit message ]
Signed-off-by: Jon Hunter
---
I am not sure if there are
Hi Olof,
On 02/09/15 19:28, Olof Johansson wrote:
> Hi,
>
> On Wed, Sep 2, 2015 at 7:21 AM, Jon Hunter wrote:
>> From: Seshagiri Holi
>>
>> Certain eMMC devices allow vendor specific device information to be read
>> via a sequence of vendor commands. These ven
On 02/09/15 23:08, Grant Grundler wrote:
> [resending text-only]
>
> On Wed, Sep 2, 2015 at 3:07 PM, Grant Grundler wrote:
>>
>>
>> On Wed, Sep 2, 2015 at 11:28 AM, Olof Johansson wrote:
>> ...
+/**
+ * struct mmc_ioc_combo_cmd - combo command information
+ * @num_of_cmds: number
On 16/10/15 17:09, Stephen Warren wrote:
> On 10/16/2015 01:35 AM, Jon Hunter wrote:
>> Add device-tree binding documentation for the Tegra210 Audio DMA
>> controller.
>
>> diff --git a/Documentation/devicetree/bindings/dma/tegra210-adma.txt
>> b/Documentation/de
On 16/10/15 17:17, Stephen Warren wrote:
> On 10/16/2015 03:24 AM, Jon Hunter wrote:
>> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the
>> Tegra124
>> documentation implies that all functions (pcie, usb3 and sata) can be
>> muxed onto to all lanes (pci
On 19/10/15 17:33, Stephen Warren wrote:
> On 10/19/2015 05:22 AM, Jon Hunter wrote:
>>
>> On 16/10/15 17:09, Stephen Warren wrote:
>>> On 10/16/2015 01:35 AM, Jon Hunter wrote:
>>>> Add device-tree binding documentation for the Tegra210 Audio DMA
&g
On 20/10/15 00:30, Stephen Warren wrote:
> From: Stephen Warren
>
> Convert the binding to provide a PHY per lane, rather than a PHY per
> "pad" block in the hardware. This will allow the driver to easily know
> which lanes are used by clients, and thus only enable those lanes, and
> generally b
On 16/10/15 17:17, Stephen Warren wrote:
> On 10/16/2015 03:24 AM, Jon Hunter wrote:
>> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the
>> Tegra124
>> documentation implies that all functions (pcie, usb3 and sata) can be
>> muxed onto to all lanes (pci
On 20/10/15 17:08, Stephen Warren wrote:
> On 10/20/2015 05:28 AM, Jon Hunter wrote:
>>
>> On 16/10/15 17:17, Stephen Warren wrote:
>>> On 10/16/2015 03:24 AM, Jon Hunter wrote:
>>>> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the
>>&
On 20/10/15 19:36, Stephen Warren wrote:
> On 10/20/2015 12:02 PM, Jon Hunter wrote:
>>
>> On 20/10/15 17:08, Stephen Warren wrote:
>>> On 10/20/2015 05:28 AM, Jon Hunter wrote:
>>>>
>>>> On 16/10/15 17:17, Stephen Warren wrote:
>>&g
On 27/10/15 02:10, Vinod Koul wrote:
> On Fri, Oct 16, 2015 at 08:35:19AM +0100, Jon Hunter wrote:
>> +static inline void tdma_ch_write(struct tegra_adma_chan *tdc,
>> +u32 reg, u32 val)
>
> Coding style issue here
Yes will correct.
>> +static int tegr
g
the CPU DAI drivers, because this will happen later with this change.
Signed-off-by: Jon Hunter
---
It is not 100% clear to me if there are any downsides to this approach
but I am looking to find away to avoid calling dapm_power_widgets() so
many times in the suspend path when there are man
pts supported by the HSP instance minus one.
> Users of this binding MUST look up entries in the interrupt property
> by name, using this interrupt-names property to do so.
> - interrupts
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
mailbox subsystem, and the specifiers implemented by the relevant
> +provider(s):
> +
> +- .../mailbox/mailbox.txt
> +- .../mailbox/nvidia,tegra186-hsp.txt
> +
> +Example bindings:
> +-
> +
> +tcu: tcu {
> + compatible = "nvidia,tegra194-tcu";
> + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
> + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
> + mbox-names = "rx", "tx";
> +};
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
hsp->mbox.txdone_poll = false;
> - hsp->mbox.ops = &tegra_hsp_doorbell_ops;
> + hsp->mbox.ops = &tegra_hsp_ops;
>
> hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans,
> sizeof(*hsp->mbox.chans),
> @@ -427,11 +465,12 @@ static int tegra_hsp_probe(struct platform_device *pdev)
> return err;
> }
>
> - err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq,
> -IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp);
> + err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
> +tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
> +dev_name(&pdev->dev), hsp);
> if (err < 0) {
> - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
> - hsp->irq, err);
> + dev_err(&pdev->dev, "failed to request doorbell IRQ#%u: %d\n",
> + hsp->doorbell_irq, err);
> return err;
> }
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
to request doorbell IRQ#%u: %d\n",
> + hsp->doorbell_irq, err);
> + goto unregister_mbox_controller;
> + }
> + }
> +
> + if (hsp->shared_irq) {
> + err = devm_request_irq(&pdev->dev, hsp->shared_irq,
> +tegra_hsp_shared_irq, 0,
> +dev_name(&pdev->dev), hsp);
> + if (err < 0) {
> + dev_err(&pdev->dev,
> + "failed to request shared0 IRQ%u: %d\n",
> + hsp->shared_irq, err);
> + goto unregister_mbox_controller;
> + }
> }
>
> return 0;
> +
> +unregister_mbox_controller:
> + mbox_controller_unregister(&hsp->mbox);
> +remove_doorbells:
> + if (hsp->doorbell_irq)
> + tegra_hsp_remove_doorbells(hsp);
This bit looks like it should have been a separate patch to fix the
clean-up if probe fails. However, unless there is a reason to re-spin
the series, probably OK.
> +
> + return err;
> }
>
> static int tegra_hsp_remove(struct platform_device *pdev)
> @@ -482,7 +651,8 @@ static int tegra_hsp_remove(struct platform_device *pdev)
> struct tegra_hsp *hsp = platform_get_drvdata(pdev);
>
> mbox_controller_unregister(&hsp->mbox);
> - tegra_hsp_remove_doorbells(hsp);
> + if (hsp->doorbell_irq)
> + tegra_hsp_remove_doorbells(hsp);
>
> return 0;
> }
>
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 20/06/18 13:20, Mikko Perttunen wrote:
> The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
> multiplexing multiple "virtual UARTs" into a single hardware serial
> port. The TCU is the primary serial port on Tegra194 devices.
>
> Add a TCU driver utilizing the mailbox fram
};
>
> @@ -382,6 +403,13 @@
> };
> };
>
> + tcu: tcu {
> + compatible = "nvidia,tegra194-tcu";
> + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
> + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
> + mbox-names = "rx", "tx";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts =
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 03/08/18 17:36, Mark Brown wrote:
> On Fri, Aug 03, 2018 at 01:57:05PM +0100, Jon Hunter wrote:
>
>> For soundcards that have several DAI links and many DAPM widgets the
>> time taken for snd_soc_suspend to execute has been observed to be
>> several milliseconds. T
of_node_put(np_stcc);
> if (IS_ERR_OR_NULL(tcd)) {
> dev_err(dev,
> "throttle-cfg: %s: failed to register cooling
> device\n",
>
Thanks!
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
Adding linux-tegra ...
On 13/08/18 19:30, Jon Hunter wrote:
>
> On 09/08/18 14:40, zhong jiang wrote:
>> Device node iterators will get the return node. Meawhile, It is
>> also put the previous device node. An explicit put will cause
>> a double put.
>>
ra_alc5632_remove(struct platform_device
> *pdev)
>
> tegra_asoc_utils_fini(&machine->util_data);
>
> + of_node_put(tegra_alc5632_dai.cpu_of_node);
> + tegra_alc5632_dai.cpu_of_node = NULL;
> + tegra_alc5632_dai.platform_of_node = NULL;
> + of_node_put(tegra_alc5632_dai.codec_of_node);
> + tegra_alc5632_dai.codec_of_node = NULL;
> +
> return 0;
> }
Thanks!
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
L_TOTAL_SLOT_SHIFT)
> +#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK
> (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
> TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT)
>
> /* TDM mode slot enable bitmask */
> #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8
Thanks for fixing.
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 27/07/18 13:59, Jorge Sanjuan wrote:
> From: Edward Cragg
>
> Add a callback to configure TDM settings for the Tegra30
> I2S ASoC 'platform' driver.
>
> Signed-off-by: Ben Dooks
> Signed-off-by: Edward Cragg
> [jorge.sanj...@codethink.co.uk: Style fixes]
> Signed-off-by: Jorge Sanjuan
>
On 27/07/18 13:59, Jorge Sanjuan wrote:
> From: Edward Cragg
>
> The CIF configuration and clock setting is currently hard coded for 2
> channels. Since the hardware is capable of supporting 1-8 channels add
> support for reading the channel count from the supplied parameters to
> allow for bet
On 30/07/18 11:18, Mark Brown wrote:
> On Mon, Jul 30, 2018 at 10:31:16AM +0100, Jon Hunter wrote:
>
>> It can be quite common for the fsync-width for DSP modes to be a single
>> clock and so
>> I am not sure that is makes sense to set this here always to the slot widt
On 30/07/18 15:04, Jon Hunter wrote:
> I still do not like configuring the fsync width in this function. The
> fsync width needs to be configured for both DSP modes and normal I2S
> modes and so it seems it would be more appropriate to do this in the
> hw_params function for this d
LEVEL_HIGH))
> irq_set_handler_locked(d, handle_level_irq);
> else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thanks for reporting this. I am seeing this as well on Tegra20 Ventana
and Tegra30 Cardhu looking at the boot log. Given that gpiochip_lock_as_irq
is checking the direction, the above fix looks good to me. So ...
Acked-by: Jon Hunter
Tested-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 19/07/18 14:24, Dmitry Osipenko wrote:
> This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
> timings for RAM code 0 registered" warning message during of kernels
> boot-up on Tegra20.
Looking at the tegra20-emc.txt bindings doc [0], the 'nvidia,ram-code'
property is also v
On 19/07/18 16:38, Dmitry Osipenko wrote:
> On Thursday, 19 July 2018 18:30:48 MSK Jon Hunter wrote:
>> On 19/07/18 14:24, Dmitry Osipenko wrote:
>>> This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
>>> timings for RAM code 0 registered&qu
On 20/07/18 08:52, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> This fixes a spelling mistake.
>
> Signed-off-by: Marcel Ziswiler
>
> ---
>
> Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
7 +44,7 @@ Optional subnode-properties:
> - nvidia,tristate: Integer.
> 0: drive, 1: tristate.
> - nvidia,enable-input: Integer. Enable the pin's input path.
> -enable :TEGRA_PIN_ENABLE0 and
> +enable :TEGRA_PIN_ENABLE and
> disable or output only: TEGRA_PIN_DISABLE.
> - nvidia,open-drain: Integer.
> enable: TEGRA_PIN_ENABLE.
Acked-by: Jon Hunter
Thanks!
Jon
--
nvpublic
Adding Linus ...
On 17/07/18 16:30, Aapo Vienamo wrote:
...
> +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
> +
> +The values accepted by power-source property are
> +TEGRA_IO_PAD_VOLTAGE_1V8 and TEGRA_IO_PAD_VOLTAGE_3V3, which are defined
> +in dt-bindings
On 18/07/18 07:30, Marcel Ziswiler wrote:
> On Tue, 2018-07-17 at 13:57 +0300, Mikko Perttunen wrote:
>> Thanks!
>
> Yes, that fixes Apalis TK1 crashing as of late as well.
>
>> Reviewed-by: Mikko Perttunen
>
> Tested-by: Marcel Ziswiler
Tested-by: Jon Hun
On 11/07/18 12:17, Peter De Schrijver wrote:
> On Wed, Jul 11, 2018 at 09:42:20AM +0100, Jon Hunter wrote:
>>
>> On 11/07/18 09:00, Peter De Schrijver wrote:
>>> On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
>>>>
>>>> On 09/07/18
On 11/07/18 15:01, Aapo Vienamo wrote:
> Implement a function to query whether a pad is in deep power down mode.
Can you elaborate on why this public function is needed and who will be
using this?
Cheers
Jon
--
nvpublic
On 11/07/18 16:23, Jon Hunter wrote:
>
> On 11/07/18 15:01, Aapo Vienamo wrote:
>> Implement a function to query whether a pad is in deep power down mode.
> Can you elaborate on why this public function is needed and who will be
> using this?
Or I should say does this need
-1876,6 +1896,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
> .cpu_powergates = NULL,
> .has_tsense_reset = false,
> .has_gpu_clamps = false,
> + .has_impl_33v_pwr = true,
> .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
> .io_pads = tegra186_io_pads,
> .regs = &tegra186_pmc_regs,
> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
> index c32bf91..445aa66 100644
> --- a/include/soc/tegra/pmc.h
> +++ b/include/soc/tegra/pmc.h
> @@ -134,6 +134,7 @@ enum tegra_io_pad {
> TEGRA_IO_PAD_USB2,
> TEGRA_IO_PAD_USB3,
> TEGRA_IO_PAD_USB_BIAS,
> + TEGRA_IO_PAD_AO_HV,
> };
>
> /* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
a_io_pad_power_enable(enum tegra_io_pad id);
> int tegra_io_pad_power_disable(enum tegra_io_pad id);
> int tegra_io_pad_is_powered(enum tegra_io_pad id);
> -int tegra_io_pad_set_voltage(enum tegra_io_pad id,
> - enum tegra_io_pad_voltage voltage);
> -int tegra_io_pad_get_voltage(enum tegra_io_pad id);
>
> /* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
> int tegra_io_rail_power_on(unsigned int id);
>
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 12/07/18 08:52, Aapo Vienamo wrote:
> On Wed, 11 Jul 2018 16:26:42 +0100
> Jon Hunter wrote:
>
>> On 11/07/18 16:23, Jon Hunter wrote:
>>>
>>> On 11/07/18 15:01, Aapo Vienamo wrote:
>>>> Implement a function to query whether a pad is in deep po
ion(+)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index e1f8846..e3b9c22 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -19,6 +19,7 @@
>
> #include
> #include
> +#include
>
> /**
> * struct tegra_cl
gt; + return 0;
> +
> + divider_ux1 -= mul;
> +
> + if (divider_ux1 > div_mask(width))
> + return div_mask(width);
> +
> + return divider_ux1;
> +}
I think that personally, I would have preferred a clk-utils.c for stuff
like this but at the same time I am OK with this for now. It can always
be change later if we have such other similar functions. I also would
have updated the $subject now the name has been changed too.
Otherwise ...
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 11/07/18 15:39, Aapo Vienamo wrote:
> From: Peter De-Schrijver
>
> Add a clock type to model the sdmmc switch divider clocks which have paths
> to source clocks bypassing the divider (Low Jitter paths). These
> are handled by selecting the lj path when the divider is 1 (ie the
> rate is the
On 12/07/18 12:20, Peter De Schrijver wrote:
> On Thu, Jul 12, 2018 at 11:52:31AM +0100, Jon Hunter wrote:
>>
>> On 11/07/18 15:39, Aapo Vienamo wrote:
>>> From: Peter De-Schrijver
>>>
>>> Add a clock type to model the sdmmc switch divider clocks which
clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -706,6 +706,32 @@ struct clk *tegra_clk_register_super_clk(const char
> *name,
> const char * const *parent_names, u8 num_parents,
> unsigned long flags, void __iomem *reg, u8 clk_super_flags,
> spinlock_t *lock);
> +
> +/**
> + * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
> + *
> + * @hw: handle between common and hardware-specific interfaces
> + * @reg: register controlling mux and divider
> + * @flags: hardware-specific flags
> + * @lock:optional register lock
> + * @gate:gate clock
> + * @gate_ops:gate clock ops
> + */
> +struct tegra_sdmmc_mux {
> + struct clk_hw hw;
> + void __iomem*reg;
> + spinlock_t *lock;
> + const struct clk_ops*gate_ops;
> + struct tegra_clk_periph_gategate;
> + u8 div_flags;
> +};
> +
> +#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
> +
> +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
> + void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
> + unsigned long flags, void *lock);
> +
> /**
> * struct clk_init_table - clock initialization table
> * @clk_id: clock id as mentioned in device tree bindings
Acked-by: Jon Hunter
Cheers!
Jon
--
nvpublic
On 12/07/18 12:53, Aapo Vienamo wrote:
> From: Peter De-Schrijver
>
> These clocks have low jitter paths to certain parents. To model these
> correctly, use the sdmmc mux divider clock type.
>
> Signed-off-by: Peter De-Schrijver
> Signed-off-by: Aapo Vienamo
> Acked-by: Peter De Schrijver
>
gates,
> @@ -1846,6 +2021,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
> .needs_mbist_war = true,
> .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
> .io_pads = tegra210_io_pads,
> + .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
> + .pin_descs = tegra210_pin_descs,
> .regs = &tegra20_pmc_regs,
> .init = tegra20_pmc_init,
> .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
> @@ -1896,6 +2073,10 @@ static const struct tegra_io_pad_soc
> tegra186_io_pads[] = {
> TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
> };
>
> +static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
> + TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
> +};
> +
> static const struct tegra_pmc_regs tegra186_pmc_regs = {
> .scratch0 = 0x2000,
> .dpd_req = 0x74,
> @@ -1949,6 +2130,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
> .has_impl_33v_pwr = true,
> .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
> .io_pads = tegra186_io_pads,
> + .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
> + .pin_descs = tegra186_pin_descs,
> .regs = &tegra186_pmc_regs,
> .init = NULL,
> .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
>
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 12/07/18 14:11, Aapo Vienamo wrote:
> On Thu, 12 Jul 2018 13:59:58 +0100
> Jon Hunter wrote:
>
>> On 12/07/18 12:53, Aapo Vienamo wrote:
>>> From: Peter De-Schrijver
>>>
>>> These clocks have low jitter paths to certain parents. To model these
>
On 13/07/18 14:17, Aapo Vienamo wrote:
> Implement and use tegra_sdhci_get_max_clock() which returns the true
> maximum host clock rate. The issue with tegra_sdhci_get_max_clock() is
Don't you mean sdhci_pltfm_clk_get_max_clock above? Does this function
need fixing then? Or at least should there
On 13/07/18 13:55, Aapo Vienamo wrote:
> This happens because sdhci_pltfm_clk_get_max_clock() does not actually
> return the maximum clock rate but the current one, leading to smaller
> clock rates on some platforms. I'll send a patch that fixes this for
> sdhci-tegra. Although this raises the qu
On 09/03/18 08:14, Peter De Schrijver wrote:
> On Thu, Mar 08, 2018 at 11:25:04PM +0000, Jon Hunter wrote:
>>
>> On 06/02/18 16:34, Peter De Schrijver wrote:
>>> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
>>> support in this driver. Also
On 12/03/18 09:14, Peter De Schrijver wrote:
> On Thu, Mar 08, 2018 at 10:50:06PM +0000, Jon Hunter wrote:
>>
>> On 06/02/18 16:34, Peter De Schrijver wrote:
>>> This patch prepares the dfll driver to work with PWM regulators.
>>> To do this we introduce a new arr
On 06/02/18 16:34, Peter De Schrijver wrote:
> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
> support in this driver. Also allow for the case where the CPU voltage is
> controlled directly by the DFLL rather than by a separate regulator object.
>
> Signed-off-by: Peter De
#include
> #include
> @@ -725,7 +726,7 @@ static int tegra_powergate_of_get_clks(struct
> tegra_powergate *pg,
> unsigned int i, count;
> int err;
>
> - count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
> + count = of_clk_get_parent_count(np);
> if (count == 0)
> return -ENODEV;
>
>
Acked-by: Jon Hunter
Cheers
Jon
On 01/03/18 14:18, Mathias Nyman wrote:
> On 14.02.2018 18:34, Jon Hunter wrote:
>> Add runtime PM support to the Tegra XHCI driver and move the function
>> calls to enable/disable the clocks, regulators and PHY into the runtime
>> PM callbacks.
>>
&
struct
> platform_device *pdev)
> return 0;
> }
>
> -static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
> - { .compatible = "nvidia,tegra124-dfll", },
> - { },
> -};
> -
> static const struct dev_pm_ops tegra124_dfll_pm_ops = {
> SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
> tegra_dfll_runtime_resume, NULL)
>
Otherwise ...
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 06/02/18 16:34, Peter De Schrijver wrote:
> The CVB table contains calibration data for the CPU DFLL based on
> process charaterization. The regulator step and offset parameters depend
> on the regulator supplying vdd-cpu , not on the specific Tegra SKU.
> Hence than hardcoding those regulator
gt; +
> static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
> .cpu_max_freq_table = tegra124_cpu_max_freq_table,
> .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
> @@ -95,11 +510,22 @@ struct dfll_fcpu_data {
> .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
> };
>
> +static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
> + .cpu_max_freq_table = tegra210_cpu_max_freq_table,
> + .cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table),
> + .cpu_cvb_tables = tegra210_cpu_cvb_tables,
> + .cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables),
> +};
> +
> static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
> {
> .compatible = "nvidia,tegra124-dfll",
> .data = &tegra124_dfll_fcpu_data,
> },
> + {
> + .compatible = "nvidia,tegra210-dfll",
> + .data = &tegra210_dfll_fcpu_data
> + },
> { },
> };
>
> diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h
> index bcf15a0..91a1941 100644
> --- a/drivers/clk/tegra/cvb.h
> +++ b/drivers/clk/tegra/cvb.h
> @@ -41,6 +41,7 @@ struct cvb_cpu_dfll_data {
> u32 tune0_low;
> u32 tune0_high;
> u32 tune1;
> + unsigned int tune_high_min_millivolts;
> };
>
> struct cvb_table {
>
Otherwise ...
Acked-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 06/02/18 16:34, Peter De Schrijver wrote:
> This patch prepares the dfll driver to work with PWM regulators.
> To do this we introduce a new array lut_uv which gives the voltage for
> a given index generated by the dfll logic. This index will then be
> translated to a PMIC voltage ID in case of
On 06/02/18 16:34, Peter De Schrijver wrote:
> The DFLL can directly generate a PWM signal to control the regulator IC
> rather then sending i2c messages. This patch adds support for this mode.
> In this mode the hardware LUT is not used and also there is no regulator
> object involved because the
On 06/02/18 16:34, Peter De Schrijver wrote:
> Add new properties to configure the DFLL PWM regulator support. Also
> add an example and make the I2C clock only required when I2C support is
> used.
>
> Signed-off-by: Peter De Schrijver
> ---
> .../bindings/clock/nvidia,tegra124-dfll.txt
ra124.o
> obj-y += cvb.o
> obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
>
Reviewed-by: Jon Hunter
Cheers
Jon
--
nvpublic
On 06/02/18 16:34, Peter De Schrijver wrote:
> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
> support in this driver. Also allow for the case where the CPU voltage is
> controlled directly by the DFLL rather than by a separate regulator object.
>
> Signed-off-by: Peter De
On 09/03/18 08:36, Thierry Reding wrote:
> On Thu, Mar 08, 2018 at 09:31:07PM +0000, Jon Hunter wrote:
>>
>> On 01/03/18 14:18, Mathias Nyman wrote:
>>> On 14.02.2018 18:34, Jon Hunter wrote:
>>>> Add runtime PM support to the Tegra XHCI driver and move the f
On 09/03/18 09:13, Mathias Nyman wrote:
> On 09.03.2018 10:36, Thierry Reding wrote:
>> On Thu, Mar 08, 2018 at 09:31:07PM +0000, Jon Hunter wrote:
>>>
>>> On 01/03/18 14:18, Mathias Nyman wrote:
>>>> On 14.02.2018 18:34, Jon Hunter wrote:
>>>>&g
On 13/03/18 09:03, Peter De Schrijver wrote:
> On Mon, Mar 12, 2018 at 11:08:51AM +0000, Jon Hunter wrote:
>>
>> On 12/03/18 09:14, Peter De Schrijver wrote:
>>> On Thu, Mar 08, 2018 at 10:50:06PM +, Jon Hunter wrote:
>>>>
>>>> On 06/02/18 1
On 13/03/18 09:51, Peter De Schrijver wrote:
> On Mon, Mar 12, 2018 at 12:15:22PM +0000, Jon Hunter wrote:
>>
>> On 06/02/18 16:34, Peter De Schrijver wrote:
>>> Tegra210 has a very similar CPU clocking scheme than Tegra124. So add
>>> support in this driver. Also
Export the symbol for genpd_dev_pm_attach_by_name() so that drivers
built as modules can call this function.
Signed-off-by: Jon Hunter
---
drivers/base/power/domain.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index 4b5714199490
Now that the Tegra xHCI driver manages the XUSB power-domains itself,
remove the code to power-up the power-domains used by the xHCI device
from the PMC driver on boot.
Signed-off-by: Jon Hunter
---
drivers/soc/tegra/pmc.c | 16
1 file changed, 16 deletions(-)
diff --git a
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