On Fri, Sep 25 2015 at 07:04 -0600, Marc Titinger wrote:
From: Marc Titinger
fake path to start testing, eventually move this out of /arch/.
incidently enable PM_GENERIC_DOMAINS for VExpress.
In fact, this could be moved out of ARM. My last series moved it to
drivers/base/power/.
-- Lina
S
cpu_cluster_pm_exit() must be sent after cpu_cluster_pm_enter() has been
sent for the cluster and before any cpu_pm_exit() notifications are sent
for any CPU.
Cc: Nicolas Pitre
Acked-by: Kevin Hilman
Signed-off-by: Lina Iyer
---
kernel/cpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1
in subsequent patches.
Suggested-by: Lina Iyer
Signed-off-by: Axel Haslam
---
arch/arm/mach-exynos/pm_domains.c | 2 +-
arch/arm/mach-imx/gpc.c | 2 +-
arch/arm/mach-s3c64xx/pm.c| 4 ++--
arch/arm/mach-shmobile/pm-r8a7779.c | 2 +-
arch/arm/mach-shmobile/pm
Hi Marc,
I am trying to apply this on top of Axel's patches on linux-next (after
fixing issues I saw with his v9), and running to issues applying your
patches. Could you rebase on top of his v10 (he said he would send to
the ML soon) ?
Thanks,
Lina
On Tue, Oct 06 2015 at 08:27 -0600, Marc Titin
On Mon, Aug 20 2018 at 00:05 -0600, Bjorn Andersson wrote:
On Fri 17 Aug 09:38 PDT 2018, Lina Iyer wrote:
Thanks Lina, I think this looks like a very reasonable approach!
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupt
On Sun, Aug 26 2018 at 08:33 -0600, Linus Walleij wrote:
On Fri, Aug 17, 2018 at 6:39 PM Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to the
its interrupt controller. Only select
On Mon, Aug 27 2018 at 18:31 -0600, Bjorn Andersson wrote:
On Fri 24 Aug 13:01 PDT 2018, Lina Iyer wrote:
Enable TLMM IRQs to be sensed by PDC when we enter suspend. It is
possible that the TLMM may be powered off and not detect GPIOs that are
configured as wake up interrupts. By hooking into
On Mon, Aug 27 2018 at 18:26 -0600, Bjorn Andersson wrote:
On Mon 27 Aug 09:56 PDT 2018, Lina Iyer wrote:
On Sun, Aug 26 2018 at 08:33 -0600, Linus Walleij wrote:
> On Fri, Aug 17, 2018 at 6:39 PM Lina Iyer wrote:
>
> > QCOM SoC's that have Power Domain Controller (PDC) chip
On Wed, Aug 08 2018 at 04:56 -0600, Lorenzo Pieralisi wrote:
On Mon, Aug 06, 2018 at 11:37:55AM +0200, Rafael J. Wysocki wrote:
On Fri, Aug 3, 2018 at 1:42 PM, Ulf Hansson wrote:
> [...]
>
>>>
>>> Assuming that I have got that right, there are concerns, mostly regarding
>>> patch [07/26], but I
On Tue, Aug 07 2018 at 13:57 -0600, Evan Green wrote:
On Tue, Jul 31, 2018 at 3:44 PM Lina Iyer wrote:
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines
On Fri, Aug 10 2018 at 09:06 -0600, Stephen Boyd wrote:
Quoting Marc Zyngier (2018-08-10 00:45:12)
On Thu, 09 Aug 2018 18:30:53 +0100,
Stephen Boyd wrote:
>
> Quoting Marc Zyngier (2018-08-07 23:26:32)
> >
> > Level interrupts should be taken care of without doing anything, by the
> > very natu
On Thu, Aug 09 2018 at 04:25 -0600, Lorenzo Pieralisi wrote:
On Wed, Aug 08, 2018 at 12:02:48PM -0600, Lina Iyer wrote:
On Wed, Aug 08 2018 at 04:56 -0600, Lorenzo Pieralisi wrote:
>On Mon, Aug 06, 2018 at 11:37:55AM +0200, Rafael J. Wysocki wrote:
>>On Fri, Aug 3, 2018 at 1:42 PM, Ul
On Thu, Aug 09 2018 at 02:16 -0600, Rafael J. Wysocki wrote:
On Wed, Aug 8, 2018 at 8:02 PM, Lina Iyer wrote:
On Wed, Aug 08 2018 at 04:56 -0600, Lorenzo Pieralisi wrote:
On Mon, Aug 06, 2018 at 11:37:55AM +0200, Rafael J. Wysocki wrote:
On Fri, Aug 3, 2018 at 1:42 PM, Ulf Hansson
wrote
On Wed, Aug 01 2018 at 14:04 -0600, Lina Iyer wrote:
On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:19 +0100,
Lina Iyer wrote:
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76
On Thu, Aug 23 2018 at 19:57 -0600, David Dai wrote:
Add RSC(Resource State Coordinator) provider
dictating network-on-chip interconnect bus performance
found on SDM845-based platforms.
Change-Id: I58f0bfc3ed484d7b45064dceb94dcfda507e9333
Remove this pls.
-- Lina
Signed-off-by: David Dai
--
On Thu, Aug 23 2018 at 19:57 -0600, David Dai wrote:
Introduce Qualcomm SDM845 specific provider driver using the
interconnect framework.
SDM845 specific, can't be reused?
Please describe why we need this driver and how this driver solves the
problem.
Change-Id: I716b39068b4a211b8203b2a52d30
On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-17 12:10:23)
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected. The PDC however will be
The PDC map should use the GIC SPI port and not the vector. GIC
internally adds 32 to SPI hwirq numbers.
Fixes: 1ae8862e27e ("dt-bindings/interrupt-controller: pdc: Describe PDC device
binding")
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.t
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Fix PDC map, use GIC SPI port number for hwirq
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC IRQ number in example
- Describe IRQ trigger type in example
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 104 +-
1 file changed, 101 insertions(+), 3 deletions(-)
diff --git a/Documentation
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Define IRQ trigger type in DT
layed again.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Remove IRQF_NO_SUSPEND and IRQF_ONE_SHOT
t-controller/qcom,pdc.txt
[3]. drivers/pinctrl/qcom/pinctrl-msm.c
[4]. https://lore.kernel.org/patchwork/patch/977589/
[5]. https://lore.kernel.org/patchwork/patch/975425/
Lina Iyer (5):
drivers: pinctrl: qcom: add wakeup capability to GPIO
dt-bindings: pinctrl: add wakeup capable GPIOs for SDM845
d
to be sent
only during entry of deeper system low power modes or suspend.
[1]https://patchwork.kernel.org/patch/10477533/
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
drivers/soc/qcom/rpmh.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/soc/qcom
2]. Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
[3]. drivers/pinctrl/qcom/pinctrl-msm.c
Lina Iyer (4):
drivers: pinctrl: qcom: add wakeup capability to GPIO
drivers: pinctrl: qcom: add wakeup gpio map for sdm845
arm64: dts: msm: add PDC device bindings for sdm845
a
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2acc17ce1a9c..8ccce42885c1
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 69
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757
rrupt at the GIC and the interrupt handler for the GPIO is invoked.
Setup the PDC IRQ when the GPIO's IRQ is requested and enable the PDC
IRQ when the GPIO's IRQ is enabled.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 163 +
drive
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2acc17ce1a9c..8ccce42885c1
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757
2]. Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
[3]. drivers/pinctrl/qcom/pinctrl-msm.c
Lina Iyer (4):
drivers: pinctrl: qcom: add wakeup capability to GPIO
drivers: pinctrl: qcom: add wakeup gpio map for sdm845
arm64: dts: msm: add PDC device bindings for sdm845
a
rrupt at the GIC and the interrupt handler for the GPIO is invoked.
Setup the PDC IRQ when the GPIO's IRQ is requested and enable the PDC
IRQ when the GPIO's IRQ is enabled.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 163 +
drive
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 69
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:18 +0100,
Lina Iyer wrote:
+static irqreturn_t wake_irq_gpio_handler(int irq, void *data)
+{
+ struct irq_data *irqd = data;
+ struct irq_desc *desc = irq_data_to_desc
On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:19 +0100,
Lina Iyer wrote:
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions
On Wed, Aug 01 2018 at 16:38 -0600, Bjorn Andersson wrote:
On Wed 01 Aug 12:45 PDT 2018, Lina Iyer wrote:
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
> On Wed, 01 Aug 2018 03:00:18 +0100,
> Lina Iyer wrote:
[..]
> Why isn't that th
On Thu, Aug 02 2018 at 00:08 -0600, Marc Zyngier wrote:
Hi Lina,
On Wed, 01 Aug 2018 20:45:38 +0100,
Lina Iyer wrote:
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
> On Wed, 01 Aug 2018 03:00:18 +0100,
> Lina Iyer wrote:
>>
>> +
On Thu, Aug 02 2018 at 01:27 -0600, Marc Zyngier wrote:
On Thu, 02 Aug 2018 07:51:04 +0100,
Lina Iyer wrote:
On Thu, Aug 02 2018 at 00:08 -0600, Marc Zyngier wrote:
> Hi Lina,
>
> On Wed, 01 Aug 2018 20:45:38 +0100,
> Lina Iyer wrote:
>>
>> Thanks for the feedback, Ma
On Thu, Jul 12 2018 at 10:31 -0600, Evan Green wrote:
On Tue, Jul 10, 2018 at 1:38 PM Lina Iyer wrote:
On Tue, Jul 10 2018 at 12:53 -0600, Evan Green wrote:
>On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson
> wrote:
>Our understanding is the downstream kernel had an interrupt hierarch
+ Dan
On Fri, Jul 13 2018 at 07:46 -0600, Raju P L S S S N wrote:
From: "Raju P.L.S.S.S.N"
The patch fixes the bug reported by Dan Carpenter.
It removes the unnecessary err check for ‘tcs’ reported by
static checker warning:
drivers/soc/qcom/rpmh-rsc.c:111 tcs_invalidate()
warn: 'tcs' isn't a
oller a.k.a PDC.
This series adds support for the PDC's interrupt controller.
Please consider reviewing these patches.
Lina Iyer (4):
drivers: irqchip: pdc: add support for PDC interrupt controller
dt-bindings/interrupt-controller: pdc: descibe PDC device binding
drivers: irqchip: pd
d replays the
pending interrupts so the GIC may wake up the processor.
Signed-off-by: Archana Sathyakumar
Signed-off-by: Lina Iyer
[Lina: Split out DT bindings target data and initialization changes]
---
drivers/irqchip/Kconfig| 9 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/qco
From: Archana Sathyakumar
Log key PDC pin configuration in FTRACE.
Cc: Steven Rostedt
Signed-off-by: Archana Sathyakumar
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 6 ++
include/trace/events/pdc.h | 50 ++
2 files changed, 56
From: Archana Sathyakumar
Add PDC pin information for SDM845. Interrupts listed are wake up
sources for the processor, when the processor and GIC are powered down.
Signed-off-by: Archana Sathyakumar
Signed-off-by: Lina Iyer
---
drivers/irqchip/Makefile | 2 +-
drivers/irqchip/qcom
ff-by: Archana Sathyakumar
Signed-off-by: Lina Iyer
---
.../bindings/interrupt-controller/qcom,pdc.txt | 55 ++
1 file changed, 55 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
diff --git
a/Documentation/devicetree/bin
On Tue, Jan 23 2018 at 18:15 +, Sudeep Holla wrote:
Hi Lina,
On Tue, Jan 23, 2018 at 5:56 PM, Lina Iyer wrote:
On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC is in a
power domain that can be powered off when not needed. Interrupts that need to
be sensed even whe
On Tue, Jan 23 2018 at 18:10 +, Sudeep Holla wrote:
On 23/01/18 17:56, Lina Iyer wrote:
From: Archana Sathyakumar
Add device binding documentation for the PDC Interrupt controller on
QCOM SoC's like the SDM845. The interrupt-controller can be used to
sense edge low interrupts and w
On Wed, Jan 24 2018 at 10:10 +, Sudeep Holla wrote:
On 23/01/18 18:44, Lina Iyer wrote:
On Tue, Jan 23 2018 at 18:15 +, Sudeep Holla wrote:
Hi Lina,
On Tue, Jan 23, 2018 at 5:56 PM, Lina Iyer wrote:
On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC
is in a
On Tue, Jan 23 2018 at 18:13 +, Steven Rostedt wrote:
On Tue, 23 Jan 2018 10:56:55 -0700
Lina Iyer wrote:
From: Archana Sathyakumar
Hi Lina and Archana,
Log key PDC pin configuration in FTRACE.
Cc: Steven Rostedt
Signed-off-by: Archana Sathyakumar
Signed-off-by: Lina Iyer
On Wed, Jan 24 2018 at 17:54 +, Sudeep Holla wrote:
On 24/01/18 17:43, Lina Iyer wrote:
On Wed, Jan 24 2018 at 10:10 +, Sudeep Holla wrote:
On 23/01/18 18:44, Lina Iyer wrote:
On Tue, Jan 23 2018 at 18:15 +, Sudeep Holla wrote:
Also when will this PDC wakeup interrupts get
On Thu, Jan 25 2018 at 16:39 +, Sudeep Holla wrote:
On 25/01/18 15:54, Lina Iyer wrote:
On Wed, Jan 24 2018 at 17:54 +, Sudeep Holla wrote:
On 24/01/18 17:43, Lina Iyer wrote:
On Wed, Jan 24 2018 at 10:10 +, Sudeep Holla wrote:
On 23/01/18 18:44, Lina Iyer wrote:
On Tue
On Wed, Jan 24 2018 at 14:20 +, Marc Zyngier wrote:
On 23/01/18 17:56, Lina Iyer wrote:
From: Archana Sathyakumar
+#include "qcom-pdc.h"
+
+const struct pdc_pin sdm845_data[] = {
+ {0, 512}, /* rpmh_wake */
+ {1, 513}, /* ee0_apps_hlos_spmi_periph_irq */
+
Hi Marc,
On Wed, Jan 24 2018 at 14:20 +, Marc Zyngier wrote:
Hi Lina, Archana,
On 23/01/18 17:56, Lina Iyer wrote:
From : Archana Sathyakumar
The Power Domain Controller (PDC) hardware block on Qualcomm SoCs houses
an interrupt controller along with other domain control functions to
On Thu, Jan 25 2018 at 18:43 +, Sudeep Holla wrote:
On 25/01/18 18:13, Lina Iyer wrote:
On Thu, Jan 25 2018 at 16:39 +, Sudeep Holla wrote:
On 25/01/18 15:54, Lina Iyer wrote:
On Wed, Jan 24 2018 at 17:54 +, Sudeep Holla wrote:
On 24/01/18 17:43, Lina Iyer wrote:
On Wed
Hi Mark,
On Wed, Jan 24 2018 at 14:20 +, Marc Zyngier wrote:
Hi Lina, Archana,
On 23/01/18 17:56, Lina Iyer wrote:
From : Archana Sathyakumar
The Power Domain Controller (PDC) hardware block on Qualcomm SoCs houses
an interrupt controller along with other domain control functions to
On Tue, Jan 30 2018 at 18:11 +, Marc Zyngier wrote:
On 30/01/18 17:56, Lina Iyer wrote:
Hi Mark,
On Wed, Jan 24 2018 at 14:20 +, Marc Zyngier wrote:
Hi Lina, Archana,
On 23/01/18 17:56, Lina Iyer wrote:
From : Archana Sathyakumar
The Power Domain Controller (PDC) hardware block on
On Wed, Jan 31 2018 at 16:46 +, Marc Zyngier wrote:
On 31/01/18 16:24, Lina Iyer wrote:
On Tue, Jan 30 2018 at 18:11 +, Marc Zyngier wrote:
On 30/01/18 17:56, Lina Iyer wrote:
On Wed, Jan 24 2018 at 14:20 +, Marc Zyngier wrote:
On 23/01/18 17:56, Lina Iyer wrote:
From : Archana
Hi Stephen,
I will address all the comments in the next spin of the patch. Here are
some responses to the questions.
On Tue, Mar 06 2018 at 12:45 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-02 08:43:08)
[...]
+#include
If the driver doesn't become tristate, this should b
in the context of the controller's thread and frees the
allocated memory. This API allows RPMH requests from atomic contexts as
well.
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh.c | 53 +
include/soc/qcom/rpmh.h | 8
2 files ch
.
rpmh_write_batch() is a blocking call that can be used to send multiple
RPMH command sets. Each RPMH command set is set asynchronously and the
API blocks until all the command sets are complete and receive their
tx_done callbacks.
Signed-off-by: Lina Iyer
---
Changes in v4:
- reorganize
the wake TCS
is being repurposed to send active request, hence the sleep and wake
TCSes be invalidated before the active request is sent.
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/qcom
at the time of writing. The TCS are triggered by the firmware
after the last of the CPUs has executed its WFI. Since these requests
may come in different batches of requests, it is the job of this
controller driver to find and arrange the requests into the available
TCSes.
Signed-off-by: Lina Iyer
are
dedicated for each type of requests. Control TCS are used to provide
specific information to the controller.
Signed-off-by: Lina Iyer
---
Changes in v4:
- lots of variable name changes as suggested by Stephen B
- use of const for data pointers
- fix comments and othe
Allow sleep and wake commands to be cleared from the respective TCSes,
so that they can be re-populated.
Signed-off-by: Lina Iyer
---
Changes in v4:
- refactored the rphm_rsc_invalidate()
---
drivers/soc/qcom/rpmh-internal.h | 1 +
drivers/soc/qcom/rpmh-rsc.c | 48
PM activity and may be called from the
system PM drivers when the system is entering suspend or deeper sleep
modes during cpuidle.
Also allow invalidating the cached requests, so they may be re-populated
again.
Signed-off-by: Lina Iyer
---
Changes in v4:
- remove locking for ->dirty
Add device binding documentation for Qualcomm Technology Inc's RPMH RSC
driver. The driver is used for communicating resource state requests for
shared resources.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
Changes in v3:
- Move to soc/qcom
- Amend tex
re patches will add
more functionality that cater to complex drivers and use cases.
Please consider reviewing this patchset.
v1: https://www.spinics.net/lists/devicetree/msg210980.html
v2: https://lkml.org/lkml/2018/2/15/852
v3: https://lkml.org/lkml/2018/3/2/801
Lina Iyer (10):
drivers: qcom
Log sent RPMH requests and interrupt responses in FTRACE.
Cc: Steven Rostedt
Signed-off-by: Lina Iyer
---
Changes in v4:
- fix compilation issues, use __assign_str
- use %#x instead of 0x%08x
Changes in v3:
- Use __string() instead of char *
- fix
used to send
active state requests.
Signed-off-by: Lina Iyer
---
Changes in v4:
- use const struct tcs_cmd in API
- remove wait count from this patch
- changed -EFAULT to -EINVAL
---
drivers/soc/qcom/Makefile| 4 +-
drivers/soc/qcom/rpmh-internal.h | 2
On Fri, Mar 09 2018 at 16:52 -0700, Steven Rostedt wrote:
On Fri, 9 Mar 2018 16:25:36 -0700
Lina Iyer wrote:
Log sent RPMH requests and interrupt responses in FTRACE.
Cc: Steven Rostedt
Signed-off-by: Lina Iyer
---
Changes in v4:
- fix compilation issues, use __assign_str
On Mon, Mar 05 2018 at 16:15 -0700, Bjorn Andersson wrote:
On Mon 26 Feb 09:58 PST 2018, Lina Iyer wrote:
From: Mahesh Sivasubramanian
Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory
On Mon, Mar 05 2018 at 17:21 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-02-26 09:58:02)
diff --git a/Documentation/devicetree/bindings/arm/msm/cmd-db.txt
b/Documentation/devicetree/bindings/arm/msm/cmd-db.txt
new file mode 100644
index ..5737ed2ac6e8
--- /dev/null
+++ b
On Mon, Mar 05 2018 at 11:42 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-02-26 09:58:01)
diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c
new file mode 100644
index ..0792a2a98fc9
--- /dev/null
+++ b/drivers/soc/qcom/cmd-db.c
@@ -0,0 +1,319 @@
+/* SPDX
On Tue, Mar 06 2018 at 09:21 -0700, Lina Iyer wrote:
On Mon, Mar 05 2018 at 11:42 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-02-26 09:58:01)
+size_t cmd_db_read_aux_data_len(const char *id)
+{
+ int ret;
+ struct entry_header ent;
+ struct rsc_hdr rsc_hdr
On Tue, Mar 06 2018 at 14:47 -0700, Steven Rostedt wrote:
On Tue, 6 Mar 2018 13:38:06 +0800
kbuild test robot wrote:
>> drivers/soc/qcom/./trace-rpmh.h:29:3: error: implicit declaration of
function '__assign_string'; did you mean '__assign_str'?
[-Werror=implicit-function-declaration]
Yes,
On Tue, Mar 06 2018 at 14:56 -0700, Lina Iyer wrote:
On Tue, Mar 06 2018 at 14:47 -0700, Steven Rostedt wrote:
On Tue, 6 Mar 2018 13:38:06 +0800
kbuild test robot wrote:
drivers/soc/qcom/./trace-rpmh.h:29:3: error: implicit declaration of function
'__assign_string'; di
On Mon, Mar 05 2018 at 13:45 -0700, Evan Green wrote:
Hi Lina,
On Fri, Mar 2, 2018 at 8:43 AM, Lina Iyer wrote:
Active state requests are sent immediately to the mailbox controller,
while sleep and wake state requests are cached in this driver to avoid
taxing the mailbox controller repeatedly
On Tue, Mar 06 2018 at 15:30 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-02 08:43:09)
Add device binding documentation for Qualcomm Technology Inc's RPMH RSC
driver. The hardware block is used for communicating resource state
s/driver/hardware/
Ok.
requests for shared reso
On Fri, Mar 16 2018 at 11:00 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-08 14:55:40)
On Thu, Mar 08 2018 at 14:59 -0700, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-03-02 08:43:16)
>> @@ -343,6 +346,146 @@ int rpmh_write(struct rpmh_client *rc, enum rpmh_sta
On Thu, Mar 22 2018 at 19:30 -0600, David Collins wrote:
Hello Stephen,
Thank you for the very detailed review feedback.
On 03/21/2018 12:07 PM, Stephen Boyd wrote:
Quoting David Collins (2018-03-16 18:09:10)
+static int rpmh_regulator_remove(struct platform_device *pdev)
+{
+ struct
From: Mahesh Sivasubramanian
Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory.
Cc: devicet...@vger.kernel.org
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by
v2]: https://lkml.org/lkml/2018/2/8/588
[v3]: https://lkml.org/lkml/2018/2/16/842
[v4]: https://patchwork.kernel.org/patch/10242935/
[v5]: https://lkml.org/lkml/2018/3/14/787
[v6]: https://lkml.org/lkml/2018/4/5/451
Lina Iyer (2):
drivers: qcom: add command DB driver
dt-bindings: introduce Command D
SoC and the platform
are made available in the shared memory. Drivers can query this
information using predefined strings.
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by: Bjorn Andersson
---
Changes in v6:
- Remove indirection and use the actual command db
y need.
[v1]: https://www.spinics.net/lists/linux-arm-msm/msg32462.html
[v2]: https://lkml.org/lkml/2018/2/8/588
[v3]: https://lkml.org/lkml/2018/2/16/842
[v4]: https://patchwork.kernel.org/patch/10242935/
[v5]: https://lkml.org/lkml/2018/3/14/787
[v6]: https://lkml.org/lkml/2018/4/5/451
Lina Iyer (2):
SoC and the platform
are made available in the shared memory. Drivers can query this
information using predefined strings.
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by: Bjorn Andersson
---
Changes in v6:
- Remove indirection and use the actual command db
From: Mahesh Sivasubramanian
Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory.
Cc: devicet...@vger.kernel.org
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by
On Tue, Apr 10 2018 at 18:31 -0600, Bjorn Andersson wrote:
On Thu 05 Apr 09:18 PDT 2018, Lina Iyer wrote:
diff --git a/drivers/soc/qcom/rpmh-internal.h b/drivers/soc/qcom/rpmh-internal.h
[..]
@@ -439,6 +445,107 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct
tcs_request *msg
On Tue, Apr 10 2018 at 20:23 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-04-09 08:36:31)
On Fri, Apr 06 2018 at 19:21 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-04-05 09:18:28)
>> diff --git a/include/soc/qcom/rpmh.h b/include/soc/qcom/rpmh.h
>> new file mode
On Wed, Apr 11 2018 at 09:29 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-04-09 09:08:00)
On Fri, Apr 06 2018 at 19:14 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-04-05 09:18:26)
>> diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
b/Documentation/d
On Tue, Apr 10 2018 at 13:36 -0600, Bjorn Andersson wrote:
On Mon 09 Apr 09:08 PDT 2018, Lina Iyer wrote:
On Fri, Apr 06 2018 at 19:14 -0600, Stephen Boyd wrote:
> Quoting Lina Iyer (2018-04-05 09:18:26)
> > diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
b/Docu
On Tue, Apr 10 2018 at 22:39 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-04-05 09:18:25)
Add controller driver for QCOM SoCs that have hardware based shared
resource management. The hardware IP known as RSC (Resource State
Coordinator) houses multiple Direct Resource Voter (DRV) for
On Fri, Apr 06 2018 at 19:21 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-04-05 09:18:28)
diff --git a/include/soc/qcom/rpmh.h b/include/soc/qcom/rpmh.h
new file mode 100644
index ..95334d4c1ede
--- /dev/null
+++ b/include/soc/qcom/rpmh.h
@@ -0,0 +1,34 @@
+/* SPDX-License
On Fri, Apr 06 2018 at 19:14 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-04-05 09:18:26)
diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
new file mode 100644
index ..dcf71a5b302f
--- /dev/null
On Fri, Apr 06 2018 at 17:23 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-04-06 08:13:55)
From: Mahesh Sivasubramanian
Command DB is a simple database in the shared memory of QCOM SoCs, that
provides information regarding shared resources. Some shared resources
in the SoC have
SoC and the platform
are made available in the shared memory. Drivers can query this
information using predefined strings.
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by: Bjorn Andersson
Reviewed-by: Stephen Boyd
---
Changes in v6:
- Remove indirection and use
From: Mahesh Sivasubramanian
Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory.
Cc: devicet...@vger.kernel.org
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
Reviewed-by
l.org/lkml/2018/4/6/756
Lina Iyer (2):
drivers: qcom: add command DB driver
dt-bindings: introduce Command DB for QCOM SoCs
.../bindings/reserved-memory/qcom,cmd-db.txt | 37 +++
drivers/of/platform.c | 1 +
drivers/soc/qcom/Kconfig
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