On Thu, Mar 08 2018 at 11:57 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-02 08:43:11)
diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c
new file mode 100644
index ..d95ea3fa8b67
--- /dev/null
+++ b/drivers/soc/qcom/rpmh.c
@@ -0,0 +1,257 @@
+// SPDX-License
On Thu, Mar 08 2018 at 14:59 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-02 08:43:16)
diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c
index a02d9f685b2b..19e84b031c0d 100644
--- a/drivers/soc/qcom/rpmh.c
+++ b/drivers/soc/qcom/rpmh.c
@@ -22,6 +22,7 @@
#define
On Thu, Mar 08 2018 at 12:41 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-02 08:43:12)
Sleep and wake requests are sent when the application processor
subsystem of the SoC is entering deep sleep states like in suspend.
These requests help lower the system power requirements when the
On Thu, Mar 08 2018 at 16:58 -0700, Lina Iyer wrote:
On Thu, Mar 08 2018 at 12:41 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-02 08:43:12)
+static int find_slots(struct tcs_group *tcs, struct tcs_request *msg,
+int *m, int *n)
+{
+ int slot, offset
On Thu, Mar 08 2018 at 13:40 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-03-02 08:43:13)
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index 34e780d9670f..e9f5a1f387fd 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-rsc.c
@@ -170,6 +170,52
SoC and the platform
are made available in the shared memory. Drivers can query this
information using predefined strings.
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
---
Changes in v5:
- Use strncmp
- Add check in probe to ensure the location at dictionary
get the information they need.
[v1]: https://www.spinics.net/lists/linux-arm-msm/msg32462.html
[v2]: https://lkml.org/lkml/2018/2/8/588
[v3]: https://lkml.org/lkml/2018/2/16/842
[v4]: https://patchwork.kernel.org/patch/10242935/
Lina Iyer (2):
drivers: qcom: add command DB driver
dt-bindings
From: Mahesh Sivasubramanian
Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory.
Cc: devicet...@vger.kernel.org
Signed-off-by: Mahesh Sivasubramanian
Signed-off-by: Lina Iyer
---
Changes
The PDC irqchp can convert a falling edge or level low interrupt to a
rising edge or level high interrupt at the GIC. We just need to setup
the GIC correctly. Set up the interrupt type for the IRQ_TYPE_EDGE_BOTH
as IRQ_TYPE_EDGE_RISING at the GIC.
Reported-by: Evan Green
Signed-off-by: Lina Iyer
On Fri, Sep 28 2018 at 04:40 -0600, Marc Zyngier wrote:
On 27/09/18 18:18, Lina Iyer wrote:
The PDC irqchp can convert a falling edge or level low interrupt to a
rising edge or level high interrupt at the GIC. We just need to setup
the GIC correctly. Set up the interrupt type for the
On Wed, Nov 21 2018 at 14:36 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-11-20 16:06:47)
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep low power modes and suspend.
Signed-off-by
On Tue, Nov 27 2018 at 02:12 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-11-26 08:14:55)
On Wed, Nov 21 2018 at 14:36 -0700, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-11-20 16:06:47)
>> SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
>> route
Add PDC wakeup irq for GPIOs and the wakeup parent for TLMM.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8e15392a6f64
98238/
[2]. https://lkml.org/lkml/2018/9/21/471
[3]. https://lkml.org/lkml/2018/9/21/474
[4]. https://lore.kernel.org/patchwork/patch/1008046/
Lina Iyer (3):
drivers: pinctrl: msm: setup gpio irqchip in hierarchy with pdc
irqchip
dt-bindings: sdm845-pinctrl: add wakeup interrupt parent for
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 125 -
1 file changed, 121 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7c7d083e2c0d..3857aa5539e0 100644
--- a/drivers
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep low power modes and suspend.
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 31 ++-
1 file
On Tue, Nov 27 2018 at 14:45 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-11-27 10:21:23)
On Tue, Nov 27 2018 at 02:12 -0700, Stephen Boyd wrote:
>
>Two reasons. First, simplicity. The TLMM driver just needs to pass the
>gpio number up to the PDC gpio domain and then that d
On Wed, Nov 28 2018 at 17:25 -0700, Bjorn Andersson wrote:
On Wed 28 Nov 09:39 PST 2018, Lina Iyer wrote:
On Tue, Nov 27 2018 at 14:45 -0700, Stephen Boyd wrote:
> Quoting Lina Iyer (2018-11-27 10:21:23)
> > On Tue, Nov 27 2018 at 02:12 -0700, Stephen Boyd wrote:
> > >
>
Hi Ulf,
On Thu, Nov 29 2018 at 10:50 -0700, Ulf Hansson wrote:
When the hierarchical CPU topology is used and when a CPU has been put
offline (hotplug), that same CPU prevents its PM domain and thus also
potential master PM domains, from being powered off. This is because genpd
observes the CPU'
On Tue, Oct 30 2018 at 11:23 -0600, Raju P.L.S.S.S.N wrote:
Add device bindings for cpuidle states for cpu devices.
Cc:
Signed-off-by: Raju P.L.S.S.S.N
---
Changes in v2
- Address comments from Doug
---
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 62
1 file c
On Thu, Nov 29 2018 at 10:50 -0700, Ulf Hansson wrote:
Introduce a new PSCI DT helper function, psci_dt_attach_cpu(), which takes
a CPU number as an in-parameter and attaches the CPU's struct device to its
corresponding PM domain. Additionally, the helper prepares the CPU to be
power managed via
On Thu, Nov 29 2018 at 14:45 -0700, Lina Iyer wrote:
On Wed, Nov 28 2018 at 17:25 -0700, Bjorn Andersson wrote:
On Wed 28 Nov 09:39 PST 2018, Lina Iyer wrote:
On Tue, Nov 27 2018 at 14:45 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-11-27 10:21:23)
> On Tue, Nov 27 2018 at 02:12 -0
On Fri, Nov 30 2018 at 01:25 -0700, Ulf Hansson wrote:
On Thu, 29 Nov 2018 at 23:31, Lina Iyer wrote:
Hi Ulf,
On Thu, Nov 29 2018 at 10:50 -0700, Ulf Hansson wrote:
>When the hierarchical CPU topology is used and when a CPU has been put
>offline (hotplug), that same CPU prevents
to initiate the PM domain data structures, the PSCI driver shall
call the new function, psci_dt_init_pm_domains(). However, this is done
from following changes.
Cc: Lina Iyer
Co-developed-by: Lina Iyer
Signed-off-by: Ulf Hansson
---
Changes in V10:
- Enable the PM domains to be used
On Tue, Jul 10 2018 at 12:53 -0600, Evan Green wrote:
On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson
wrote:
Sorry for not getting back to you in a timely manner Evan, I wanted to
read up more on the details of how this is supposed to work. I still
haven't done so, but here's my concern:
When
Hi Doug,
On Thu, May 10 2018 at 16:37 -0600, Doug Anderson wrote:
Hi,
On Tue, May 8, 2018 at 9:05 AM, wrote:
On 2018-05-03 14:26, Doug Anderson wrote:
Hi Doug,
Hi,
On Wed, May 2, 2018 at 12:37 PM, Lina Iyer wrote:
+static struct rpmh_ctrlr rpmh_rsc[RPMH_MAX_CTRLR];
+static
On Fri, May 11 2018 at 14:14 -0600, Doug Anderson wrote:
Hi,
On Fri, May 11, 2018 at 8:06 AM, Lina Iyer wrote:
As I've said I haven't reviewed RPMh in any amount of detail and so
perhaps I don't understand something.
OK, I dug a little more and coded up something for you. B
Hi Doug,
Will explain only the key points now.
On Fri, May 11 2018 at 14:19 -0600, Doug Anderson wrote:
Hi,
On Wed, May 9, 2018 at 10:01 AM, Lina Iyer wrote:
/**
@@ -77,12 +82,14 @@ struct rpmh_request {
* @cache: the list of cached requests
* @lock: synchronize access to the
On Mon, Jun 18 2018 at 07:37 -0600, Raju P L S S S N wrote:
From: Lina Iyer
Sending RPMH requests and waiting for response from the controller
through a callback is common functionality across all platform drivers.
To simplify drivers, add a library functions to create RPMH client and
send
On Mon, Jun 18 2018 at 11:23 -0600, Douglas Anderson wrote:
Children of RPMh will need access to cmd_db. Rather than having each
child have code to check if cmd_db is ready let's add the check to
RPMh.
Suggested-by: Stephen Boyd
Signed-off-by: Douglas Anderson
Acked-by: Lina Iyer
---
On Mon, Jun 18 2018 at 12:33 -0600, Doug Anderson wrote:
Lina,
On Mon, Jun 18, 2018 at 9:39 AM, Lina Iyer wrote:
+/**
* struct rsc_drv: the Direct Resource Voter (DRV) of the
* Resource State Coordinator controller (RSC)
*
@@ -52,6 +78,7 @@ struct tcs_group {
* @tcs:TCS groups
On Mon, Jun 18 2018 at 13:54 -0600, Doug Anderson wrote:
Hi,
On Mon, Jun 18, 2018 at 12:06 PM, Lina Iyer wrote:
On Mon, Jun 18 2018 at 12:33 -0600, Doug Anderson wrote:
Lina,
On Mon, Jun 18, 2018 at 9:39 AM, Lina Iyer wrote:
+/**
* struct rsc_drv: the Direct Resource Voter (DRV) of the
On Mon, Jun 18 2018 at 14:56 -0600, Douglas Anderson wrote:
This adds the rpmh-rsc node to sdm845 based on the examples in the
bindings.
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/b
Thanks for the quick spin Doug.
On Mon, Jun 18 2018 at 15:51 -0600, Douglas Anderson wrote:
This adds the rpmh-rsc node to sdm845 based on the examples in the
bindings.
Signed-off-by: Douglas Anderson
Reviewed-by: Lina Iyer
---
Changes in v2:
- Fixed ordering of tcs-config as per Lina
On Fri, May 25 2018 at 19:08 -0600, David Collins wrote:
Hello Rajendra,
On 05/25/2018 03:01 AM, Rajendra Nayak wrote:
+
+ to_active_sleep(pd, pd->corner, &this_corner, &this_sleep_corner);
+
+ if (peer && peer->enabled)
+ to_active_sleep(peer, peer->corner, &peer_corn
On Wed, Jun 13 2018 at 15:09 -0600, Doug Anderson wrote:
Hi,
On Mon, Jun 11, 2018 at 10:25 AM, Raju P L S S S N
wrote:
@@ -148,7 +148,8 @@ int rpmh_rsc_invalidate(struct rsc_drv *drv)
static struct tcs_group *get_tcs_for_msg(struct rsc_drv *drv,
const
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 24e254efb9d1..399bfbd52c5b
Adding Ram, so he can respond.
-- Lina
On Thu, Jul 26 2018 at 02:55 -0600, Zhang Rui wrote:
On δΈ€, 2018-05-07 at 11:55 -0600, Lina Iyer wrote:
From: Ram Chandrasekar
Let userspace be another voter for cooling device state instead of
the
overriding authority. It is possible that the thermal
On Wed, Aug 15 2018 at 09:28 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-14 10:30:58)
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64
s.
Reported-by: Lina Iyer
Signed-off-by: Marc Zyngier
---
Lina, please let me know how this goes. If that fixes your issues,
I'll queue it as a fix for the current cycle.
Thanks for the quick turn around, Marc.
Tested-by: Lina Iyer
drivers/irqchip/irq-gic-v3.c | 8 ++--
1 file c
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-
com-pdc.c
[2]. Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
[3]. drivers/pinctrl/qcom/pinctrl-msm.c
Lina Iyer (5):
drivers: pinctrl: qcom: add wakeup capability to GPIO
dt-bindings: pinctrl: add wakeup capable GPIOs for SDM845
drivers: pinctrl: msm: enable PDC interrupt o
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 58 ++-
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use interrupt-extended for all
layed again.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Trigger GPIO in h/w from PDC IRQ ha
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-
From: Marc Zyngier
Although GICv3 doesn't directly offers support for wake-up interrupts
and relies on external HW for this, it shouldn't prevent the driver
for such HW from doing it work.
Let's set the required flags on the irq_chip structures.
Reported-by: Lina Iyer
Sign
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use interrupt-extended for all
eatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
[3]. drivers/pinctrl/qcom/pinctrl-msm.c
*** BLURB HERE ***
Lina Iyer (4):
dt-bindings: pinctrl: add wakeup capable GPIOs for SDM845
drivers: pinctrl: msm: enab
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 58 ++-
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845
Please ignore this series. The series is incorrectly marked as v2. I am
resending it as v1.
On Fri, Aug 17 2018 at 10:39 -0600, Lina Iyer wrote:
Hi,
Changes in v1:
- Avoid GPIO-PDC map in .c file
- Trigger GPIO by writing to the hardware
- Hooked up to suspend/resume
On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote:
Hi Lina,
On Fri, 17 Aug 2018 20:10:23 +0100,
Lina Iyer wrote:
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected
On Mon, Aug 20 2018 at 09:34 -0600, Marc Zyngier wrote:
On 20/08/18 16:26, Lina Iyer wrote:
On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote:
Hi Lina,
On Fri, 17 Aug 2018 20:10:23 +0100,
Lina Iyer wrote:
[...]
@@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data
On Mon, Dec 03 2018 at 16:48 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-11-30 10:33:17)
On Thu, Nov 29 2018 at 14:45 -0700, Lina Iyer wrote:
>On Wed, Nov 28 2018 at 17:25 -0700, Bjorn Andersson wrote:
>>On Wed 28 Nov 09:39 PST 2018, Lina Iyer wrote:
>>
>>>On T
l.org/lkml/2018/11/21/168
Lina Iyer (5):
irqdomain: add bus token DOMAIN_BUS_WAKEUP
dt-bindings: sdm845-pinctrl: add wakeup interrupt parent for GPIO
drivers: pinctrl: msm: setup GPIO irqchip hierarchy
arm64: dts: msm: add PDC device bindings for sdm845
arm64: dts: msm: setup PDC as wakeup
ve as well as the
TLMM and therefore the GPIOs need to be masked at TLMM to avoid
duplicate interrupts. To enable both these configurations to exist,
allow the parent irqchip to dictate the TLMM irqchip's behavior when
masking/unmasking the interrupt.
Signed-off-by: Stephen Boyd
Signed-of
Add PDC wakeup parent for TLMM for SDM845 SoC.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8e15392a6f64..40dca655ba86 100644
--- a/arch
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Fix PDC map, use GIC SPI port number for hwirq
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
Add new bus token to describe domains that are wakeup capable.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
include/linux/irqdomain.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index 068aa46f0d55..b9ea3c3998e2 100644
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep low power modes and suspend.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/pinctrl/qcom,sdm845
PDC interrupt as its parent.
Also, provide the map of the PDC pins for the GPIOs for SDM845.
Signed-off-by: Stephen Boyd
Signed-off-by: Lina Iyer
[ilina: create separate file for PDC data]
---
drivers/irqchip/Makefile| 2 +-
drivers/irqchip/qcom-pdc-data.c | 94
From: Thierry Reding
Hierarchical IRQ domains can be used to stack different IRQ controllers
on top of each other. One specific use-case where this can be useful is
if a power management controller has top-level controls for wakeup
interrupts. In such cases, the power management controller can be
On Thu, Dec 20 2018 at 14:42 -0700, Doug Anderson wrote:
Hi,
On Fri, Nov 30, 2018 at 7:41 AM Lina Iyer wrote:
On Tue, Oct 30 2018 at 11:23 -0600, Raju P.L.S.S.S.N wrote:
>Add device bindings for cpuidle states for cpu devices.
>
>Cc:
>Signed-off-by: Raju P.L.S.S.S.N
>---
On Thu, Dec 20 2018 at 13:19 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-12-19 14:11:01)
diff --git a/drivers/irqchip/qcom-pdc-data.c b/drivers/irqchip/qcom-pdc-data.c
new file mode 100644
index ..99b4be0af5db
--- /dev/null
+++ b/drivers/irqchip/qcom-pdc-data.c
@@ -0,0 +1,94
On Fri, Dec 28 2018 at 17:07 -0700, Rob Herring wrote:
On Wed, Dec 19, 2018 at 03:11:02PM -0700, Lina Iyer wrote:
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep low power modes and suspend
On Thu, Dec 20 2018 at 11:14 -0700, Doug Anderson wrote:
Hi,
On Wed, Dec 19, 2018 at 2:11 PM Lina Iyer wrote:
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Fix PDC map, use GIC SPI port number for hwirq
Changes in v2
On Thu, Dec 20 2018 at 13:03 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-12-19 14:11:03)
To allow GPIOs to wakeup the system from suspend or deep idle, the
wakeup capable GPIOs are setup in hierarchy with interrupts from the
wakeup-parent irqchip.
In older SoC's, the TLMM will han
queue and
completes each message instead of tracking the last inserted message and
completing that first.
Cc: Lina Iyer
Cc: "Raju P.L.S.S.S.N"
Cc: Matthias Kaehlcke
Cc: Evan Green
Fixes: c8790cb6da58 ("drivers: qcom: rpmh: add support for batch RPMH request")
Signed-of
On Tue, Oct 02 2018 at 11:06 -0600, Lina Iyer wrote:
Marc,
I am exploring an option where we don't do this enable/disable every
suspend/resume and in that process, I was able to just use the PDC
interrupt instead of the TLMM for triggering the GPIO. The PDC interrupt
(which takes over fo
see any
issues that I may have missed.
Thanks,
Lina
[1]. https://lkml.org/lkml/2018/9/4/846
Lina Iyer (1):
drivers: pinctrl: qcom: add wakeup capability to GPIO
drivers/pinctrl/qcom/pinctrl-msm.c | 91 +-
1 file changed, 90 insertions(+), 1 deletion(-)
--
The
again.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v4:
- Redesign to use PDC interrupts instead of
On Wed, Oct 31 2018 at 01:05 -0600, Stephen Boyd wrote:
Hi Lina,
Quoting Lina Iyer (2018-10-10 17:29:58)
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs
On Wed, Oct 31 2018 at 01:05 -0600, Stephen Boyd wrote:
Hi Lina,
Quoting Lina Iyer (2018-10-10 17:29:58)
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Fix PDC map, use GIC SPI port number for hwirq
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
The PDC map should use the GIC SPI port and not the vector. GIC
internally adds 32 to SPI hwirq numbers.
Fixes: 1ae8862e27e ("dt-bindings/interrupt-controller: pdc: Describe PDC device
binding")
Reviewed-by: Rob Herring
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/interrupt-
On Mon, Nov 05 2018 at 22:19 -0700, Stephen Boyd wrote:
Quoting Lina Iyer (2018-11-01 10:16:30)
On Wed, Oct 31 2018 at 18:13 -0600, Stephen Boyd wrote:
>
[...]
Ok. I don't see why we need to limit ourselves here. If a GPIO interrupt
isn't routed through PDC physically why does
Sudeep,
This is idea is based on GenPD/PM Domains, but solves for the CPU domain
activities that need to be done from Linux when the CPU domain could be
powered off. In that, it shares the same ideas from the series posted by
Ulf. But this has no bearing on PSCI. The 845 SoC that Raju is working
On Thu, Oct 11 2018 at 10:19 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 10:00:53AM -0600, Lina Iyer wrote:
Sudeep,
The CPU PD does not power off the domain from Linux. That is done from
PSCI firmware (ATF). These patches are doing the part that Linux has do,
when powering off the CPUs
On Thu, Oct 11 2018 at 11:37 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 10:58:22AM -0600, Lina Iyer wrote:
On Thu, Oct 11 2018 at 10:19 -0600, Sudeep Holla wrote:
> On Thu, Oct 11, 2018 at 10:00:53AM -0600, Lina Iyer wrote:
> > Sudeep,
> >
> > The CPU PD does not
nt, via calling
pm_runtime_get_sync().
Cc: Lina Iyer
Co-developed-by: Lina Iyer
Signed-off-by: Ulf Hansson
Signed-off-by: Raju P.L.S.S.S.N
(am from https://patchwork.kernel.org/patch/10478153/)
---
kernel/cpu_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/kernel/cpu_pm.c b/kernel/cpu_pm.
On Fri, Oct 12 2018 at 01:43 -0600, Rafael J. Wysocki wrote:
On Fri, Oct 12, 2018 at 12:08 AM Lina Iyer wrote:
On Thu, Oct 11 2018 at 14:56 -0600, Rafael J. Wysocki wrote:
>On Wednesday, October 10, 2018 11:20:49 PM CEST Raju P.L.S.S.S.N wrote:
>> From: Ulf Hansson
The clust
On Fri, Oct 12 2018 at 09:04 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 03:06:09PM -0600, Lina Iyer wrote:
On Thu, Oct 11 2018 at 11:37 -0600, Sudeep Holla wrote:
[...]
>
> Is DDR managed by Linux ? I assumed it was handled by higher exception
> levels. Can you give ex
On Fri, Oct 12 2018 at 09:46 -0600, Ulf Hansson wrote:
On 12 October 2018 at 17:04, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 03:06:09PM -0600, Lina Iyer wrote:
On Thu, Oct 11 2018 at 11:37 -0600, Sudeep Holla wrote:
[...]
>
> Is DDR managed by Linux ? I assumed it was handled by
On Fri, Oct 12 2018 at 11:01 -0600, Sudeep Holla wrote:
On Fri, Oct 12, 2018 at 10:04:27AM -0600, Lina Iyer wrote:
On Fri, Oct 12 2018 at 09:04 -0600, Sudeep Holla wrote:
[...]
Yes all these are fine but with multiple power-domains/cluster, it's
hard to determine the first CPU. You m
On Fri, Oct 12 2018 at 11:35 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 02:50:55AM +0530, Raju P.L.S.S.S.N wrote:
Add cpu power domain support
Signed-off-by: Raju P.L.S.S.S.N
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/ar
On Wed, Oct 31 2018 at 18:13 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-10-31 09:46:50)
On Wed, Oct 31 2018 at 01:05 -0600, Stephen Boyd wrote:
>Hi Lina,
>
>Quoting Lina Iyer (2018-10-10 17:29:58)
>> QCOM SoC's that have Power Domain Controller (PDC) chip in the alw
to be sent
only during entry of deeper system low power modes or suspend.
[1]https://patchwork.kernel.org/patch/10477533/
nit: [1] https://
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
drivers/soc/qcom/rpmh.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a
bit() in IRQ handler. clear_bit() is
atomic.
- Remove redundant read of TCS registers.
- Use spin_lock instead of _irq variants as the locks are not held
in interrupt context
Suggested-by: Lina Iyer
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
This patch is based on https://lkml.o
On Wed, Oct 24 2018 at 11:43 -0600, Evan Green wrote:
On Mon, Oct 8, 2018 at 7:09 PM Raju P.L.S.S.S.N wrote:
From: Lina Iyer
Controllers may be in 'solver' state, where they could be in autonomous
mode executing low power modes for their hardware and as such are not
available f
On Mon, Oct 22 2018 at 03:27 -0600, Marc Zyngier wrote:
On Fri, 19 Oct 2018 20:47:12 +0100,
Lina Iyer wrote:
On Fri, Oct 19 2018 at 09:53 -0600, Marc Zyngier wrote:
> Hi Lina,
>
> On 19/10/18 16:32, Lina Iyer wrote:
>> Hi folks,
>>
>> On Wed, Oct 10 2018 at 1
Hi folks,
On Wed, Oct 10 2018 at 18:30 -0600, Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs that are deemed wakeup capable
are rout
On Fri, Oct 19 2018 at 09:53 -0600, Marc Zyngier wrote:
Hi Lina,
On 19/10/18 16:32, Lina Iyer wrote:
Hi folks,
On Wed, Oct 10 2018 at 18:30 -0600, Lina Iyer wrote:
[...]
+static irqreturn_t wake_irq_gpio_handler(int irq, void *data)
+{
+ struct irq_data *irqd = data;
+ struct
On Mon, Oct 15 2018 at 11:02 -0600, Raju P.L.S.S.S.N wrote:
Add device bindings for cpuidle states for cpu devices.
Cc:
Signed-off-by: Raju P.L.S.S.S.N
---
Reviewed-by: Lina Iyer
arch/arm64/boot/dts/qcom/sdm845.dtsi | 62
1 file changed, 62 insertions
On Fri, Oct 12 2018 at 11:25 -0600, Sudeep Holla wrote:
On Fri, Oct 12, 2018 at 11:19:10AM -0600, Lina Iyer wrote:
On Fri, Oct 12 2018 at 11:01 -0600, Sudeep Holla wrote:
> On Fri, Oct 12, 2018 at 10:04:27AM -0600, Lina Iyer wrote:
> > On Fri, Oct 12 2018 at 09:04 -0600, Sudeep Ho
f02d34 ("drivers: qcom: rpmh-rsc: allow invalidation
of sleep/wake TCS")
Reported-by: Dan Carpenter
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/rpmh-rsc.c
On Wed, Mar 18 2015 at 12:46 -0600, Daniel Lezcano wrote:
Some architectures have some cpus which does not support idle states.
Let the underlying low level code to return -ENOSYS when it is not
possible to set an idle state.
Signed-off-by: Daniel Lezcano
---
drivers/cpuidle/cpuidle-arm.c | 45
On Thu, Mar 19 2015 at 09:33 -0600, Daniel Lezcano wrote:
On 03/19/2015 04:31 PM, Lina Iyer wrote:
On Wed, Mar 18 2015 at 12:46 -0600, Daniel Lezcano wrote:
Some architectures have some cpus which does not support idle states.
Let the underlying low level code to return -ENOSYS when it is not
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