Am Dienstag, den 23.10.2012, 12:49 +0530 schrieb Pavan Kunapuli:
vmmc and vqmmc regulators control the voltage to
the host and device. Defer the probe if either of
them is not registered.
Does this work with boards where we don't have any MMC supplies? Or are
we just deferring the probe
Dropping Tegra ML, it's not the place where Nouveau mails should go.
Adding Nouveau ML and Maarten, who probably knows Lockdep+Nouveau best.
Am Montag, den 04.03.2013, 22:16 +0100 schrieb Borislav Petkov:
New -rc1, so let the stabilization games begin.
I see the following on rc1, let me know
Am Freitag, den 30.11.2012, 09:44 +0200 schrieb Terje Bergström:
On 29.11.2012 14:14, Thierry Reding wrote:
On Thu, Nov 29, 2012 at 10:09:13AM +0100, Lucas Stach wrote:
This way you would also be able to construct different handles (like GEM
obj or V4L2 buffers) from the same backing nvhost
Am Donnerstag, den 29.11.2012, 11:38 -0700 schrieb Stephen Warren:
On 11/29/2012 04:47 AM, Thierry Reding wrote:
I agree. But I also fear that there will be changes eventually and
having both go in via different tree requires those trees to be
merged in a specific order to avoid breakage
Am Samstag, den 01.12.2012, 18:55 +0200 schrieb Terje Bergström:
On 01.12.2012 17:10, Thierry Reding wrote:
On Sat, Dec 01, 2012 at 01:44:41PM +0200, Terje Bergström wrote:
host1x module being in DRM directory hinders using nvhost from anywhere
outside DRM in both upstream and downstream.
Am Mittwoch, den 05.12.2012, 13:47 +0200 schrieb Terje Bergström:
[...]
The problem that this solves is that the DRM driver needs to be bound to
a specific platform device. None of the DRM subdevices are suitable
because they are only part of the whole DRM device. I think that host1x
is
Am Dienstag, den 27.11.2012, 10:45 +0200 schrieb Terje Bergström:
On 27.11.2012 10:32, Dave Airlie wrote:
On Tue, Nov 27, 2012 at 8:16 AM, Terje Bergström tbergst...@nvidia.com
wrote:
Thanks for the pointer, I looked at exynos code. It indeed checks the
registers written to, but it
Am Dienstag, den 27.11.2012, 13:31 +0200 schrieb Terje Bergström:
On 27.11.2012 12:37, Thierry Reding wrote:
But in that case it should be made mandatory at first until proper IOMMU
support is enabled on Tegra30. Then it can be checked at driver probe
time whether or not to enable the extra
Am Mittwoch, den 28.11.2012, 15:17 +0200 schrieb Terje Bergström:
On 28.11.2012 01:00, Dave Airlie wrote:
We generally aim for the first, to stop the gpu from reading/writing
any memory it hasn't been granted access to,
the second is nice to have though, but really requires a GPU with VM
Am Mittwoch, den 28.11.2012, 15:57 +0200 schrieb Terje Bergström:
On 28.11.2012 15:33, Lucas Stach wrote:
So this is obviously wrong. Userspace has to allocate a pushbuffer from
the kernel just as every other buffer, then map it into it's own address
space to push in commands. At submit
Am Mittwoch, den 28.11.2012, 16:45 +0200 schrieb Terje Bergström:
On 28.11.2012 16:06, Lucas Stach wrote:
Why do even need/use dma-buf for this use case? This is all one DRM
device, even if we separate host1x and gr2d as implementation modules.
I didn't want to implement dependency to drm
Am Mittwoch, den 28.11.2012, 18:23 +0200 schrieb Terje Bergström:
On 28.11.2012 17:13, Lucas Stach wrote:
To be honest I still don't grok all of this, but nonetheless I try my
best.
Sorry. I promised in another thread a write-up explaining the design. I
still owe you guys
Am Donnerstag, den 29.11.2012, 10:17 +0200 schrieb Terje Bergström:
On 28.11.2012 20:46, Lucas Stach wrote:
Am Mittwoch, den 28.11.2012, 18:23 +0200 schrieb Terje Bergström:
Sorry. I promised in another thread a write-up explaining the design. I
still owe you guys that.
That would
Am Freitag, den 21.12.2012, 13:39 +0200 schrieb Terje Bergstrom:
This set of patches adds support for Tegra20 and Tegra30 host1x and
2D. It is based on linux-next-20121220.
The fourth version has only few changes compared to previous version:
* Fixed some sparse warnings
* Fixed host1x
Am Freitag, den 21.12.2012, 13:39 +0200 schrieb Terje Bergstrom:
Register a dummy device for tegradrm, and provide a getter to
access the device.
Signed-off-by: Terje Bergstrom tbergst...@nvidia.com
---
[...]
diff --git a/drivers/gpu/host1x/drm.c b/drivers/gpu/host1x/drm.c
new file mode
Am Freitag, den 21.12.2012, 15:57 +0200 schrieb Terje Bergström:
On 21.12.2012 15:50, Lucas Stach wrote:
This has to be resolved before merging. Personally I'm in favour of
keeping reg access patterns close to what is done in other parts of the
kernel.
I haven't so far received comments
Hello Dave,
Am Sonntag, den 30.12.2012, 04:23 + schrieb Dave Airlie:
Hi Linus,
[...]
Lucas Stach (6):
drm: tegra: protect DC register access with mutex
This patch is unnecessary and really shouldn't go in. There
was a brief discussion on the list with the conclusion
Hi Terje,
Am Donnerstag, den 13.12.2012, 16:04 +0200 schrieb Terje Bergstrom:
This set of patches adds support for Tegra20 and Tegra30 host1x and
2D. It is based on linux-next.
The third version has too many changes to list all of them. Here are
highlights:
* Renamed to host1x, and moved
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Am Dienstag, den 06.08.2013, 10:14 -0400 schrieb Rob Clark:
On Tue, Aug 6, 2013 at 8:18 AM, Lucas Stach l.st...@pengutronix.de wrote:
Am Dienstag, den 06.08.2013, 12:31 +0100 schrieb Tom Cooksey:
Hi Rob,
+lkml
On Fri, Jul 26, 2013 at 11:58 AM, Tom Cooksey tom.cook...@arm.com
Am Freitag, den 21.06.2013, 10:24 -0600 schrieb Stephen Warren:
On 06/20/2013 03:08 PM, Anna-Maria Gleixner wrote:
The nvidia,tristate entry for the pinmux of i2c1 an i2c3 was set to
tristate. This results in non working i2c, because the i2c pins are
not actively driven. Set the entries to
{
+compatible = fsl,sgtl5000;
+reg = 0x0a;
+clocks = clks VF610_CLK_SAI2;
+ };
+};
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as the next
string and not need to invent generic and unspecific comms-ssc-i2c-v2
compatibles.
Regards,
Lucas
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;
+ regulator-max-microvolt = 180;
regulator-always-on;
};
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Peiner
Am Mittwoch, den 27.11.2013, 12:05 +0100 schrieb Stefan Agner:
Hi Lucas,
Am 2013-11-27 10:59, schrieb Lucas Stach:
This isn't a global Tegra change, but very specific to the Colibri, so
please reword your commit headline to reflect that.
Agree, will do that.
Also there are other
everyone so far is
able to use DTs bundled with the kernel.
Regards,
Lucas
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.
LDO6 should deliver 2.85V. The attached peripherals were not in
use so far.
Signed-off-by: Stefan Agner ste...@agner.ch
Reviewed-by: Lucas Stach l.st...@pengutronix.de
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 30
+++---
1 file changed, 15 insertions
forward. I'm currently porting
the Tegra NAND drive to mainline and at least the OF ONFI mode and ONFI
mode to timing converter parts of this series are really helpful.
Regards,
Lucas
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agree with the reasoning here.
Though it would be nice to have this expected driver behavior put down
somewhere in the documentation. Any volunteers?
Regards,
Lucas
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for all the other potential crystal rates too?
The TRM states that PCIe and thus PLLE are only supported with 12MHz
external crystal rate.
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with the last watchdog that
registers a handler wins the system reset logic in your patch.
Regards,
Lucas
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Am Mittwoch, den 07.05.2014, 06:01 -0700 schrieb Guenter Roeck:
On 05/07/2014 04:52 AM, Lucas Stach wrote:
Hi Guenter,
Am Freitag, den 02.05.2014, 21:29 -0700 schrieb Guenter Roeck:
On Fri, May 02, 2014 at 06:22:43PM -0700, Maxime Ripard wrote:
Hi Guenter,
On Thu, May 01, 2014 at 08
voltages.
To make this function behave as expected employ the same logic
as used when calling set_voltage() and round the voltages to
the closest matching voltage supported by the regulator.
Signed-off-by: Lucas Stach l.st...@pengutronix.de
---
drivers/regulator/core.c | 11 +++
1 file changed
Am Mittwoch, den 21.05.2014, 18:53 +0200 schrieb Lucas Stach:
Currently this function only provides a valid output if both
old_uV and new_uV are exact voltages that can be provided by the
regulator.
This is almost impossible to achive as the consumer has
no way to know the exact voltages
Am Freitag, den 23.05.2014, 16:10 +0900 schrieb Alexandre Courbot:
On Mon, May 19, 2014 at 7:16 PM, Lucas Stach l.st...@pengutronix.de wrote:
Am Montag, den 19.05.2014, 19:06 +0900 schrieb Alexandre Courbot:
On 05/19/2014 06:57 PM, Lucas Stach wrote:
Am Montag, den 19.05.2014, 18:46 +0900
Am Freitag, den 23.05.2014, 18:43 +0900 schrieb Alexandre Courbot:
On 05/23/2014 06:24 PM, Lucas Stach wrote:
Am Freitag, den 23.05.2014, 16:10 +0900 schrieb Alexandre Courbot:
On Mon, May 19, 2014 at 7:16 PM, Lucas Stach l.st...@pengutronix.de
wrote:
Am Montag, den 19.05.2014, 19:06
nouveau is reading back a lot from those
buffers.
Using the write-combining buffer doesn't need any additional
synchronization as it will get flushed on pushbuf kickoff anyways.
Regards,
Lucas
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Am Montag, den 19.05.2014, 16:10 +0900 schrieb Alexandre Courbot:
From: Lucas Stach d...@lynxeye.de
Signed-off-by: Lucas Stach d...@lynxeye.de
[acour...@nvidia.com: make conditional and platform-friendly]
Signed-off-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpu/drm/nouveau
Am Montag, den 19.05.2014, 10:46 +0200 schrieb Thierry Reding:
On Mon, May 19, 2014 at 04:10:57PM +0900, Alexandre Courbot wrote:
From: Lucas Stach d...@lynxeye.de
Signed-off-by: Lucas Stach d...@lynxeye.de
[acour...@nvidia.com: make conditional and platform-friendly]
Signed-off
-default_caching = TTM_PL_FLAG_UNCACHED;
+#else
man-default_caching = TTM_PL_FLAG_WC;
+#endif
break;
case TTM_PL_TT:
if (nv_device(drm-device)-card_type = NV_50)
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/nvidia,gk20a.txt
create mode 100644 drivers/gpu/drm/nouveau/nouveau_platform.c
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Am Montag, den 19.05.2014, 19:06 +0900 schrieb Alexandre Courbot:
On 05/19/2014 06:57 PM, Lucas Stach wrote:
Am Montag, den 19.05.2014, 18:46 +0900 schrieb Alexandre Courbot:
This patch is not meant to be merged, but rather to try and understand
why this is needed and what a more suitable
Am Sonntag, den 01.06.2014, 12:38 +0100 schrieb Mark Brown:
On Wed, May 21, 2014 at 06:53:59PM +0200, Lucas Stach wrote:
Currently this function only provides a valid output if both
old_uV and new_uV are exact voltages that can be provided by the
regulator.
This is almost impossible
Am Montag, den 26.05.2014, 09:45 +0300 schrieb Terje Bergström:
On 23.05.2014 17:40, Alex Courbot wrote:
On 05/23/2014 06:59 PM, Lucas Stach wrote:
So after checking with more knowledgeable people, it turns out this is
the expected behavior on ARM and BAR regions should be mapped uncached
Am Samstag, den 01.02.2014, 12:16 +0900 schrieb Alexandre Courbot:
Add a clumsy-but-working FB support for GK20A. This chip only uses system
memory, so we allocate a big chunk using CMA and let the existing memory
managers work on it.
A better future design would be to allocate objects
Am Samstag, den 01.02.2014, 18:28 -0500 schrieb Ilia Mirkin:
On Sat, Feb 1, 2014 at 8:40 AM, Lucas Stach d...@lynxeye.de wrote:
Am Samstag, den 01.02.2014, 12:16 +0900 schrieb Alexandre Courbot:
Add a clumsy-but-working FB support for GK20A. This chip only uses system
memory, so we allocate
display.
Regards,
Lucas
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Am Donnerstag, den 08.08.2013, 19:41 +0530 schrieb Viresh Kumar:
On 8 August 2013 19:28, Lucas Stach l.st...@pengutronix.de wrote:
From what I learned those voltage levels are dependent on both the
Speedo and the process ID of the specific Tegra processor. So you really
get a two
the perf increase may be even better with a more
adequate interconnect.
Regards,
Lucas
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Hi Alexandre,
Am Mittwoch, den 26.03.2014, 15:33 +0900 schrieb Alexandre Courbot:
Hi Lucas,
On Mon, Mar 24, 2014 at 10:19 PM, Lucas Stach l.st...@pengutronix.de wrote:
Hi Alexandre,
Am Montag, den 24.03.2014, 17:42 +0900 schrieb Alexandre Courbot:
Hi everyone,
[...]
A few lines
.
Regards,
Lucas
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power domain code.
Regards,
Lucas
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of
the invalidate overhead especially for userspace suballocated buffers.
Regards,
Lucas
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.
Regards,
Lucas
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Linux wrote:
On Tue, Jun 24, 2014 at 06:54:26PM +0900, Alexandre Courbot wrote:
From: Lucas Stach d...@lynxeye.de
On architectures for which access to GPU memory is non-coherent,
caches need to be flushed and invalidated explicitly at the
appropriate places. Introduce two small helpers
Am Dienstag, den 24.06.2014, 22:52 +0900 schrieb Alexandre Courbot:
On Tue, Jun 24, 2014 at 10:25 PM, Lucas Stach l.st...@pengutronix.de wrote:
Am Dienstag, den 24.06.2014, 14:27 +0200 schrieb Maarten Lankhorst:
op 24-06-14 14:23, Alexandre Courbot schreef:
On Tue, Jun 24, 2014 at 7:55 PM
around. If the MFD has subdev information
stored in the parent node it should be the MFD drivers responsibility to
populate the subdev of_node with its own node. The subdev should not be
forced to make such possible unsafe assumptions.
Regards,
Lucas
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to
allocate single pages from CMA on x86, on ARM the CMA pool is the only
way to get lowmem pages on which you are allowed to change the caching
state.
So the obvious fix is to avoid CMA for order 0 allocations on x86. I can
cook a patch for this.
Regards,
Lucas
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input and output buffers
simultaneously.
Regards,
Lucas
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;
- dma-names = rx, tx;
status = disabled;
};
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are eating CPU cycles here for no good reason.
Could you please explain where you see the benefit of using strings
instead of plain integers with proper binding defines attached to them?
Regards,
Lucas
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Please read
);
imx_anatop_init();
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
--
1.9.3
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different in that
regard from any other device. This should work for all platforms AFAICS.
Regards,
Lucas
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, but it's not there, so we have to cope with
this.
So I'm afraid that we have to break the old DTs in the gap between the two
levels patch accepted cycle.
On Mon, Sep 15, 2014 at 11:41:13AM +0200, Lucas Stach wrote:
Am Mittwoch, den 10.09.2014, 13:30 +0800 schrieb Robin Gong:
There is one
Am Mittwoch, den 17.09.2014, 16:41 +0800 schrieb Robin Gong:
On Tue, Sep 16, 2014 at 11:50:06AM +0200, Lucas Stach wrote:
Hi Robin,
Am Dienstag, den 16.09.2014, 11:41 +0800 schrieb Robin Gong:
Hi Lucas,
I understood your concern,but looks we have to break old DT.
Sorry
Am Mittwoch, den 17.09.2014, 17:19 +0800 schrieb Robin Gong:
On Wed, Sep 17, 2014 at 10:55:56AM +0200, Lucas Stach wrote:
Am Mittwoch, den 17.09.2014, 16:41 +0800 schrieb Robin Gong:
On Tue, Sep 16, 2014 at 11:50:06AM +0200, Lucas Stach wrote:
Hi Robin,
Am Dienstag, den
() in the 3.18 cycle
and I would think it would be no problem to to the same with rcar.
Regards,
Lucas
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be taken if the property is present in DT but has any
other value than 1 or 4, which is an error.
Regards,
Lucas
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solution to not change behavior on old bootloaders, while providing
a fixed numbering for the serial ports.
Regards,
Lucas
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argue to just
drop the #ifdef.
Regards,
Lucas
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Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
This patch adds some missing pieces of the rail gaing/ungating sequence that
can improve the stability in theory.
Signed-off-by: Vince Hsu vin...@nvidia.com
---
drm/nouveau_platform.c | 42
Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
The Tegra124 and later Tegra SoCs have a sepatate rail gating register
to enable/disable the clamp. The original function
tegra_powergate_remove_clamping() is not sufficient for the enable
function. So add a new function which is
Am Donnerstag, den 25.12.2014, 10:28 +0800 schrieb Vince Hsu:
On 12/24/2014 09:16 PM, Lucas Stach wrote:
Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu:
The Tegra124 and later Tegra SoCs have a sepatate rail gating register
to enable/disable the clamp. The original function
Am Montag, den 29.12.2014, 10:49 +0800 schrieb Vince Hsu:
[...]
That's a read fence to assure the post of the previous writes through
Tegra interconnect. (copy-paster from
https://android.googlesource.com/kernel/tegra.git/+/28b107dcb3aa122de8e94e48af548140d519298f)
I see what it does,
-ops;
c = rdev-constraints;
- if (c c-always_on)
+ if (c (c-always_on || c-boot_on))
continue;
if (c !(c-valid_ops_mask REGULATOR_CHANGE_STATUS))
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);
// error handling
}
Also the DT binding doc for this property is missing.
Regards,
Lucas
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/* ifndef CONFIG_CPU_V7M */
/*
* on V7-M there is no need to copy the vector table to a dedicated
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);
clk_prepare_enable(imx_data-clk_ahb);
return sdhci_runtime_resume_host(host);
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the hardware or waiting for the hardware here so why is it needed? I don't
have Exynos based hardware lying
around through to test it.
If you can't test it, don't touch it. It's that simple.
Regards,
Lucas
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0x4800 0 0x0001 /*
downstream I/O */
+ 0x8200 0 0x4000 0x4000 0 0x0400; /*
non-prefetchable memory */
+ phy-addr = 6;
+ };
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Am Mittwoch, den 21.01.2015, 20:35 +0100 schrieb Arnd Bergmann:
On Wednesday 21 January 2015 16:47:36 Gabriel Fernandez wrote:
On 19 January 2015 at 14:49, Arnd Bergmann a...@arndb.de wrote:
On Monday 19 January 2015 13:37:33 Gabriel Fernandez wrote:
On 17 December 2014 at 23:14, Arnd
e.K. | Lucas Stach |
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)
is the control weather a master should go through the M4U unit for
translation or bypass it and talk directly to external memory
controller.
Regards,
Lucas
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Use the libpci helper pci_filter_init() to fix this and guard against
similar breakages in the future.
This fixes probing of the AMD fam12h/14h cpuidle monitor on systems
with libpci = 3.3.0.
Signed-off-by: Lucas Stach d...@lynxeye.de
---
tools/power/cpupower/utils/helpers/pci.c | 11
So, who is going to pick up this patch?
Regards,
Lucas
Am Dienstag, den 14.04.2015, 18:28 +0200 schrieb Thomas Renninger:
Hi,
On Monday, April 13, 2015 10:24:01 PM Lucas Stach wrote:
libpci 3.3.0 introduced an additional member in the pci_filter struct
which needs to be initialized to -1
importantly it fixes the resulting memory corruption.
Signed-off-by: Lucas Stach d...@lynxeye.de
---
This is an important fix and should go into 4.1.
---
drivers/irqchip/irq-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq
-enabled inadvertently when
new events are coming in.
This makes the irqsoff latency tracer useful again, as we stop
capturing CPU sleep time as IRQ latency.
Signed-off-by: Lucas Stach l.st...@pengutronix.de
---
drivers/cpuidle/cpuidle.c | 2 ++
kernel/sched/idle.c | 14 +-
2
Am Donnerstag, den 13.08.2015, 15:18 +0900 schrieb Michel Dänzer:
On 13.08.2015 15:03, Lucas Stach wrote:
Hi Christian,
this commit is causing a boot regression with v4.2-rcX on my Richland
APU (CHIP_ARUBA) based laptop. I didn't have time yet to track down
where exactly it is going
Hi Christian,
this commit is causing a boot regression with v4.2-rcX on my Richland
APU (CHIP_ARUBA) based laptop. I didn't have time yet to track down
where exactly it is going wrong, but I bisected it down to this single
commit.
I don't have the VCE firmware installed on this system, so from a
into the same abort vector, which won't work
currently.
Regards,
Lucas
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the standardized bindings for this
stuff, instead of doing another round of NIH.
Regards,
Lucas
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Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb Thierry Reding:
On Wed, Aug 19, 2015 at 04:17:08PM +0200, Lucas Stach wrote:
Hi Thierry, Archit,
[...]
Perhaps a better way would be to invert this relationship. According to
your proposal we'd have to have DT like this:
i2c
Hi Simon,
why did you send this to the Tegra ML?
Am Dienstag, den 11.08.2015, 08:25 -0600 schrieb Simon Glass:
This updates the device tree from the kernel version to something suitable
for U-Boot:
- Add stdout-path alias for console
- Mark the /soc node to be available pre-relocation so
Am Dienstag, den 11.08.2015, 11:29 -0600 schrieb Stephen Warren:
On 08/11/2015 11:05 AM, Lucas Stach wrote:
Hi Simon,
why did you send this to the Tegra ML?
At my request, so that the DT changes could be reviewed by the kernel DT
reviewers and added to the copy of the DT files
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host driver already hooks the same fault code. Those
hooks are no chain, but a simple pointer, so one of those handlers is
going to loose out.
This likely isn't what you intended.
Regards,
Lucas
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,
but apparently it has fallen through the cracks. If you agree that this
is the right thing to do I can do a proper repost.
Regards,
Lucas
--8-
From bb9117d94cc2f1061dc364f42c446ccd9191e869 Mon Sep 17 00:00:00 2001
From: Lucas Stach l.st
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