Hi,
On 7/21/2017 2:31 PM, Baolin Wang wrote:
> On 21 July 2017 at 16:45, Manu Gautam <mgau...@codeaurora.org> wrote:
>> Hi,
>>
>>
>> On 7/21/2017 12:28 PM, Baolin Wang wrote:
>>> For some mobile devices with strict power management, we also want to
>&g
Hi,
On 7/21/2017 12:28 PM, Baolin Wang wrote:
> For some mobile devices with strict power management, we also want to
> suspend the host when the slave was detached for power saving. Thus
> adding the host suspend/resume functions to support this requirement.
USB/PM core already takes care of
From: Vivek Gautam
Pipe clock comes out of the phy and is available as long as
the phy is turned on. Clock controller fails to gate this
clock after the phy is turned off and generates a warning.
/ # [ 33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on'
[
poweron callback from phy_ops and explicitly perform
this from init, similar changes needed for poweroff.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index a230c7b..aefb853 100644
--- a/drivers/phy/qu
poweron callback from phy_ops and explicitly perform
this from init, similar changes needed for poweroff.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 6c57524..fa60a99 100644
--- a/drive
Driver currently notifies only USB3 PHY for mode change.
Extend this to USB3 PHY so that driver based on the mode
can release system resources - clocks, regulators etc.
and can even turn off PHY during runtime suspend.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
diff --git a/drive
Driver can turn off clocks during runtime suspend.
Also, runtime suspend is not as a result of host mode
selective suspend then PHY can be powered off as well.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/ph
Driver can turn off clocks during runtime suspend.
Also, runtime suspend is not as a result of host mode
selective suspend then PHY can be powered off as well.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/ph
Hi,
On 7/25/2017 1:30 PM, Baolin Wang wrote:
> This patch introduces the usb charger support based on usb phy that
> makes an enhancement to a power driver. The basic conception of the
> usb charger is that, when one usb charger is added or removed by
> reporting from the extcon device state
On 7/21/2017 10:29 PM, Stephen Boyd wrote:
> On 07/21/2017 04:01 AM, Manu Gautam wrote:
>> From: Vivek Gautam <vivek.gau...@codeaurora.org>
>>
>> Pipe clock comes out of the phy and is available as long as
>> the phy is turned on. Clock controller fails to
On 7/21/2017 10:39 PM, Stephen Boyd wrote:
> On 07/21/2017 04:02 AM, Manu Gautam wrote:
>> Driver currently notifies only USB3 PHY for mode change.
>> Extend this to USB3 PHY so that driver based on the mode
>> can release system resources - clocks, regulators etc.
>>
Hi Baolin,
On 7/24/2017 11:26 AM, Baolin Wang wrote:
Other than what I pushed in my patch -
("usb: dwc3: Don't reinitialize core during host bus-suspend/resume")
Just performing pm_request_resume or handling same in dwc3 glue
driver should be sufficient.
>>> Yes.
>>>
Hi,
On 7/24/2017 2:45 PM, Baolin Wang wrote:
> Hi Manu,
>
> On 24 July 2017 at 16:42, Manu Gautam <mgau...@codeaurora.org> wrote:
>> Hi Baolin,
>>
>>
>> On 7/24/2017 11:26 AM, Baolin Wang wrote:
>>
>>>>>> Other than what I pushed i
Hi,
On 7/21/2017 10:54 PM, Stephen Boyd wrote:
> On 07/21/2017 04:01 AM, Manu Gautam wrote:
>> Driver can turn off clocks during runtime suspend.
>> Also, runtime suspend is not as a result of host mode
>> selective suspend then PHY can be powered off as well.
>>
&g
On 7/21/2017 4:31 PM, Manu Gautam wrote:
> }
> @@ -729,19 +771,17 @@ static int qcom_qmp_phy_init(struct phy *phy)
> void __iomem *pcs = qphy->pcs;
> void __iomem *status;
> unsigned int mask, val;
> - int ret, i;
> + int ret;
>
On 9/27/2017 11:29 PM, Jack Pham wrote:
> On Wed, Sep 27, 2017 at 02:29:09PM +0530, Manu Gautam wrote:
>> QMP V3 USB3 PHY is a DP USB combo PHY with
>> dual RX/TX lanes to support type-c. There is a
>> separate block DP_COM for configuration related
>> to type-c or
Hi Jack,
On 9/28/2017 10:23 PM, Jack Pham wrote:
> Hi Manu,
>
> On Thu, Sep 28, 2017 at 09:30:38AM +0530, Manu Gautam wrote:
>> On 9/28/2017 12:46 AM, Jack Pham wrote:
>>> On Wed, Sep 27, 2017 at 10:57:41AM -0700, Jack Pham wrote:
>>>> On Wed, Sep 27, 2017 at
/0x12c
[ 33.381776] [] ret_from_fork+0x10/0x50
Fix this by enabling pipe clock at the end of phy_init(), and disabling
it as the first thing in phy_exit().
Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org&g
poweron callback
from phy_ops and explicitly perform this from com_init,
similar changes needed for poweroff. On similar lines move
clk_enable from init to com_init which can be called once
for multi lane PHYs.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom
From: Vivek Gautam <vivek.gau...@codeaurora.org>
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/p
that as well.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 2
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 inse
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 131 --
poweron callback from phy_ops and explicitly perform
this from init, similar changes needed for poweroff.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 47 +++
1 file changed, 15 insertions(+), 32 deletions(-)
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
QMP V3 USB3 PHY is a DP USB combo PHY with
dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related
to type-c or DP. Add support for dp_com region
and secondary rx/tx lanes initialization.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drive
Update compatible string and clock names for QMP version V3
USB PHY.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/ph
lane0_power_present signal must be asserted of hardware to
operate properly in SS device mode. On some platforms where VBUS
line is not connected to SS QMP PHY there is SS_PHY_CTRL register
in QSCRATCH wrapper that can be used by software to override VBUS.
Signed-off-by: Manu Gautam <m
Disable clocks and dp/dm asynchronous interrupts from
PHY as part of runtime suspend.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 159 ++
1 file changed, 159 insertions(+)
diff --git a/drivers/phy/qualco
Disable clocks as part of PHY suspend. This also requires enabling
PHY autonomous mode to detect lfps/rx_det in suspend state.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 182 +++-
drivers/phy/qualcomm/ph
-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index bda1f4c..0e9d88b 100644
--- a/d
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/d
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff
line is not connected to PHYs. Also, remove NULL checks
for PHY when calling phy_set_mode as PHY ops already check this.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/usb/dwc3/core.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drive
this by not reinitializing core on suspend/resume in host mode
for HOST only and OTG/drd configurations.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/usb/dwc3/core.c | 43 ---
1 file changed, 20 insertions(+), 23 deletions(-)
diff
) as well which results in dwc3
pm usage_count becoming negative after couple of
runtime suspend resume iterations. Fix this by
performing runtime_get/put from dwc3-pci driver only
using workqueue.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/usb/dwc3/core.c | 1 -
drive
Hi Jack,
On 9/28/2017 12:46 AM, Jack Pham wrote:
> On Wed, Sep 27, 2017 at 10:57:41AM -0700, Jack Pham wrote:
>> Hi Manu,
>>
>> On Wed, Sep 27, 2017 at 02:29:10PM +0530, Manu Gautam wrote:
>>> VBUS signal coming from PHY must be asserted in device for
>>>
Hi Kishon
On 10/5/2017 2:38 PM, Manu Gautam wrote:
> Hi Jack,
>
> On 9/28/2017 10:23 PM, Jack Pham wrote:
>>
>>>>>> +static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
>>>>>> +{
>>>>>> +struct qusb2_
Hi Kishon,
Please review this so that I can re-submit patch-set based on this approach.
On 10/9/2017 1:33 PM, Manu Gautam wrote:
> Hi Kishon
>
> On 10/5/2017 2:38 PM, Manu Gautam wrote:
>> Kishon,
>> What would you suggest here?
>> Should we add new calls e.g. phy
Hi,
On 11/22/2017 10:56 PM, Stephen Boyd wrote:
> On 11/21/2017 01:23 AM, Manu Gautam wrote:
>> New revision (v3) of QMP PHY uses different offsets
>> for almost all of the registers. Hence, move these
>> definitions to header file so that updated offsets
>> can be add
Hi,
On 11/22/2017 11:33 PM, Stephen Boyd wrote:
> On 11/21/2017 01:23 AM, Manu Gautam wrote:
>> PHY must be powered on before turning ON clocks and
>> attempting to initialize it. Driver is exposing
>> separate init and power_on routines for this.
>> Apparently USB dwc3
Hi
On 12/20/2017 12:47 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
[snip]
>>> Why not use a notification mechanism instead of adding new APIs in phy-core.
>>> This will only bloat phy-core with APIs for a particular platform.
>> Do you mean notifier_chains ?
>> When we have multiple instances of
On 12/20/2017 8:07 AM, Vivek Gautam wrote:
> Hi Manu,
>
> [snip]
>
>> @@ -998,29 +992,17 @@ static int qcom_qmp_phy_reset_init(struct device *dev)
>> static int qcom_qmp_phy_clk_init(struct device *dev)
>> {
>> struct qcom_qmp *qmp = dev_get_drvdata(dev);
>> - int ret, i;
>> +
Hi,
On 12/20/2017 11:19 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 12 December 2017 08:54 PM, Manu Gautam wrote:
>> Hi,
>>
>>
>> On 12/12/2017 5:13 PM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Tuesday 21 Novem
QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY
with dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related to type-c
or DP. Add support for dp_com region and secondary rx/tx
lanes initialization.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 inse
Use register layout to add additional registers present
on QUSB2 PHY V2 version for PHY initialization.
Other than new registers on V2, following two register's
offset and bit definitions are different: POWERDOWN control
and PLL_STATUS.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
Disable clocks and enable DP/DM wakeup interrupts when
suspending PHY.
Core driver should notify speed to PHY driver to enable
appropriate DP/DM wakeup interrupts polarity in suspend state.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 -
1 fil
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 131 --
Update compatible string and clock names for QMP version V3
USB PHY.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
poweron callback from phy_ops and explicitly perform
this from init, similar changes needed for poweroff.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 47 +++
1 file changed, 15 insertions(+), 32 deletions(-)
New revision (v3) of QMP PHY uses different offsets
for almost all of the registers. Hence, move these
definitions to header file so that updated offsets
can be added for QMP v3.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c
poweron callback
from phy_ops and explicitly perform this from com_init,
similar changes needed for poweroff. On similar lines move
clk_enable from init to com_init which can be called once
for multi lane PHYs.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom
that as well.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 2
Disable clocks and enable PHY autonomous mode to detect
wakeup events when PHY is suspended.
Core driver should notify speed to PHY driver to enable
LFPS and/or RX_DET interrupts.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c
.
Similarly QMP USB3 PHY in SS mode should monitor RX
terminations attach/detach and LFPS events depending on
SSPHY is active or not.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/phy-core.c | 30 ++
include/linux/phy/phy.
Registers offsets for QMP V3 PHY are changed from
previous versions (1/2), update same in header file.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 149
1 file changed, 149 insertions(+)
diff --git a/d
From: Vivek Gautam <vivek.gau...@codeaurora.org>
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/p
/0x12c
[ 33.381776] [] ret_from_fork+0x10/0x50
Fix this by enabling pipe clock at the end of phy_init(), and disabling
it as the first thing in phy_exit().
Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org&g
Hi Vivek,
On 12/5/2017 3:53 PM, Vivek Gautam wrote:
>
>
> On 11/21/2017 02:53 PM, Manu Gautam wrote:
>> New version of QUSB2 PHY has some registers offset changed.
>> Add support to have register layout for a target and update
>> the same in phy_configuration.
>&
Hi,
On 12/12/2017 5:13 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 21 November 2017 02:53 PM, Manu Gautam wrote:
>> QCOM USB PHYs can monitor resume/remote-wakeup event in
>> suspended state. However PHY driver must know current
>> operational speed of
Hi,
On 10/26/2017 3:31 AM, Alex Elder wrote:
> No Qualcomm SoC requires the "ehci-msm.c" code any more. So remove it.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: Alex Elder
> Acked-by: Bjorn Andersson
> Acked-by: Andy
Hi,
On 10/26/2017 3:31 AM, Alex Elder wrote:
> No Qualcomm SoC requires the "phy-msm-usb.c" USB phy driver support
> any more, so remove the code.
>
> Suggested-by: Stephen Boyd
> Signed-off-by: Alex Elder
> Acked-by: Bjorn Andersson
Hi Felipe,
Let me know if patches in this series look fine to you.
On 9/27/2017 4:49 PM, Manu Gautam wrote:
> Driver powers-off PHYs and reinitializes DWC3 core and gadget on
> resume. While this works fine for gadget mode but in host
> mode there is not re-initialization of host st
.
- Support for wakeup interrupts lines that are asserted whenever
there is any wakeup event on USB3 or USB2 bus.
- Support to replace pip3 clock going to DWC3 with utmi clock
for hardware configuration where SSPHY is not used with DWC3.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
Existing documentation has lot of incorrect information as it
was originally added for a driver that no longer exists.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
.../devicetree/bindings/usb/qcom,dwc3.txt | 85 --
1 file changed, 63 insertions(
value in case of any initalization by boot code.
Manu Gautam (3):
dt-bindings: usb: Update documentation for Qualcomm DWC3 driver
usb: dwc3: Add Qualcomm DWC3 glue driver
usb: dwc3: core: Suspend PHYs on runtime suspend in host mode
.../devicetree/bindings/usb/qcom,dwc3.txt | 85
platform glue drivers e.g.
dwc3-qcom handle remote wakeup during bus suspend by waking up
devices on receiving wakeup event from PHY.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/usb/dwc3/core.c | 36 +---
1 file changed, 33 insertions(+), 3 del
On 5/5/2018 12:18 AM, Manu Gautam wrote:
> DWC3 controller on Qualcomm SOCs has a Qscratch wrapper.
> Some of its uses are described below resulting in need to
> have a separate glue driver instead of using dwc3-of-simple:
> - It exposes register interface to override v
Existing documentation has lot of incorrect information as it
was originally added for a driver that no longer exists.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
Reviewed-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/usb/qcom,dwc3.txt
.
- Support for wakeup interrupts lines that are asserted whenever
there is any wakeup event on USB3 or USB2 bus.
- Support to replace pip3 clock going to DWC3 with utmi clock
for hardware configuration where SSPHY is not used with DWC3.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
platform glue drivers e.g.
dwc3-qcom handle remote wakeup during bus suspend by waking up
devices on receiving wakeup event from PHY.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/usb/dwc3/core.c | 36 +---
1 file changed, 33 insertions(+), 3 del
assert in driver probe to ensure core registers
are reset to POR value in case of any initalization by boot code.
Manu Gautam (3):
dt-bindings: usb: Update documentation for Qualcomm DWC3 driver
usb: dwc3: Add Qualcomm DWC3 glue driver
usb: dwc3: core: Suspend PHYs on runtime suspend in host
Hi,
On 5/26/2018 3:37 AM, Douglas Anderson wrote:
> It appears that a "#define DEBUG" was left in on the recent patch
> landed for the Qualcomm DWC3 glue driver. Let's remove it.
>
> Fixes: a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver")
> Signed-off-by: Douglas Anderson
Hi,
On 5/29/2018 10:07 AM, Can Guo wrote:
> All PHYs should be powered on before register configuration starts. And
> only PCIe PHYs need an extra power control before deasserts reset state.
>
> Signed-off-by: Can Guo
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 5 -
> 1 file changed, 4
e wouldn't be any user of same.
Reviewed-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/device
or disabling
the clocks. It allows to simplify PHY client driver code which
is both user and source of the pipe_clk and avoid error logging
related status check on clk_disable/enable.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/clk/qcom/gcc-msm8996.c | 4
1 file chan
vek Gautam <vivek.gau...@codeaurora.org>
Reviewed-by: Evan Green <evgr...@chromium.org>
Cc: stable <sta...@vger.kernel.org> # 4.14+
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4
1 file changed, 4 insertions(+)
diff --g
review comments from Stephen.
Changes since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (7):
clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
phy: qcom-qmp: Enable pipe_clk before PHY initialization
phy: qcom-qusb2: Fix crash if nvmem cell
ring which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.
Reviewed-by: Evan Green <evgr...@chromium.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcom
There are two QUSB2 PHYs present on sdm845. In order
to improve eye diagram for both the PHYs some parameters
need to be changed. Provide device tree properties to
override these from board specific device tree files.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qu
as earlier added for
sdm845 only.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
.../devicetree/bindings/phy/qcom-qusb2-phy.txt | 23 +-
include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++
2 files changed, 59 insertions(+), 1 deletion
-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 6470c5d..fddb1c9 100644
--- a/drive
review comments from Stephen.
Changes since v1:
- Updated qusb2 compatibility name as per comment from Vivek.
Manu Gautam (7):
clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
phy: qcom-qmp: Enable pipe_clk before PHY initialization
phy: qcom-qusb2: Fix crash if nvmem cell
Hi,
On 10/19/2017 5:17 PM, Philipp Zabel wrote:
> From: Vivek Gautam
>
> Add support to get a list of resets available for the device.
> These resets must be kept de-asserted until the device is
> in use.
>
> Signed-off-by: Vivek Gautam
Hi,
On 1/5/2018 4:31 PM, Kishon Vijay Abraham I wrote:
>> +enum phy_mode phy_get_mode(struct phy *phy)
>> +{
>> +enum phy_mode ret;
>> +
>> +if (!phy || !phy->ops->get_mode)
>> +return PHY_MODE_INVALID;
>> +
>> +mutex_lock(>mutex);
>> +ret = phy->ops->get_mode(phy);
>
Hi,
On 1/10/2018 6:18 PM, Roger Quadros wrote:
> Hi Manu,
>
> On 27/09/17 14:19, Manu Gautam wrote:
>> Driver powers-off PHYs and reinitializes DWC3 core and gadget on
>> resume. While this works fine for gadget mode but in host
>> mode there is not re-initial
Hi Felipe,
On 1/11/2018 1:44 PM, Felipe Balbi wrote:
> Hi,
>
> Manu Gautam <mgau...@codeaurora.org> writes:
>>> On 27/09/17 14:19, Manu Gautam wrote:
>>>> Driver powers-off PHYs and reinitializes DWC3 core and gadget on
>>>> resume. While this
Hi Roger,
On 1/15/2018 9:10 PM, Roger Quadros wrote:
> Hi Manu,
[snip]
>> I think it will be better to separate runtime_suspend and pm_suspend
>> handling for
>> host mode in dwc3. Powering offf/on PHYs and dwc3_core_exit/init across
>> system
>> suspend-resume should be ok but doing that for
Disable clocks and enable PHY autonomous mode to detect
wakeup events when PHY is suspended.
Core driver should notify speed to PHY driver to enable
LFPS and/or RX_DET interrupts.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c
The SPDX identifier is a legally binding shorthand, which
can be used instead of the full boiler plate text.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 11 +--
drivers/phy/qualcomm/phy-qcom-qusb2.c | 10 +-
2 files chan
of wakeup
events for detection. E.g. QUSB2 PHY monitors DP/DM line state
depending on whether speed is LS or FS/HS to detect resume.
Similarly QMP USB3 PHY in SS mode should monitor RX terminations
attach/detach and LFPS events depending on SSPHY is active or not.
Signed-off-by: Manu Gautam <m
Update generic compatible string for QUSB2 V2 PHY. This will allow
all targets using QUSB2 V2 use same string.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
Documentation/d
that as well.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-q
/0x12c
[ 33.381776] [] ret_from_fork+0x10/0x50
Fix this by disabling it as the first thing in phy_exit().
Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Manu Gautam <mgau...@codeaur
From: Vivek Gautam <vivek.gau...@codeaurora.org>
Move from using array of clocks to clk_bulk_* APIs that
are available now.
Signed-off-by: Vivek Gautam <vivek.gau...@codeaurora.org>
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
---
drivers/phy/qualcomm/p
poweron callback from phy_ops and explicitly perform
this from init, similar changes needed for poweroff.
Signed-off-by: Manu Gautam <mgau...@codeaurora.org>
Reviewed-by: Vivek Gautam <vivek.gau...@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 47 +++---
PHY and some
core drivers e.g. PCIe follow specific sequence after phy_init()
that mandates pipe_clk to be enabled from power_on() only.
On similar lines move clk_enable from init() to com_init() which
executes once for multi lane PHYs.
Signed-off-by: Manu Gautam <mgau...@codeaurora.
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