[PATCH v2 2/6] MIPS: tlb-r4k: If there are wired entries, don't use TLBINVF

Wired register. Therefore if the TLB has any wired entries, fall back to iterating over the entries rather than blasting them all using TLBINVF. Signed-off-by: Matt Redfearn --- Changes in v2: None arch/mips/mm/tlb-r4k.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a

[PATCH v2 5/6] remoteproc/MIPS: Add a remoteproc driver for MIPS

protocol. Signed-off-by: Lisa Parratt Signed-off-by: Matt Redfearn --- Changes in v2: None Documentation/ABI/testing/sysfs-class-mips-rproc | 24 + drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc

[PATCH v2 4/6] MIPS: CPS: Add VP(E) stealing

cpu_present mask. It is then available to be brought online again via CPU hotplug. This mechanism is used by the MIPS remote processor driver to allow CPUs within the system to execute bare metal code, not under control of the kernel. Signed-off-by: Lisa Parratt Signed-off-by: Matt Redfearn

[PATCH v2 6/6] MIPS: Deprecate VPE Loader

The MIPS remote processor driver (CONFIG_MIPS_RPROC) provides a more standard mechanism for using one or more VPs as coprocessors running separate firmware. Here we deprecate this mechanism before it is removed. Signed-off-by: Matt Redfearn --- Changes in v2: None arch/mips/Kconfig | 5

[PATCH v2 0/6] MIPS: Remote processor driver

T_SAVING define. - Make saved local state a per-cpu variable - Make gic_save_* static functions when enabled, and do { } while(0) otherwise Lisa Parratt (1): MIPS: CPS: Add VP(E) stealing Matt Redfearn (5): irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC MIPS: tlb-r4k: If

[PATCH v2 3/6] MIPS: smp.c: Introduce mechanism for freeing and allocating IPIs

: Matt Redfearn --- Changes in v2: None arch/mips/include/asm/smp.h | 14 +++ arch/mips/kernel/smp.c | 61 +++-- 2 files changed, 67 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index

[PATCH v2 1/6] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

e context saving will restore an incorrect map to VPE value, since there is a route to not having the interrupt affinity set. Signed-off-by: Matt Redfearn --- Changes in v2: Add dependence on additional patches to mips-gic in commit log Incorporate changes from Marc Zynger's review: - Remove

Re: [PATCH v2 6/6] MIPS: Deprecate VPE Loader

Hi Ralf, On 20/09/16 14:19, Ralf Baechle wrote: On Tue, Sep 20, 2016 at 09:47:29AM +0100, Matt Redfearn wrote: The MIPS remote processor driver (CONFIG_MIPS_RPROC) provides a more standard mechanism for using one or more VPs as coprocessors running separate firmware. Here we deprecate this

Re: [PATCH v2 5/6] remoteproc/MIPS: Add a remoteproc driver for MIPS

Hi Thomas, On 20/09/16 10:47, Thomas Gleixner wrote: On Tue, 20 Sep 2016, Matt Redfearn wrote: +/* Intercept CPU hotplug events for syfs purposes */ +static int mips_rproc_callback(struct notifier_block *nfb, unsigned long action, + void *hcpu) +{ Please convert

[PATCH] MIPS: smp-cps: Avoid BUG() when offlining pre-r6 CPUs

is shared by all vps in a core. Fixes: 0d2808f338c7 ("MIPS: smp-cps: Add support for CPU hotplug...) Signed-off-by: Matt Redfearn --- Ralf, it'd be great to get this into v4.8, if possible at this late stage, to avoid the regression introduced in v4.8-rc1. --- arch/mips/kernel/s

Re: [PATCH 15/21] mips: octeon: smp: Convert to hotplug state machine

HI Sebastian, On 06/09/16 18:04, Sebastian Andrzej Siewior wrote: Install the callbacks via the state machine. Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Signed-off-by: Sebastian Andrzej Siewior --- arch/mips/cavium-octeon/smp.c | 24 +++- include/linux/cpuhotplug.

[PATCH v2 12/12] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs.

This patch enables the MIPS CPS driver for MIPSr6 CPUs. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None drivers/cpuidle/Kconfig.mips | 2 +- drivers/cpuidle/cpuidle-cps.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpuidle

[PATCH v2 09/12] MIPS: pm-cps: Add MIPSr6 CPU support

yield to other VPs on the same core, so drop the MT ASE yield instruction. 3. To halt a MIPSr6 VP, the CPC VP_STOP register is used rather than the MT ASE TCHalt CP0 register. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/include/asm/pm-cps.h | 6

[PATCH v2 11/12] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other

All calls to mips_cpc_lock_other should be wrapped in mips_cm_lock_other. This only matters if the system has CM3 and is using cpu idle, since otherwise a) the CPC lock is sufficent for CM < 3 and b) any systems with CM > 3 have not been able to use cpu idle until now. Signed-off-by

[PATCH v2 05/12] MIPS: Barrier: Add definitions of SYNC stype values

-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: Add new patch to define standard MIPS barrier types arch/mips/include/asm/barrier.h | 96 + 1 file changed, 96 insertions(+) diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include

[PATCH v2 10/12] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register

coherence. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/include/asm/mips-cm.h | 1 + arch/mips/kernel/pm-cps.c | 31 ++- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b

[PATCH v2 08/12] MIPS: pm-cps: Remove selection of sync types

Instead of selecting an implementation or vendor specific sync type for the required sync operations, always use the architecturally mandated sync types which previous patches have put in place. The selection of special sync types is now redundant an can be removed. Signed-off-by: Matt Redfearn

[PATCH v2 04/12] MIPS: pm-cps: Update comments on barrier instructions

This code makes large use of barriers, which had quite vague descriptions. Update the comments to make the choice of barrier and reason for it more clear. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: Update comments on barriers arch/mips/kernel/pm-cps.c | 16

[PATCH v2 01/12] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int'

Checkpatch complains about use of bare unsigned type. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/kernel/mips-cpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c

[PATCH v2 00/12] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs

selecting CPU specific ones. Matt Redfearn (12): MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' MIPS: CPC: Avoid lock when MIPS CM >= 3 is present MIPS: pm-cps: Change FSB workaround to CPU blacklist MIPS: pm-cps: Update comments on barrier instructions MIPS: B

[PATCH v2 06/12] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

loads / stores are gloablly completed, use the defined standard sync stype. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/kernel/pm-cps.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch

[PATCH v2 07/12] MIPS: pm-cps: Use MIPS standard completion barrier

completion sync stype. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/kernel/pm-cps.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index d7037fe00d1c..953ff0db9061

[PATCH v2 03/12] MIPS: pm-cps: Change FSB workaround to CPU blacklist

workaround can then be added to the blacklist. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/kernel/pm-cps.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index 5b31a9405ebc

[PATCH v2 02/12] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present

mips_cm_{lock,unlock}_other pair ensuring the correct CPC_OTHER region will be accessed. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- Changes in v2: None arch/mips/kernel/mips-cpc.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/mips

Re: [PATCH 15/21] mips: octeon: smp: Convert to hotplug state machine

Hi Sebastian On 07/09/16 15:27, Sebastian Andrzej Siewior wrote: On 2016-09-07 09:24:57 [+0100], Matt Redfearn wrote: HI Sebastian, Hi Matt, --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -44,6 +44,7 @@ enum cpuhp_state { CPUHP_SH_SH3X_PREPARE

[PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs

MIPSr6 CPUs. Applies atop v4.8-rc4 Matt Redfearn (10): MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' MIPS: CPC: Avoid lock when MIPS CM >= 3 is present MIPS: pm-cps: Change FSB workaround to CPU blacklist MIPS: pm-cps: Remove I6400 sync types MIPS: pm-cps: A

[PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other

All calls to mips_cpc_lock_other should be wrapped in mips_cm_lock_other. This only matters if the system has CM3 and is using cpu idle, since otherwise a) the CPC lock is sufficent for CM < 3 and b) any systems with CM > 3 have not been able to use cpu idle until now. Signed-off-by

[PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs.

This patch enables the MIPS CPS driver for MIPSr6 CPUs. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- drivers/cpuidle/Kconfig.mips | 2 +- drivers/cpuidle/cpuidle-cps.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpuidle/Kconfig.mips b/drivers

[PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register

coherence. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/kernel/pm-cps.c | 31 ++- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include

[PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support

yield to other VPs on the same core, so drop the MT ASE yield instruction. 3. To halt a MIPSr6 VP, the CPC VP_STOP register is used rather than the MT ASE TCHalt CP0 register. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/include/asm/pm-cps.h | 6 -- arch/mips

[PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist

workaround can then be added to the blacklist. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/kernel/pm-cps.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index 5b31a9405ebc..2faa227a032e 100644

[PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

heavyweight sync(0) such that we can benefit from the lighter weight sync. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/include/asm/barrier.h | 10 ++ arch/mips/kernel/pm-cps.c | 3 +-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/mips

[PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types

Commit 4e88a8621301 ("MIPS: Add cases for CPU_I6400") added a case for I6400 to the selection of lightweight sync types, but these are not implemented. Remove the case. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/kernel/pm-cps.c | 1 - 1 file changed,

[PATCH 01/10] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int'

Checkpatch complains about use of bare unsigned type. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/kernel/mips-cpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c index 566b8d2c092c

[PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present

mips_cm_{lock,unlock}_other pair ensuring the correct CPC_OTHER region will be accessed. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/kernel/mips-cpc.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips

[PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types

P6600 implements the same lightweight sync types as previous CPUs. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/kernel/pm-cps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c index c6b9ad2256f0..f8c8edd0a451

Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

On 31/08/16 12:48, Peter Zijlstra wrote: On Wed, Aug 31, 2016 at 11:44:35AM +0100, Matt Redfearn wrote: Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but architecturally defined ordering barrier. If a CPU does not implement it, the arch specifies that it must fall back to

Re: [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

On 31/08/16 15:28, Peter Zijlstra wrote: On Wed, Aug 31, 2016 at 02:36:26PM +0100, Matt Redfearn wrote: The code previously had 0x10 as a magic number, this patch just replaces that with a #defined name. The value is documented in the MIPS64 instruction set manual, https://imgtec.com/?do

[PATCH 3/6] MIPS: smp.c: Introduce mechanism for freeing and allocating IPIs

: Matt Redfearn --- arch/mips/include/asm/smp.h | 14 +++ arch/mips/kernel/smp.c | 61 +++-- 2 files changed, 67 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 8bc6c70a4030..060f23ff1817

[PATCH 6/6] MIPS: Deprecate VPE Loader

The MIPS remote processor driver (CONFIG_MIPS_RPROC) provides a more standard mechanism for using one or more VPs as coprocessors running separate firmware. Here we deprecate this mechanism before it is removed. Signed-off-by: Matt Redfearn --- arch/mips/Kconfig | 5 - 1 file changed, 4

[PATCH 5/6] remoteproc/MIPS: Add a remoteproc driver for MIPS

protocol. Signed-off-by: Lisa Parratt Signed-off-by: Matt Redfearn --- Documentation/ABI/testing/sysfs-class-mips-rproc | 24 + drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/mips_remoteproc.c | 651

[PATCH 4/6] MIPS: CPS: Add VP(E) stealing

cpu_present mask. It is then available to be brought online again via CPU hotplug. This mechanism is used by the MIPS remote processor driver to allow CPUs within the system to execute bare metal code, not under control of the kernel. Signed-off-by: Lisa Parratt Signed-off-by: Matt Redfearn --- arch

[PATCH 0/6] MIPS: Remote processor driver

to Linux the kernel exception handlers won't be reinstated properly. [1] http://wiki.prplfoundation.org/w/images/d/df/MIPS_OS_Remote_Processor_Driver_Whitepaper_1.0.9.pdf [2] https://github.com/MIPS/mips-rproc-example Lisa Parratt (1): MIPS: CPS: Add VP(E) stealing Matt Redfearn (5):

[PATCH 2/6] MIPS: tlb-r4k: If there are wired entries, don't use TLBINVF

Wired register. Therefore if the TLB has any wired entries, fall back to iterating over the entries rather than blasting them all using TLBINVF. Signed-off-by: Matt Redfearn --- arch/mips/mm/tlb-r4k.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/tlb-r4k.c

[PATCH 1/6] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

is restored. These functions will also be useful for restoring GIC context after a suspend to RAM. Signed-off-by: Matt Redfearn --- drivers/irqchip/irq-mips-gic.c | 185 +++-- 1 file changed, 178 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq

Re: [PATCH 1/6] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

On 02/09/16 10:59, Matt Redfearn wrote: The MIPS remote processor driver allows non-Linux firmware to take control of and execute on one of the systems VPEs. If that VPE is brought back under Linux, it is necessary to ensure that all GIC interrupts are routed and masked as Linux expects them

Re: [PATCH 1/6] irqchip: mips-gic: Add context saving for MIPS_REMOTEPROC

Hi Marc, Thanks for the review! On 02/09/16 11:54, Marc Zyngier wrote: Hi Matt, On 02/09/16 10:59, Matt Redfearn wrote: The MIPS remote processor driver allows non-Linux firmware to take control of and execute on one of the systems VPEs. If that VPE is brought back under Linux, it is

[PATCH] MIPS: Move identification of VP(E) into proc.c from smp-mt.c

smp-mt.c. Signed-off-by: Matt Redfearn Reviewed-by: Paul Burton --- arch/mips/kernel/proc.c | 7 +++ arch/mips/kernel/smp-mt.c | 23 --- 2 files changed, 7 insertions(+), 23 deletions(-) diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index

[PATCH] MIPS: generic: Fix compilation error from include asm/mips-cpc.h

-cps.h instead. Fixes: e83f7e02af50c ("MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers") Signed-off-by: Matt Redfearn --- arch/mips/generic/init.c | 2 +- arch/mips/kernel/smp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/generic/init.

Re: [PATCH 4.4 36/50] MIPS: IRQ Stack: Unwind IRQ stack onto task stack

On 16/10/17 22:28, Ben Hutchings wrote: On Fri, 2017-10-06 at 10:53 +0200, Greg Kroah-Hartman wrote: 4.4-stable review patch.  If anyone has any objections, please let me know. -- From: Matt Redfearn [ Upstream commit db8466c581cca1a08b505f1319c3ecd246f16fa8

[PATCH] MIPS: Boston: Fix earlycon baud rate selection

t the baud rate settings from the bootloader. By the time the real console is probed, the clock drivers necessary to calculate the divisor are enabled and the kernel can correctly configure the baud rate. Fixes: 31cb9a8575ca ("earlycon: initialise baud field of earlycon device structure")

Re: [PATCH 1/5] MIPS: Optimize uasm insn lookup.

Hi David, On 26/05/17 01:38, David Daney wrote: Instead of doing a linear search through the insn_table for each instruction, use the opcode as direct index into the table. This will give constant time lookup performance as the number of supported opcodes increases. Make the tables const as t

Re: [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic

Hi, On 29/10/17 23:11, Stafford Horne wrote: In case timers are not in sync when cpus start (i.e. hot plug / offset resets) we need to synchronize the secondary cpus internal timer with the main cpu. This is needed as in OpenRISC SMP there is only one clocksource registered which reads from th

Re: [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic

On 01/11/17 00:34, Stafford Horne wrote: On Wed, Nov 01, 2017 at 08:17:59AM +0900, Stafford Horne wrote: On Tue, Oct 31, 2017 at 02:06:21PM +, Matt Redfearn wrote: Hi, On 29/10/17 23:11, Stafford Horne wrote: In case timers are not in sync when cpus start (i.e. hot plug / offset

[PATCH] MIPS: CPS: Fix use of current_cpu_data in preemptible code

u_cluster(¤t_cpu_data) will always be 0, even if this task being preempted and continues running on a different CPU. Regardless, the BUG should not be triggered, so fix this by switching to raw_current_cpu_data. When multicluster support lands upstream this check will need removing or changing

Re: [PATCH] MIPS: Boston: Fix earlycon baud rate selection

Hi Paul, On 25/10/17 23:09, Paul Burton wrote: Hi Matt, On Tuesday, October 17, 2017 at 6:28 AM Matt Redfearn wrote: During set up of the early console, the earlycon driver will attempt to configure a baud rate, if one is set in the earlycon structure. Previously, of_setup_earlycon left this

[PATCH] watchdog: indydog: Add dependency on SGI_HAS_INDYDOG

g/indydog.o:indydog.c:(.text+0xa8): more undefined references to `sgimc' follow make: *** [Makefile:1005: vmlinux] Error 1 Fix this by ensuring that CONFIG_INDIDOG can only be selected when the necessary dependent platform symbols are built in. Fixes: da2a68b3eb47 ("watchdog: Enable CO

[PATCH] MIPS: ath25: Avoid undefined early_serial_setup() without SERIAL_8250_CONSOLE

dependencies to the platform to force inclusion of SERIAL_8250_CONSOLE together with it's dependencies like TTY, HAS_IOMEM, etc, just make ath25_serial_setup() a no-op when the dependency is not selected in the kernel config. Signed-off-by: Matt Redfearn --- arch/mips/ath25/devices.c | 2 +

Re: [PATCH] MIPS: ath25: Avoid undefined early_serial_setup() without SERIAL_8250_CONSOLE

On 14/11/17 14:05, Ralf Baechle wrote: On Tue, Nov 14, 2017 at 01:29:17PM +, Matt Redfearn wrote: Currently MIPS allnoconfig with CONFIG_ATH25=y fails to link due to missing support for early_serial_setup(): LD vmlinux arch/mips/ath25/devices.o: In function ath25_serial_setup

[PATCH 2/2] MIPS: RB532: Avoid undefined mac_pton without GENERIC_NET_UTILS

latform to force inclusion of GENERIC_NET_UTILS which is selected by CONFIG_NET, just exclude the setup of the MAC address if CONFIG_NET is not selected in the kernel config. Signed-off-by: Matt Redfearn --- arch/mips/rb532/devices.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/

[PATCH 1/2] MIPS: RB532: Avoid undefined early_serial_setup() without SERIAL_8250_CONSOLE

han adding dependencies to the platform to force inclusion of SERIAL_8250_CONSOLE together with it's dependencies like TTY, HAS_IOMEM, etc, just exclude arch/mips/rb532/serial.c from the build when it's dependency is not selected in the kernel config. Reported-by: Ralf Baechle Signed-off-by: Matt

[PATCH] MIPS: BCM47XX Avoid compile error with MIPS allnoconfig

both, but not neither. Signed-off-by: Matt Redfearn --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 350a990fc719..659e0079487f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -259,6 +259,7 @@ config BCM47XX

Re: [PATCH V8 5/5] libata: Align DMA buffer to dma_get_cache_alignment()

On 18/10/17 14:03, Tejun Heo wrote: On Tue, Oct 17, 2017 at 04:05:42PM +0800, Huacai Chen wrote: In non-coherent DMA mode, kernel uses cache flushing operations to maintain I/O coherency, so in ata_do_dev_read_id() the DMA buffer should be aligned to ARCH_DMA_MINALIGN. Otherwise, If a DMA buff

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

On 18/10/17 21:34, Thomas Gleixner wrote: On Wed, 11 Oct 2017, Matt Redfearn wrote: When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This is suboptimal for two reasons. Firstly, the CPU timer counts once

Re: [PATCH 1/3] clocksource/mips-gic-timer: Fix rcu_sched timeouts from multithreading

On 19/10/17 10:09, Daniel Lezcano wrote: On 11/10/2017 16:01, Matt Redfearn wrote: When the MIPS GIC clockevent code was written, it appears to have inherited the 0x300 cycle min delta from the MIPS CPU timer driver. This is suboptimal for two reasons. Firstly, the CPU timer counts once

[PATCH 1/3] clockevents: Retry programming min delta up to 10 times

ving up. Signed-off-by: James Hogan Signed-off-by: Matt Redfearn Cc: Thomas Gleixner Cc: Martin Schwidefsky --- kernel/time/clockevents.c | 26 +++--- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/kernel/time/clockevents.c b/kernel/time/clockevents.c in

[PATCH 2/3] clocksource/mips-gic-timer: Remove pointless irq_save,restore

gic_next_event is always called with interrupts disabled, so the save / restore is pointless - remove it. Signed-off-by: Matt Redfearn Suggested-by: Thomas Gleixner --- drivers/clocksource/mips-gic-timer.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clocksource/mips-gic

[PATCH V2 3/3] clocksource: mips-gic-timer: Add fastpath for local timer updates

Always accessing the compare register via the CM redirect region is (relatively) slow. If the timer being updated is the current CPUs then this can be shortcutted by writing to the CM VP local region. Signed-off-by: Matt Redfearn --- drivers/clocksource/mips-gic-timer.c | 9 +++-- 1 file

Re: [PATCH 1/3] clockevents: Retry programming min delta up to 10 times

On 19/10/17 13:43, Thomas Gleixner wrote: On Thu, 19 Oct 2017, Matt Redfearn wrote: unsigned long long clc; int64_t delta; + int i; - delta = dev->min_delta_ns; - dev->next_event = ktime_add_ns(ktime_get(), delta); + for (i = 0;;) { Bah. What&#

[PATCH v2] clockevents: Retry programming min delta up to 10 times

e increasing the attempted delta by min_delta, before giving up. Signed-off-by: James Hogan Signed-off-by: Matt Redfearn Cc: Thomas Gleixner Cc: Martin Schwidefsky --- Changes in v2: Restructure for loop and retry with increasing multiples of min_delta. kernel/time/clockevents.c | 20 +++

Re: [PATCH 02/14] MIPS: memblock: Surely map BSS kernel memory section

Hi Serge, On 22/01/18 21:47, Serge Semin wrote: Hello Matt, On Mon, Jan 22, 2018 at 04:35:26PM +, Matt Redfearn wrote: Hi Serge, On 17/01/18 22:23, Serge Semin wrote: The current MIPS code makes sure the kernel code/data/init sections are in the maps, but BSS should also be there

Re: [PATCH v2] MIPS: fix incorrect mem=X@Y handling

s factory default command line args of "mem=256M@0x0 mem=768M@0x3000" are passed. Though those arguments appear redundant since without them both memory regions are detected through device tree instead, and there is no problem. Tested-by: Matt Redfearn --- v2: Use updated email a

Re: [PATCH 00/14] MIPS: memblock: Switch arch code to NO_BOOTMEM

Hi Mathieu, On 23/01/18 11:29, Mathieu Malaterre wrote: Hi Matt, On Mon, Jan 22, 2018 at 5:36 PM, Matt Redfearn wrote: Hi Serge, On 17/01/18 22:22, Serge Semin wrote: Even though it's common to see the architecture code using both bootmem and memblock early memory allocators, it&

Re: [PATCH 11/14] MIPS: memblock: Print out kernel virtual mem layout

Hi Serge, On 19/01/18 14:27, Serge Semin wrote: On Fri, Jan 19, 2018 at 07:59:43AM +, Matt Redfearn wrote: Hello Matt, Hi Serge, On 18/01/18 20:18, Serge Semin wrote: On Thu, Jan 18, 2018 at 12:03:03PM -0800, Florian Fainelli wrote: On 01/17/2018 02:23 PM, Serge Semin wrote: It

Re: [PATCH 11/14] MIPS: memblock: Print out kernel virtual mem layout

Hi Serge, On 23/01/18 19:10, Serge Semin wrote: Hello Matt, On Tue, Jan 23, 2018 at 03:35:14PM +, Matt Redfearn wrote: Hi Serge, On 19/01/18 14:27, Serge Semin wrote: On Fri, Jan 19, 2018 at 07:59:43AM +, Matt Redfearn wrote: Hello Matt, Hi Serge, On 18/01/18 20:18, Serge

Re: [PATCH 02/14] MIPS: memblock: Surely map BSS kernel memory section

Hi Serge, On 23/01/18 19:27, Serge Semin wrote: Hello Matt, On Tue, Jan 23, 2018 at 11:03:27AM +, Matt Redfearn wrote: Hi Serge, On 22/01/18 21:47, Serge Semin wrote: Hello Matt, On Mon, Jan 22, 2018 at 04:35:26PM +, Matt Redfearn wrote: Hi Serge, On 17/01/18 22:23, Serge

[PATCH] MIPS: Sort MIPS Kconfig Alphabetically.

Sort the entries in config MIPS alphabetically so as to make entries easier to find. Signed-off-by: Matt Redfearn --- This patch is based on 4.12-rc1. My intention would be for it to be applied during the -rc's when it is less likely to cause merge conflicts with other patches changing c

[PATCH] bcma: Prevent build of PCI host features in module

ake[1]: *** [scripts/Makefile.modpost:92: __modpost] Error 1 To prevent this, don't allow the host mode feature to be built if CONFIG_BCMA=m Signed-off-by: Matt Redfearn --- drivers/bcma/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bcma/Kconfig b/d

[PATCH] ssb: Prevent build of PCI host features in module

ake[1]: *** [scripts/Makefile.modpost:92: __modpost] Error 1 To prevent this, don't allow the host mode feature to be built if CONFIG_SSB=m Signed-off-by: Matt Redfearn --- drivers/ssb/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ssb/Kconfig b/drivers/ssb/K

Re: [PATCH v2 1/2] Add notrace to lib/ucmpdi2.c

Hi On 30/01/18 22:42, Antony Pavlov wrote: From: Palmer Dabbelt As part of the MIPS conversion to use the generic GCC library routines, Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This patch rectifies the problem. CC: Matt Redfearn CC: Antony Pavlov Signed-o

Re: [PATCH v2 2/2] MIPS: use generic GCC library routines from lib/

in favour of similar routines from lib/. Signed-off-by: Antony Pavlov Cc: Palmer Dabbelt Cc: Matt Redfearn Cc: James Hogan Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Cc: linux-kernel@vger.kernel.org --- arch/mips/Kconfig | 5 + arch/mips/lib/Makefile | 2 +- arch/mips/lib

Re: [PATCH v3 2/2] MIPS: use generic GCC library routines from lib/

in favour of similar routines from lib/. Signed-off-by: Antony Pavlov Cc: Palmer Dabbelt Cc: Matt Redfearn Cc: James Hogan Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Cc: linux-kernel@vger.kernel.org --- arch/mips/Kconfig | 5 + arch/mips/lib/Makefile | 2 +- arch/mips/lib

Re: [PATCH 11/14] MIPS: memblock: Print out kernel virtual mem layout

Hi Serge, On 18/01/18 20:18, Serge Semin wrote: On Thu, Jan 18, 2018 at 12:03:03PM -0800, Florian Fainelli wrote: On 01/17/2018 02:23 PM, Serge Semin wrote: It is useful to have the kernel virtual memory layout printed at boot time so to have the full information about the booted kernel. I

Re: [PATCH 02/14] MIPS: memblock: Surely map BSS kernel memory section

below _end. Reviewed-by: Matt Redfearn Thanks, Matt Signed-off-by: Serge Semin --- arch/mips/kernel/setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 76e9e2075..0d21c9e04 100644 --- a/arch/mips/kernel/setup.c +++ b/arch

Re: [PATCH 00/14] MIPS: memblock: Switch arch code to NO_BOOTMEM

ards/generic code had been discarded. Here are the list of folks, who agreed to perform some tests of the patchset: Alexander Sverdlin - Octeon2 Matt Redfearn - Loongson3, etc I have applied and tested these patches on various platforms that we have available here, and the kernel appears to boot a

[PATCH 2/6] MIPS: CPS: Introduce mips_gic_enable_eic

CPU flags to reflect that VEIC mode is now active. Signed-off-by: Matt Redfearn --- arch/mips/include/asm/mips-gic.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h index 558059a8f218..b8345b117224

[PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available

tested on Boston, Malta & SEAD3 MIPS platforms implementing a GIC with and without EIC mode supported in hardware. Matt Redfearn (6): MIPS: Move ehb() to barrier.h MIPS: CPS: Introduce mips_gic_enable_eic MIPS: Generic: Support GIC in EIC mode irqchip/mips-gic: Always attempt to en

[PATCH 1/6] MIPS: Move ehb() to barrier.h

The current location of ehb() in mipsmtregs.h does not make sense, since it is not strictly related to multi-threading, and may be used in code which does not include mipsmtregs.h Signed-off-by: Matt Redfearn --- arch/mips/include/asm/barrier.h| 13 + arch/mips/include/asm

[PATCH 3/6] MIPS: Generic: Support GIC in EIC mode

hould panic. Support for alternative EICs being present is needed here for the generic kernel to support them. Suggested-by: Paul Burton Signed-off-by: Matt Redfearn --- arch/mips/generic/irq.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/mips/ge

[PATCH 4/6] irqchip/mips-gic: Always attempt to enable EIC mode

CPU flags to reflect that VEIC mode is now active. Signed-off-by: Matt Redfearn --- drivers/irqchip/irq-mips-gic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index ef92a4d2038e..ee391f42e97d 100644 --- a/drivers/irqchip

[PATCH 6/6] irqchip/mips-gic: Separate local interrupt handling.

__gic_irq_dispatch to __gic_irq_dispatch_local, which is only called for local interrupt sources now so no longer needs to handle shared interrupts. Signed-off-by: Matt Redfearn --- drivers/irqchip/irq-mips-gic.c | 20 +--- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers

[PATCH 5/6] irqchip/mips-gic: Use separate vector for shared interrupts in EIC mode

introduces additional latency into the interrupt paths which is easy to remove in EIC mode by making use of an additional vector for shared interrupt sources. Signed-off-by: Matt Redfearn --- drivers/irqchip/irq-mips-gic.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff

[PATCH] MIPS: TXx9: use IS_BUILTIN() for CONFIG_LEDS_CLASS

33b44073734 ("MIPS: TXX9: use IS_ENABLED() macro") Signed-off-by: Matt Redfearn --- arch/mips/txx9/rbtx4939/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 8b937300fb7f..fd26fadc8617

Re: [PATCH] MIPS: use generic GCC library routines from lib/

Hi, On Wed, Jan 17, 2018 at 09:51:21AM +0300, Antony Pavlov wrote: > The commit b35cd9884fa5 ("lib: Add shared copies of > some GCC library routines") makes it possible > to share generic GCC library routines by several > architectures. > > This commit removes several generic GCC library > routin

Re: [PATCH] bcma: Prevent build of PCI host features in module

Hi Kalle, On 15/01/18 10:07, Kalle Valo wrote: Matt Redfearn writes: Attempting to build bcma.ko with BCMA_DRIVER_PCI_HOSTMODE=y results in a build error due to use of symbols not exported from vmlinux: ERROR: "pcibios_enable_device" [drivers/bcma/bcma.ko] undefi

Re: [PATCH] mips: ftrace: fix static function graph tracing

etup could give it a spin. My test I've tested this patch fixes static function graph tracing on the following platforms: QEMU (MIPS32r2 P5600) Creator Ci40 (MIPS32r2 InterAptiv) Cavium Octeon II (MIPS64r2) MIPS Boston FPGA with I6400 (MIPS64r6) So Tested-by: Matt Redfearn device runs

[PATCH v6 1/4] Add notrace to lib/ucmpdi2.c

From: Palmer Dabbelt As part of the MIPS conversion to use the generic GCC library routines, Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This patch rectifies the problem. CC: Matt Redfearn CC: Antony Pavlov Signed-off-by: Palmer Dabbelt Reviewed-by: Matt Red

[PATCH v6 2/4] lib: Rename compiler intrinsic selects to GENERIC_LIB_*

When these are included into arch Kconfig files, maintaining alphabetical ordering of the selects means these get split up. To allow for keeping things tidier and alphabetical, rename the selects to GENERIC_LIB_* Signed-off-by: Matt Redfearn Reviewed-by: Palmer Dabbelt --- Changes in v6: None

[PATCH v6 3/4] MIPS: vmlinuz: Use generic ashldi3

additional CFLAGS are apparently unnecessary - remove them as well. Signed-off-by: Matt Redfearn --- Changes in v6: New patch to fix vmlinuz which requires ashldi3 so must be switched to come from $(srctree)/lib before the arch/mips/ version is deleted. This version has been build tested with every

[PATCH v6 4/4] MIPS: use generic GCC library routines from lib/

tines from lib/. Signed-off-by: Antony Pavlov [Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries Signed-off-by: Matt Redfearn Cc: Palmer Dabbelt Cc: Matt Redfearn Cc: James Hogan Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Cc: linux-kernel@vger.kernel.org --- Changes in v6: None Cha

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