ms that we support is empty, and will be
> filled in as and when we move platforms to use it.
>
> It always compiles as part of the kernel and so doesn't need a
> module-exit operation.
>
> Signed-off-by: Viresh Kumar
> Reviewed-by: Krzysztof Kozlowski
Test on ipq4019.
Tested-by: Matthew McClintock
-M
I’m seeing this too, same commit if you want another person to test/reproduce.
-M
> On May 24, 2016, at 11:10 AM, Larry Finger wrote:
>
> On 05/23/2016 07:18 PM, Al Viro wrote:
>> On Mon, May 23, 2016 at 04:30:43PM -0500, Larry Finger wrote:
>>> The mainline kernels past 4.6.0 fail hang when lo
On May 24, 2016, at 2:16 PM, Larry Finger wrote:
>
> On 05/24/2016 02:13 PM, Matthew McClintock wrote:
>> I’m seeing this too, same commit if you want another person to
>> test/reproduce.
>
> If you do a pull today, does that fix your problem?
Hmm, no. Which commit
> On May 24, 2016, at 2:36 PM, Larry Finger wrote:
>
> On 05/24/2016 02:25 PM, Matthew McClintock wrote:
>> On May 24, 2016, at 2:16 PM, Larry Finger wrote:
>>>
>>> On 05/24/2016 02:13 PM, Matthew McClintock wrote:
>>>> I’m seeing this too, same co
> On May 24, 2016, at 6:41 PM, Al Viro wrote:
>
> Again, I understand what's going on kernel-side; the only tricky part is how
> to fix it without bringing the nasal daemons back. I think I have a solution
> and I'm going to post it tonight if it survives the local beating. In any
> case, the
> On May 24, 2016, at 8:10 PM, Al Viro wrote:
>
> Slap the WARN_ON(!size); in the very beginning of iov_iter_advance(), see
> where it's triggered...
diff --git a/lib/iov_iter.c b/lib/iov_iter.c
index 28cb431..d89e154 100644
--- a/lib/iov_iter.c
+++ b/lib/iov_iter.c
@@ -488,6 +488,7 @@ EXPORT_S
> On May 24, 2016, at 8:28 PM, Al Viro wrote:
>
> The next obvious question is which binary it is and what's the return
> address to userland; make that
> if (!size)
> printk(KERN_ERR "crap in %s[%x]",
> current->comm,
> current_pt_
On May 25, 2016, at 1:24 AM, Al Viro wrote:
>
> diff --git a/lib/iov_iter.c b/lib/iov_iter.c
> index 28cb431..0cd5227 100644
> --- a/lib/iov_iter.c
> +++ b/lib/iov_iter.c
> @@ -101,7 +101,7 @@
> #define iterate_and_advance(i, n, v, I, B, K) { \
> if (unlikely(i->count
- combine reset dts include files into one overall dts include
SoC dts file:
v2
- add sleep_clk
Board dts file:
- add xo clock
Matthew McClintock (4):
ARM: qcom: add IPQ4019 compatible match
qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC
dts: ipq4019: Add support for IPQ4019 DK01 board
From: Matthew McClintock
This will select qcom board type when the machine compatible is
qcom,ipq4019.
Signed-off-by: Matthew McClintock
---
arch/arm/mach-qcom/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7
From: Matthew McClintock
Initial board support dts files for DK01 board.
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
---
v2
- add xo clock
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
arch
From: Matthew McClintock
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan
---
v2
- add sleep_clk
arch/arm/boot/dts/qcom-ipq4019.dtsi | 115
1 file changed, 115 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom
From: Varadarajan Narayanan
Add pinctrl driver support for IPQ4019 platform
Signed-off-by: Sricharan R
Signed-off-by: Mathieu Olivari
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
---
v3
- update example with actual values from dts
- add missing pins 71-99
- drop
From: Varadarajan Narayanan
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
On Feb 8, 2016, at 4:43 PM, Stephen Boyd wrote:
>
> On 11/19, Matthew McClintock wrote:
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
>> +compatible = "qcom,ipq4019";
>> +
>> +clocks {
>&
> On Feb 16, 2016, at 8:54 AM, Linus Walleij wrote:
>
> On Fri, Nov 20, 2015 at 12:19 AM, Matthew McClintock
> wrote:
>
>> From: Varadarajan Narayanan
>>
>> Add pinctrl driver support for IPQ4019 platform
>>
>> Signed-off-by: Sricharan R
>&g
On Apr 6, 2016, at 12:02 AM, Sreedhar Sambangi wrote:
>
>>> +config REGULATOR_IPQ4019
>> How bout REGULATOR_QCOM_IPQ4019.
>
> Sounds good, Will update in V2
Also prefix the name with “Qualcomm” and insert it in the list in order.
-M
IPQ8019 has a Quad-Core ARM Cortex A7 with integrated Wifi, GMAC,
Swtich, USB, PCIe, and more..
Matthew McClintock (3):
ARM: qcom: add IPQ4019 compatible match
qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC
dts: ipq4019: Add support for IPQ4019 DK01 board
Varadarajan Narayanan (2
This will select qcom board type when the machine compatible is
qcom,ipq4019.
Signed-off-by: Matthew McClintock
---
arch/arm/mach-qcom/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7..b52a6bc 100644
--- a/arch/arm
From: Varadarajan Narayanan
Add pinctrl driver support for IPQ4019 platform
Signed-off-by: Sricharan R
Signed-off-by: Mathieu Olivari
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
---
.../bindings/pinctrl/qcom,ipq4019-pinctrl.txt | 116 ++
drivers/pinctrl
Initial board support dts files for DK01 board.
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +++
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 49
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 108
1 file changed, 108 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi
diff --git a/arch/arm/boot/dts/qco
From: Varadarajan Narayanan
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
> On Nov 5, 2015, at 8:34 PM, Rob Herring wrote:
>
> On Thu, Nov 05, 2015 at 04:07:52PM -0600, Matthew McClintock wrote:
>> From: Varadarajan Narayanan
>>
>> Add pinctrl driver support for IPQ4019 platform
>>
>> Signed-off-by: Sricharan R
>> Sig
From: Matthew McClintock
This will select qcom board type when the machine compatible is
qcom,ipq4019.
Signed-off-by: Matthew McClintock
---
arch/arm/mach-qcom/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index 6d8bbf7
From: Matthew McClintock
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan
---
v2 - add sleep_clk
arch/arm/boot/dts/qcom-ipq4019.dtsi | 115
1 file changed, 115 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom
From: Matthew McClintock
Initial board support dts files for DK01 board.
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
---
v2 - add xo clock
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts | 22 +
arch
From: Varadarajan Narayanan
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
From: Varadarajan Narayanan
Add pinctrl driver support for IPQ4019 platform
Signed-off-by: Sricharan R
Signed-off-by: Mathieu Olivari
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
---
v2 - add a note in the device tree binding about the TLMM block
.../bindings
From: Varadarajan Narayanan
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi
Signed-off-by: Senthilkumar N L
Signed-off-by: Varadarajan Narayanan
Signed-off-by: Matthew McClintock
> On Mar 25, 2016, at 11:23 AM, Guenter Roeck wrote:
>
>> -#define WDT_RST 0x38
>> -#define WDT_EN 0x40
>> -#define WDT_BITE_TIME 0x5C
>> +enum wdt_reg {
>> +WDT_RST,
>> +WDT_EN,
>> +WDT_BITE_TIME,
>> +};
>> +
>> +static const u32 reg_offset_data_apcs_t
On Mar 25, 2016, at 9:15 AM, Rob Herring wrote:
>
> On Wed, Mar 23, 2016 at 05:05:04PM -0500, Matthew McClintock wrote:
>> Update the compatible string to add new device tree binding
>>
>> CC: linux-watch...@vger.kernel.org
>> Signed-off-by: Matthew McCli
On Mar 28, 2016, at 1:13 PM, Guenter Roeck wrote:
>
>>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg
>>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is
>>> undefined.
>>
>> I honestly don’t see anything at 0x8 for either blocks that looks
On Mar 28, 2016, at 4:56 PM, Guenter Roeck wrote:
>
>> So taken from the timer offset 0x0208A000 I just have a generic counter
>> register CPU0_APCS_GPT0_CNT at 0x8
>>
>> What doc are you looking at?
>>
> "Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Description"
>
> It is avai
On Mar 28, 2016, at 1:15 PM, Guenter Roeck wrote:
>
>>> What SoC(s) is this in. Use SoC specific compatible strings please.
>>
>> So ipq4019 wins the race because we are the first to try to enable watchdog
>> for this block?
>>
>> qcom,kpss-ipq4019 ?
>>
> It is a dedicated watchdog block, isn
This should have been bumped to 100 when the extra pins
were added in the original pinctrl patch
CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
For this SoC the register offsets changed from previous versions to be
separated by a larger amount.
CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +-
1 file changed, 5 insertions(+), 5
Without this, we would fail to set the mode to gpio if trying to
configure for that mode
CC: linus.wall...@linaro.org
CC: bjorn.anders...@linaro.org
Signed-off-by: Matthew McClintock
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Drivers for these don't exist yet so we will add them as fixed clocks
so we don't BUG() if we change clocks that reference these clocks.
Signed-off-by: Matthew McClintock
---
drivers/clk/qcom/gcc-ipq4019.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/cl
This adds the blsp_dma node to the device tree and the required
properties for using DMA with serial
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4
arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 +++
2 files changed, 19 insertions
Add cpufreq driver for ipq4019 SoC. This driver simply instantiates
cpufreq-dt.
Signed-off-by: Matthew McClintock
---
drivers/cpufreq/Kconfig.arm | 9 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/ipq4019-cpufreq.c | 35 +++
3 files
For certain parts and some versions of TZ, TZ will reset the chip
when a BARK is triggered even though it was not configured here. So
by default let's configure this BARK time as well.
Signed-off-by: Matthew McClintock
---
drivers/watchdog/qcom-wdt.c | 5 +
1 file changed, 5 inser
This adds some operating points for cpu frequeny scaling
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1937edf..db48fd3 100644
: Stanimir Varbanov
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8
arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +
2 files changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
b/arch
This will allow boards to enable watchdog support
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4
arch/arm/boot/dts/qcom-ipq4019.dtsi | 8
2 files changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1
This will allow boards to enable the SPI bus
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 37 +++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 +
2 files changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts
Commit 0dfd582e026a ("watchdog: qcom: use timer devicetree binding") moved
to use the watchdog as a subset timer register block. Some devices have the
watchdog completely standalone with slightly different register offsets as
well so let's account for the differences here.
Signed-
This will allow boards to enable the I2C bus
CC: Sricharan R
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 99e64f4
Update the compatible string to add new device tree binding
CC: linux-watch...@vger.kernel.org
Signed-off-by: Matthew McClintock
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/qcom
Update the compatible string to align with driver
CC: linux-watch...@vger.kernel.org
Signed-off-by: Matthew McClintock
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/watchdog
This will allow these types of boards to be rebooted.
Signed-off-by: Matthew McClintock
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 00a5e9e..acb851d 100644
--- a
When this was added not all the remaining defines were switched over to
use enums, so let's complete that process here
Reported-by: Stephen Boyd
Signed-off-by: Matthew McClintock
---
drivers/clk/qcom/gcc-ipq4019.c | 60 ++
1 file changed, 25 inser
On Mar 24, 2016, at 1:44 AM, Viresh Kumar wrote:
>
> On 23-03-16, 17:05, Matthew McClintock wrote:
>> Add cpufreq driver for ipq4019 SoC. This driver simply instantiates
>> cpufreq-dt.
>>
>> Signed-off-by: Matthew McClintock
>> ---
>> drivers/cpufreq/K
On Mar 23, 2016, at 5:42 PM, Stephen Boyd wrote:
>
> On 03/23, Matthew McClintock wrote:
>> For certain parts and some versions of TZ, TZ will reset the chip
>> when a BARK is triggered even though it was not configured here. So
>> by default let's configure this BA
> On Mar 23, 2016, at 5:26 PM, Stephen Boyd wrote:
>
> On 03/23/2016 03:05 PM, Matthew McClintock wrote:
>> Update the compatible string to align with driver
>>
>> CC: linux-watch...@vger.kernel.org
>> Signed-off-by: Matthew McClintock
>
> I ha
On Mar 24, 2016, at 11:17 AM, Guenter Roeck wrote:
>
>>> Why isn't TZ configuring the bark time to what it wants? I'm lost
>>> why we have to do this for them.
>>
>> So it was done like this to ensure we had a valid upgrade. The bootloader is
>> using the watchdog to ensure the system is bootab
gt;> > properly detect these bad interrupts and print warning messages.
>> >
>> > Signed-off-by: Matthew McClintock
>> > Signed-off-by: Varadarajan Narayanan
>> > ---
>> > drivers/spi/spi-qup.c | 20 +++-
>> > 1 fi
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