Hi Laurent,
On 1/21/21 11:37 PM, Laurent Pinchart wrote:
> Hi Michal,
>
> Thank you for the patch.
>
> On Thu, Jan 21, 2021 at 01:36:07PM +0100, Michal Simek wrote:
>> From: Laurent Pinchart
>>
>> Enable the dpsub device and wire it up to the PS-GTR PHY l
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.
Signed-off-by: Michal Simek
---
Changes in v2: None
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts| 17 ++
.../boot/dts
Enable psgtr driver and write clocks property to get sata to work.
Signed-off-by: Michal Simek
---
Changes in v2: None
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts| 10 +++
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts| 28 +++
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts
0 12500
0 0 5
clock-generator.1 000 0
0 0 5
...
Signed-off-by: Michal Simek
---
Changes in v2: None
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts| 56 ++-
.../boot/dts/xilinx/zynqmp
Enable reset controller to be prepared for use.
Signed-off-by: Michal Simek
---
Changes in v2:
- Remove reset description for IPs from this patch. IPs will be enabled
separately with DT binding update.
- Change patch subject
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +
1 file changed
Add missing arasan controller with clocks. Disable it by default. Every
board can enable it with specifying others properties.
Signed-off-by: Michal Simek
---
Changes in v2: None
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12
Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c
structure compare to revA. The rest of the board is the same from software
perspective.
Also enable DMAs and QSPI.
Signed-off-by: Michal Simek
---
Changes in v2: None
arch/arm64/boot/dts/xilinx/Makefile | 1
On 1/21/21 11:41 AM, Michael Walle wrote:
> Hi,
>
> Am 2021-01-21 11:23, schrieb Michal Simek:
>>>> Back to your case. Board is cheap which is not all the time case for
>>>> any
>>>> xilinx board but you have only uart, sd and partially described
Add label which is used by bootloader for adding bootloader specific flag.
Signed-off-by: Michal Simek
---
Changes in v2: None
U-Boot needs to add u-boot,dm-pre-reloc; property
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch
Trivial example fix.
Signed-off-by: Michal Simek
---
Documentation/devicetree/bindings/usb/dwc3-xilinx.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
index
From: Laurent Pinchart
Add a DT node for the DisplayPort DMA engine (DPDMA).
Signed-off-by: Laurent Pinchart
Acked-by: Michal Simek
Signed-off-by: Michal Simek
---
Changed node possition.
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
From: Laurent Pinchart
Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.
Signed-off-by: Laurent Pinchart
Signed-off-by: Michal Simek
---
Wire all the boards
---
.../boot/dts/xilinx/zynqmp-zcu100-revC.dts| 31
Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.
Signed-off-by: Laurent Pinchart
Signed-off-by: Michal Simek
---
Change node position and label.
---
.../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 +
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
]
http://lore.kernel.org/r/20200718001347.25451-1-laurent.pinch...@ideasonboard.com
[3] http://lore.kernel.org/r/cover.1611224800.git.michal.si...@xilinx.com
Thanks,
Michal
Laurent Pinchart (2):
arm64: dts: zynqmp: Add DPDMA node
arm64: dts: zynqmp: Wire up the DisplayPort subsystem
Michal
Trivial fix.
Signed-off-by: Michal Simek
---
Documentation/devicetree/bindings/arm/xilinx.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml
b/Documentation/devicetree/bindings/arm/xilinx.yaml
index ae0ef1bf7965
Add missing iommu IDs to all IPs which have IDs assigned.
Signed-off-by: Michal Simek
---
Changes in v2: None
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 52 ++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts
Xilinx ZynqMP SoC has FPD (Full Power Domain) and LPD (Low Power Domain)
watchdogs. There are cases where also LPD WDT should be used by Arm cores
that's why list it with disabled status.
Signed-off-by: Michal Simek
---
Changes in v2: None
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4
Add missing ZynqMP qspi IP. It works in single mode only.
Signed-off-by: Michal Simek
---
Changes in v2: None
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 14 ++
2 files changed, 18 insertions(+)
diff --git a/arch
Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Signed-off-by: Michal Simek
---
Changes
u48 chip on zcu111 is si5382 not si5328.
Signed-off-by: Michal Simek
---
Changes in v2: None
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
b/arch/arm64/boot/dts/xilinx
with DT binding update.
- Change patch subject
Michal Simek (12):
arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
arm64: dts: zynqmp: Enable reset controller driver
Hi,
On 1/21/21 11:13 AM, Michael Walle wrote:
> Hi,
>
> Am 2021-01-21 10:57, schrieb Michal Simek:
>> Hi,
>>
>> On 1/21/21 10:35 AM, Michael Walle wrote:
>>> Hi Michal,
>>>
>>> Am 2021-01-21 10:25, schrieb Michal Simek:
>>&
st 2. 12. 2020 v 15:14 odesílatel Michal Simek napsal:
>
> The commit 3eb619b2f7d8 ("scripts/dtc: Update to upstream version
> v1.6.0-11-g9d7888cbf19c") updated dtc version which also contained DTC
> commit
> "81e0919a3e21 checks: Add interrupt provider test"
Hi,
On 12/7/20 10:32 AM, Michal Simek wrote:
>
>
> On 06. 12. 20 23:38, Laurent Pinchart wrote:
>> Hi Michal,
>>
>> Thank you for the patch.
>>
>> On Wed, Dec 02, 2020 at 03:06:03PM +0100, Michal Simek wrote:
>>> Enable reset controller for
Hi,
On 1/21/21 10:35 AM, Michael Walle wrote:
> Hi Michal,
>
> Am 2021-01-21 10:25, schrieb Michal Simek:
>> On 1/20/21 8:40 PM, Michael Walle wrote:
>>> Add support for the Ebang EBAZ4205 board. This board was once used as a
>>> control board for a bitcoin mi
Hi
On 1/20/21 8:40 PM, Michael Walle wrote:
> Add support for the Ebang EBAZ4205 board. This board was once used as a
> control board for a bitcoin mining device. Nowawdays it is sold as a cheap
> Zynq-7000 eval board.
>
> Michael Walle (3):
> dt-bindings: add ebang vendor prefix
>
On 1/18/21 3:43 AM, Nava kishore Manne wrote:
> From: Appana Durga Kedareswara rao
>
> This patch adds binding doc for versal fpga manager driver.
>
> Signed-off-by: Nava kishore Manne
> Signed-off-by: Appana Durga Kedareswara rao
> ---
> .../bindings/fpga/xlnx,versal-fpga.yaml | 33
There is no reason to keep PM_API_MAX around. The commit acfdd18591ea
("firmware: xilinx: Use hash-table for api feature check") removed its
usage that's why it is not used anywhere now.
Signed-off-by: Michal Simek
---
include/linux/firmware/xlnx-zynqmp.h | 1 -
1 file changed,
/microblaze_oprofile.c
> deleted file mode 100644
> index def17e59888e..
> --- a/arch/microblaze/oprofile/microblaze_oprofile.c
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - * Microblaze oprofile code
> - *
> - * Copyright (C) 2009 Michal Simek
> - * Copyright (C) 2009 Pet
On 11. 01. 21 16:33, Lars-Peter Clausen wrote:
> On 1/11/21 10:32 AM, Michal Simek wrote:
>> Hi Lars,
>>
>> On 10. 01. 21 16:43, Lars-Peter Clausen wrote:
>>> On 1/10/21 4:16 PM, Paul Thomas wrote:
>>>> On Fri, Jan 8, 2021 at 1:36 PM Radhey Shyam Pandey
anuary 8, 2021 9:27 PM
>>>> To: Radhey Shyam Pandey
>>>> Cc: Dan Williams ; Vinod Koul
>>>> ; Michal Simek ; Matthew Murrian
>>>> ; Romain Perier
>>>> ; Krzysztof Kozlowski ; Marc
>>>> Ferland ; Sebastian von Ohr
>>>> ; d
On 07. 01. 21 11:47, Linus Walleij wrote:
> On Thu, Jan 7, 2021 at 11:29 AM Michal Simek wrote:
>> On 07. 01. 21 11:17, Linus Walleij wrote:
>>> On Wed, Jan 6, 2021 at 1:27 PM Srinivas Neeli
>>> wrote:
>
>>>> @@ -591,6 +591,9 @@ static in
On 07. 01. 21 11:17, Linus Walleij wrote:
> On Wed, Jan 6, 2021 at 1:27 PM Srinivas Neeli
> wrote:
>
>> Add check to see if gpio-width property does not exceed 32.
>> If it exceeds then return -EINVAL.
>>
>> Signed-off-by: Srinivas Neeli
>
> Aha
>
>> @@ -591,6 +591,9 @@ static int
Hi,
On 26. 12. 20 7:41, Syed Nayyar Waris wrote:
> Hello Linus,
>
> Since this patchset primarily affects GPIO drivers, would you like
> to pick it up through your GPIO tree?
>
> (Note: Patchset resent with the new macro and relevant
> functions shifted to a new header clump_bits.h [Linus
alue() and bitmap_set_value(). The code is now simpler
>> to read and understand. Moreover, instead of looping for each bit
>> in xgpio_set_multiple() function, now we can check each channel at
>> a time and save cycles.
>>
>> Cc: William Breathitt Gray
>> Cc: B
On 26. 12. 20 7:45, Syed Nayyar Waris wrote:
> Add extra check to see if sum of widths does not exceed 64. If it
> exceeds then return -EINVAL alongwith appropriate error message.
>
> Cc: Michal Simek
> Signed-off-by: Syed Nayyar Waris
> ---
> drivers/gpio/gpio-xilinx.c
ATTREE
> select PCI_DOMAINS_GENERIC if PCI
> select PCI_SYSCALL if PCI
> - select TRACING_SUPPORT
> select VIRT_TO_BUS
> select CPU_NO_EFFICIENT_FFS
> select MMU_GATHER_NO_RANGE
>
make sense.
Applied.
Thanks,
Michal
--
Michal Simek, Ing. (M
support for TIF_NOTIFY_SIGNAL
- Small header fix
Geert Uytterhoeven (1):
microblaze: Replace by
Jens Axboe (1):
microblaze: add support for TIF_NOTIFY_SIGNAL
Michal Simek (1):
microblaze: Remove noMMU code
arch/microblaze/Kconfig | 53 +-
arc
Hi Stephen,
On 16. 12. 20 2:00, Stephen Rothwell wrote:
> Hi all,
>
> On Thu, 10 Dec 2020 15:03:23 +0100 Michal Simek wrote:
>>
>> On 10. 12. 20 5:58, Stephen Rothwell wrote:
>>>
>>> Today's linux-next merge of the tip tree got conflicts in:
>&
> @@ -273,6 +292,10 @@ enum zynqmp_pm_request_ack {
> };
>
> enum pm_node_id {
> + NODE_TCM_0_A = 0xf,
> + NODE_TCM_0_B = 0x10,
> + NODE_TCM_1_A = 0x11,
> + NODE_TCM_1_B = 0x12,
Please convert these hex to int to be aligned with the rest.
> NODE_SD_0 = 39,
> NODE_SD_1,
> };
>
When that fixed feel free to add.
Acked-by: Michal Simek
Thanks,
Michal
be different but there are a lot
of issues like this that's why
Acked-by: Michal Simek
Thanks,
Michal
hanks for letting me know. I will mentioned it to Linus.
Your resolution is correct.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
On 01. 12. 20 15:29, Michal Simek wrote:
> kernel-doc is reporting some style issues. The patch is fixing them.
>
> Signed-off-by: Michal Simek
> ---
>
> drivers/firmware/xilinx/zynqmp.c | 46
> 1 file changed, 23 insertions(+), 23 d
Hi,
On 02. 12. 20 8:38, Michal Simek wrote:
> Hi,
>
> for being able to review new changes more effectively it is good to get rid
> of existing kernel-doc and checkpatch violations.
> That's why this small clean up series.
>
> Based on
> h
čt 26. 11. 2020 v 14:32 odesílatel Michal Simek
napsal:
>
> This configuration is obsolete and likely none is really using it. That's
> why remove it to simplify code.
>
> Note about CONFIG_MMU in hw_exception_handler.S is left intentionally
> for better comment understan
Hi,
On 08. 12. 20 13:35, quanyang.w...@windriver.com wrote:
> From: Quanyang Wang
>
> The Zynqmp Ultrascale clock controller generates clocks for peripherals,
> so we need to enable it when ARCH_ZYNQMP is selected.
>
> Signed-off-by: Quanyang Wang
> ---
> drivers/clk/zynqmp/Kconfig | 1 +
>
Hi Laurent,
On 07. 12. 20 23:16, Laurent Pinchart wrote:
> Hi Michal,
>
> On Mon, Dec 07, 2020 at 10:39:25AM +0100, Michal Simek wrote:
>> On 06. 12. 20 23:46, Laurent Pinchart wrote:
>>> On Wed, Dec 02, 2020 at 03:06:05PM +0100, Michal Simek wrote:
>>>> A
On 06. 12. 20 23:48, Laurent Pinchart wrote:
> On Mon, Dec 07, 2020 at 12:46:56AM +0200, Laurent Pinchart wrote:
>> Hi Michal,
>>
>> Thank you for the patch.
>>
>> On Wed, Dec 02, 2020 at 03:06:05PM +0100, Michal Simek wrote:
>>> Add label which i
Hi,
On 06. 12. 20 23:46, Laurent Pinchart wrote:
> Hi Michal,
>
> Thank you for the patch.
>
> On Wed, Dec 02, 2020 at 03:06:05PM +0100, Michal Simek wrote:
>> Add label which is used by bootloader for adding bootloader specific flag.
>>
>> Signed-off-by: Michal
On 06. 12. 20 23:38, Laurent Pinchart wrote:
> Hi Michal,
>
> Thank you for the patch.
>
> On Wed, Dec 02, 2020 at 03:06:03PM +0100, Michal Simek wrote:
>> Enable reset controller for several IPs.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
&g
property is less critical, but creates
ambiguities when used in interrupt-map properties, so warn about this as
well now."
That's why add address-cells property to gic and gpio nodes to get rid of
this warning.
CC: Andre Przywara
Signed-off-by: Michal Simek
---
I was grepping DTSes in th
Add label which is used by bootloader for adding bootloader specific flag.
Signed-off-by: Michal Simek
---
U-Boot needs to add u-boot,dm-pre-reloc; property
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/xilinx
Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c
structure compare to revA. The rest of the board is the same from software
perspective.
Also enable DMAs and QSPI.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
.../boot/dts/xilinx
Add missing ZynqMP qspi IP. It works in single mode only.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 14 ++
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx
Add missing arasan controller with clocks. Disable it by default. Every
board can enable it with specifying others properties.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12
2 files
Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Signed-off-by: Michal Simek
---
Based
Add missing iommu IDs to all IPs which have IDs assigned.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 52 ++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
Xilinx ZynqMP SoC has FPD (Full Power Domain) and LPD (Low Power Domain)
watchdogs. There are cases where also LPD WDT should be used by Arm cores
that's why list it with disabled status.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4
arch/arm64/boot
Enable reset controller for several IPs.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 29 ++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 68923fbd0e89
Enable psgtr driver and write clocks property to get sata to work.
Signed-off-by: Michal Simek
---
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts| 10 +++
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts| 28 +++
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts| 10
.
And mio-bank patch requires update in dt-binding which has been posted here
https://lore.kernel.org/r/5fa17dfe4b42abefd84b4cbb7b8bcd4d31398f40.1606914986.git.michal.si...@xilinx.com
Thanks,
Michal
Michal Simek (12):
arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
arm64: dts: zynqmp: Add DT
0 12500
0 0 5
clock-generator.1 000 0
0 0 5
...
Signed-off-by: Michal Simek
---
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts| 56 ++-
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts| 45
u48 chip on zcu111 is si5382 not si5328.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.
Signed-off-by: Michal Simek
---
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts| 17 ++
.../boot/dts/xilinx/zynqmp-zcu106
Xilinx ZynqMP has 3 mio banks and all of them are valid. That's why also
list the first one which is missing. Property is enumeration not range.
Signed-off-by: Michal Simek
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This additional newline is useless and also reported by checkpatch
--strict.
Signed-off-by: Michal Simek
---
(no changes since v1)
include/linux/firmware/xlnx-zynqmp.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx
,
Michal
Changes in v2:
- keep variable name and type on the same line - reported by Joe Perches
Michal Simek (3):
firmware: xilinx: Remove additional newline
firmware: xilinx: Add a blank line after function declaration
firmware: xilinx: Properly align function parameter
include/linux/firmware
Fix parameters alignment reported by checkpatch --strict.
Signed-off-by: Michal Simek
---
Changes in v2:
- keep variable name and type on the same line - reported by Joe Perches
include/linux/firmware/xlnx-zynqmp.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Fix all these issues which are also reported by checkpatch --strict.
Signed-off-by: Michal Simek
---
(no changes since v1)
include/linux/firmware/xlnx-zynqmp.h | 34
1 file changed, 34 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include
On 01. 12. 20 20:42, Joe Perches wrote:
> On Tue, 2020-12-01 at 16:50 +0100, Michal Simek wrote:
>> Fix parameters alignment reported by checkpatch --strict.
>
> Please use a newer checkpatch as the 80 column warning
> isn't enforced quite the same way.
I was using i
On 01. 12. 20 22:26, Greg KH wrote:
> On Tue, Dec 01, 2020 at 01:03:59PM +0100, Michal Simek wrote:
>>
>>
>> On 01. 12. 20 12:51, Zou Wei wrote:
>>> Fix the following sparse warning:
>>>
>>> drivers/firmware/xilinx/zynqmp.c:32:1: warning: sy
Fix all these issues which are also reported by checkpatch --strict.
Signed-off-by: Michal Simek
---
include/linux/firmware/xlnx-zynqmp.h | 34
1 file changed, 34 insertions(+)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx
This additional newline is useless and also reported by checkpatch
--strict.
Signed-off-by: Michal Simek
---
include/linux/firmware/xlnx-zynqmp.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index f84244ea633b
Fix parameters alignment reported by checkpatch --strict.
Signed-off-by: Michal Simek
---
include/linux/firmware/xlnx-zynqmp.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index
,
Michal
Michal Simek (3):
firmware: xilinx: Remove additional newline
firmware: xilinx: Add a blank line after function declaration
firmware: xilinx: Properly align function parameter
include/linux/firmware/xlnx-zynqmp.h | 45
1 file changed, 40 insertions(+), 5
kernel-doc is reporting some style issues. The patch is fixing them.
Signed-off-by: Michal Simek
---
drivers/firmware/xilinx/zynqmp.c | 46
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware
eature_data - PM API Feature data
>
The patch is good but I am missing fixed tag to get it to LTS.
When you add it please add my
Reviewed-by: Michal Simek
Thanks,
Michal
Fix comment about targeted extension card. It was likely just c error.
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-zc770-xm011.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts
b/arch/arm/boot/dts/zynq-zc770-xm011.dts
This configuration is obsolete and likely none is really using it. That's
why remove it to simplify code.
Note about CONFIG_MMU in hw_exception_handler.S is left intentionally
for better comment understanding.
Cc: Mike Rapoport
Cc: Arnd Bergmann
Signed-off-by: Michal Simek
---
Changes in v2
he binding.
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-zturn-common.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi
b/arch/arm/boot/dts/zynq-zturn-common.dtsi
index 84f3c85c5bab..bf5d1c4568b0 100644
--- a/arch/arm/boot/dts/
: eeprom@2: 'size' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property
>From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml
by converting them to new binding.
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-zc770-
s/leds-gpio.yaml
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-zc702.dts | 2 +-
arch/arm/boot/dts/zynq-zybo-z7.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 27cd6cb52f1b..10a
-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml
Similar change has been done for Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-7000.dtsi | 2 +-
1 file changed, 1 in
ress-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc: '#size-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc: 'ranges' is a required property
>From schema: .../Documentation/devicetree/bindings/sram/sram.yaml
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/z
Hi,
several issues have been reported from binding check. The series is
addressing most of them.
Patches are based on
https://github.com/Xilinx/linux-xlnx/tree/zynq/dt
Thanks,
Michal
Michal Simek (5):
ARM: zynq: Fix compatible string for adi,adxl345 chip
ARM: zynq: Rename bus to be align
default-state = "off";
> - };
> - };
> -
> - gpio-keys {
> - compatible = "gpio-keys";
> - autorepeat;
> - K1 {
> - label = "K1";
> -
On 25. 11. 20 13:57, Arnd Bergmann wrote:
> On Wed, Nov 25, 2020 at 1:14 PM Michal Simek wrote:
>>
>> And second part. I know I removed that Kconfig macros for it but maybe
>> good to talk about what needs to change to support different page size
>> for systems with
út 29. 9. 2020 v 13:43 odesílatel Michal Simek napsal:
>
> DT schema is checking tuples which should be properly separated. The patch
> is doing this separation to avoid the following warning:
> ..yaml: axi: pcie@fd0e:ranges: [[33554432, 0, 3758096384, 0,
> 375809638
čt 12. 11. 2020 v 13:52 odesílatel Michal Simek
napsal:
>
> The support to driver was added by commit ffdbae28d9d1 ("drivers: soc:
> xilinx: Use mailbox IPI callback") that's why also enable it via DT by
> default. It setups communication with firmware via IPI interface.
>
út 10. 11. 2020 v 16:20 odesílatel Michal Simek
napsal:
>
> The reason for this change is that after change from amba to axi U-Boot
> started to show error like:
> Unable to update property /axi/ethernet@ff0e:mac-address,
> err=FDT_ERR_NOTFOUND
> Unable to update prop
Hi Mike,
On 25. 11. 20 13:07, Mike Rapoport wrote:
> On Wed, Nov 25, 2020 at 12:30:32PM +0100, Michal Simek wrote:
>> This configuration is obsolete and likely none is really using it. That's
>> why remove it to simplify code.
>>
>> Cc: Arnd Bergmann
>
with kernel.
Also there is need to allocate initramfs because origin mapping is done
only to the _end symbol which stayed at the same location. The follow up
patch will explain reasons behind it.
Signed-off-by: Michal Simek
---
arch/microblaze/include/asm/sections.h | 2 ++
arch/microblaze/kernel
etween _text and _end for kernel itself. Initrd or initramfs is
mapped below. That's why there is all the time gap between _end and
__initramfs_start covered by TLB which can be used for early page
allocation.
Signed-off-by: Michal Simek
---
arch/microblaze/include/asm/sections.h | 1 +
arch/micr
This configuration is obsolete and likely none is really using it. That's
why remove it to simplify code.
Cc: Arnd Bergmann
Signed-off-by: Michal Simek
---
If anybody is using this configuration please let me know.
---
arch/microblaze/Kconfig | 53 +-
arch/microblaze
On 24. 11. 20 9:18, Wendy Liang wrote:
> Fix compilation warning when ZYNQMP_FIRMWARE is not defined.
>
> include/linux/firmware/xlnx-zynqmp.h: In function
> 'zynqmp_pm_get_eemi_ops':
> include/linux/firmware/xlnx-zynqmp.h:363:9: error: implicit
> declaration of function 'ERR_PTR'
>
On 24. 11. 20 6:52, Rajan Vaja wrote:
> From: Amit Sunil Dhamne
>
> Currently array of fix length PM_API_MAX is used to cache
> the pm_api version (valid or invalid). However ATF based
> PM APIs values are much higher then PM_API_MAX.
> So to include ATF based PM APIs also, use hash-table to
Hi,
On 24. 11. 20 14:02, Arnd Bergmann wrote:
> On Tue, Nov 24, 2020 at 1:54 PM Michal Simek wrote:
>> On 24. 11. 20 6:52, Rajan Vaja wrote:
>>
>> Some lines should be added.
>>
>> Cc: stable
>> Fixes: f3217d6f2f7a ("firmware: xilinx: fix out-of-b
nqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -50,10 +50,6 @@
> #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
> #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
>
> -/* Feature check status */
> -#define PM_FEATURE_INVALID -1
> -#define PM_FEATURE_UN
t;>> (.text+0xa1fc): undefined reference to `start_isolate_page_range'
>>>> microblaze-linux-ld: (.text+0xa40c): undefined reference to
>>>> `test_pages_isolated'
>>>> microblaze-linux-ld: (.text+0xa47c): undefined reference to
>>>> `undo_isolate_page_range'
MMC_TIMING_MMC_HS200:
> /* For 200MHz clock, 30 Taps are available */
> tap_max = 30;
> + break;
> default:
> break;
> }
>
No problem with it.
Acked-by: Michal Simek
Thanks,
Michal
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