Reviewed-by: Mikko Perttunen
On 22.02.2017 17:14, Peter De Schrijver wrote:
If the PLL is on, only warn if the defaults are not yet set. Otherwise be
silent.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-tegra210.c | 18 --
1 file changed, 12 insertions(+), 6
Reviewed-by: Mikko Perttunen
On 22.02.2017 17:14, Peter De Schrijver wrote:
Return the actually achieved rate in cfg->output_rate rather than just the
requested rate. This is important to make clk_round_rate return the correct
result.
Signed-off-by: Peter De Schrijver
---
drivers/clk/te
Reviewed-by: Mikko Perttunen
On 22.02.2017 17:14, Peter De Schrijver wrote:
When used as part of fractional ndiv calculations, the current range is not
enough because the denominator of the fraction is multiplied with m.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk.h | 2
gt;plat->force_thresh_dma_mode)
priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
Reviewed-by: Mikko Perttunen
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
When DMA mapping an SKB fragment, the mapping must be checked for
errors, otherwise the DMA debug code will complain upon unmap.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 ++
1 file
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
clk_prepare_enable() and clk_disable_unprepare() for this clock aren't
properly balanced, which can trigger a WARN_ON() in the common clock
framework.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/stmmac_
move platform: %d\n", err);
+
+ err = data->remove(pdev);
+ if (err < 0)
+ dev_err(&pdev->dev, "failed to remove subdriver: %d\n", err);
+
+ stmmac_remove_config_dt(pdev, priv->plat);
+
+ return err;
}
static const struct of_device_id dwc_eth_dwmac_match[] = {
- { .compatible = "snps,dwc-qos-ethernet-4.10", },
+ { .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
{ }
};
MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
Reviewed-by: Mikko Perttunen
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
Program the receive queue size based on the RX FIFO size and enable
hardware flow control for large FIFOs.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 12 +++
drivers/net/ethernet/stm
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
ethernet QOS IP core. The binding that it uses is slightly different
from existing ones because of the integration (clocks, resets, ...).
Signed-off-by: Thierry Redi
;i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0",
+ "vimclk_sync",
};
My GCC spews a bunch of warnings because these are "const char * const"
and are passed to tegra_audio_sync_clk_init which takes "const
Series,
Reviewed-by: Mikko Perttunen
Tested-by: Mikko Perttunen
On 02/23/2017 12:44 PM, Peter De Schrijver wrote:
A number of bug fixes for the Tegra210 clock implementation.
Changelog:
v2: add better description for 'remove non-existing pll_m_out1 clock'
Peter De Schrijver
On 6/26/20 1:29 PM, Sandipan Patra wrote:
Add the chip IDs for NVIDIA Tegra186, Tegra194 and Tegra234
SoC family.
families
Signed-off-by: Sandipan Patra
---
include/soc/tegra/fuse.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/soc/tegra/fuse.h b/include
On 9/21/20 4:10 PM, Qinglang Miao wrote:
Simplify the return expression.
Signed-off-by: Qinglang Miao
---
drivers/gpu/host1x/cdma.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c
index e8d3fda91..08a0f9e10 1006
Not sure which boards this issue is happening on, but looking at my
hobby kernel's git history (from a couple of years ago, memory is a bit
hazy), the commit labeled "Add support for TX2" adds code to drop from
EL2 to EL1 at boot.
Mikko
On 9/16/20 10:06 PM, Jon Hunter wrote:
On 16/09/2020 17
Rob, Mark,
could you review this and the 3/3 in the series (which I'm sending to
you momentarily)?
Thanks,
Mikko.
On 04.04.2017 16:43, Mikko Perttunen wrote:
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-o
On 04.04.2017 16:43, Mikko Perttunen wrote:
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen
---
v2:
- Only one regs entry
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++
1 file changed, 7
Ah, had to forget something :)
Reviewed-by: Mikko Perttunen
On 19.04.2017 21:24, Arnd Bergmann wrote:
When IOMMU_IOVA is not built-in but host1x is, we get a link error:
drivers/gpu/host1x/dev.o: In function `host1x_remove':
dev.c:(.text.host1x_remove+0x50): undefined referen
On 19.04.2017 21:24, Arnd Bergmann wrote:
When dma_addr_t and phys_addr_t are not the same size, we get a warning
from the dma_alloc_wc function:
drivers/gpu/host1x/cdma.c: In function 'host1x_pushbuffer_init':
drivers/gpu/host1x/cdma.c:94:48: error: passing argument 3 of 'dma_alloc_wc'
from in
On 20.04.2017 11:25, Arnd Bergmann wrote:
On Thu, Apr 20, 2017 at 9:02 AM, Mikko Perttunen wrote:
On 19.04.2017 21:24, Arnd Bergmann wrote:
When dma_addr_t and phys_addr_t are not the same size, we get a warning
from the dma_alloc_wc function:
drivers/gpu/host1x/cdma.c: In function
On 20.04.2017 13:02, Arnd Bergmann wrote:
On Thu, Apr 20, 2017 at 11:44 AM, Mikko Perttunen wrote:
On 20.04.2017 11:25, Arnd Bergmann wrote:
On Thu, Apr 20, 2017 at 9:02 AM, Mikko Perttunen wrote:
On 19.04.2017 21:24, Arnd Bergmann wrote:
I don't think this can be a per-platform p
can be set individually; however,
this is just a hint as all CPUs in a cluster will run at
the maximum rate of non-idle CPUs in the cluster.
Signed-off-by: Mikko Perttunen
---
drivers/cpufreq/Kconfig.arm| 7 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra186
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen
---
.../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644
On 04/03/2017 05:06 PM, Thierry Reding wrote:
On Mon, Apr 03, 2017 at 03:42:24PM +0300, Mikko Perttunen wrote:
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen
---
.../arm/tegra/nvidia,tegra186
On 04/03/2017 05:24 PM, Jon Hunter wrote:
On 03/04/17 13:42, Mikko Perttunen wrote:
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen
---
.../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22
On 04/03/2017 05:47 PM, Thierry Reding wrote:
On Mon, Apr 03, 2017 at 03:42:23PM +0300, Mikko Perttunen wrote:
Add a new cpufreq driver for Tegra186 (and likely later).
The CPUs are organized into two clusters, Denver and A57,
with two and four cores respectively. CPU frequency can be
adjusted
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen
---
v2:
- Only one regs entry.
- s/Phandle/phandle/
.../arm/tegra/nvidia,tegra186-ccplex-cluster.txt| 17 +
1 file changed
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen
---
v2:
- Only one regs entry
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot
can be set individually; however,
this is just a hint as all CPUs in a cluster will run at
the maximum rate of non-idle CPUs in the cluster.
Signed-off-by: Mikko Perttunen
---
v2:
- Many cosmetic / restructuring changes
- Only one aperture read from DT now, with a new
structure containing the
On 05.04.2017 06:36, Stephen Rothwell wrote:
Hi all,
After merging the tip tree, today's linux-next build (arm
multi_v7_defconfig) failed like this:
drivers/gpu/built-in.o:(__tracepoints+0x64): multiple definition of
`__tracepoint_remove_device_from_group'
drivers/iommu/built-in.o:(__tracepoin
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index f8fda446a6a6..f05ebb14fa63 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -27,6 +27,7 @@
#define
From: Matt Craighead
According to the GICv2 specification, the GICD_ICFGR0,
or GIC_DIST_CONFIG[0] register is read-only. Therefore
avoid writing to it.
Signed-off-by: Matt Craighead
[mperttu...@nvidia.com: commit message rewritten]
Signed-off-by: Mikko Perttunen
---
drivers/irqchip/irq-gic.c
On 06.04.2017 12:26, Marc Zyngier wrote:
On 06/04/17 09:17, Mikko Perttunen wrote:
From: Matt Craighead
According to the GICv2 specification, the GICD_ICFGR0,
or GIC_DIST_CONFIG[0] register is read-only. Therefore
avoid writing to it.
Have you verified that this also applies to pre-v2 GICs
On 07.04.2017 10:32, Marc Zyngier wrote:
On 07/04/17 07:49, Mikko Perttunen wrote:
On 06.04.2017 12:26, Marc Zyngier wrote:
On 06/04/17 09:17, Mikko Perttunen wrote:
From: Matt Craighead
According to the GICv2 specification, the GICD_ICFGR0,
or GIC_DIST_CONFIG[0] register is read-only
On 04/11/2017 09:35 AM, Viresh Kumar wrote:
On 04-04-17, 16:43, Mikko Perttunen wrote:
Add a new cpufreq driver for Tegra186 (and likely later).
The CPUs are organized into two clusters, Denver and A57,
with two and four cores respectively. CPU frequency can be
adjusted by writing the desired
can be set individually; however,
this is just a hint as all CPUs in a cluster will run at
the maximum rate of non-idle CPUs in the cluster.
Signed-off-by: Mikko Perttunen
Acked-by: Viresh Kumar
---
v3:
- Fixed size parameter of dma_free_coherent
drivers/cpufreq/Kconfig.arm| 6
v_err(&pdev->dev, "failed to get reset: %d\n", err);
return err;
}
Reviewed-by: Mikko Perttunen
On 01.07.2017 05:53, Eduardo Valentin wrote:
Hey Mikko,
Sorry for the late answer,
Likewise,
On Fri, Jun 16, 2017 at 02:28:25PM +0300, Mikko Perttunen wrote:
On Tegra186, the BPMP (Boot and Power Management Processor) exposes an
interface to thermal sensors on the system-on-chip. This
On 01.07.2017 02:56, Eduardo Valentin wrote:
On Fri, Jun 16, 2017 at 02:28:22PM +0300, Mikko Perttunen wrote:
This adds the thermal sensor device provided by the BPMP, and the
relevant thermal sensors to the Tegra186 device tree.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia
Thanks for the patch, didn't consider this case. I really need to get
together some system to automatically test on multiple platforms.. :)
Reviewed-by: Mikko Perttunen
On 10.07.2017 22:33, Paul Kocialkowski wrote:
When there is no device to attach to the IOMMU domain, as may be the
On 07/11/2017 05:44 PM, Paul Kocialkowski wrote:
On Tue, 2017-07-11 at 14:37 +, Marcel Ziswiler wrote:
On Tue, 2017-07-11 at 11:49 +0300, Paul Kocialkowski wrote:
On Mon, 2017-07-10 at 21:33 +0200, Paul Kocialkowski wrote:
When there is no device to attach to the IOMMU domain, as may be
th
AIUI, the PWM framework already exposes a sysfs node with period
information. We should just use that instead of adding a new driver for
this.
In any case, we cannot add something like this to device tree since it's
not a hardware device.
Mikko
On 21.02.2018 08:58, Rajkumar Rampelli wrote:
On 21.02.2018 16:46, Guenter Roeck wrote:
On 02/20/2018 11:15 PM, Mikko Perttunen wrote:
AIUI, the PWM framework already exposes a sysfs node with period
information. We should just use that instead of adding a new driver
for this.
I am kind of lost. Please explain.
Are you saying that we
->driver_data =
data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
cpufreq_table_validate_and_show(policy, cluster->table);
+ break;
}
policy->cpuinfo.transition_latency = 300 * 1000;
Reviewed-by: Mikko Perttunen
On 07.02.2018 12:21, Marc Zyngier wrote:
Hi Mikko,
On 06/02/18 07:22, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UA
On 10.02.2018 00:54, Rob Herring wrote:
On Tue, Feb 06, 2018 at 09:22:36AM +0200, Mikko Perttunen wrote:
...
index ..dcc6eea52684
--- /dev/null
+++ b/include/dt-bindings/clock/tegra194-clock.h
@@ -0,0 +1,664 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
Notes:
v3:
- added hypervisor-related apertu
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
1 file
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
On 02/10/2018 12:49 AM, Rob Herring wrote:
On Tue, Feb 06, 2018 at 09:22:34AM +0200, Mikko Perttunen wrote:
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- add
On 16.02.2018 14:33, Philippe Ombredanne wrote:
Mikko,
On Thu, Feb 15, 2018 at 3:52 PM, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
Notes:
v4:
- fixed copyright headers ac
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
1 file
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
FWIW, we had this problem some years ago with the Tegra CPU clock - then
it was determined that a simpler solution was to have the determine_rate
callback support unsigned long rates - so clock drivers that need to
return rates higher than 2^31 can instead implement the determine_rate
callback.
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a
red in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
1 file changed, 16 insertions
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 142 +++---
include/soc/tegra
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi
of_find_node_by_name() drops a reference to its first argument.
Fixes: 3568df3d31d6 ("soc: tegra: Add thermal reset (thermtrip) support to PMC")
Cc: stable # 4.0
Cc: Mikko Perttunen
Signed-off-by: Johan Hovold
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Enable Tegra186 CPU frequency scaling support by default.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6356c6da34ea..42711031a72d 100644
--- a/arch/arm64
Enable Tegra BPMP thermal sensor support by default, built as a module.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 42711031a72d..d0f05da8baf9 100644
--- a
On 07.11.2017 23:23, Dmitry Osipenko wrote:
On 07.11.2017 15:28, Mikko Perttunen wrote:
On 05.11.2017 18:46, Dmitry Osipenko wrote:
On 05.11.2017 14:01, Mikko Perttunen wrote:
...
+static int mlock_id_for_class(unsigned int class)
+{
+#if HOST1X_HW >= 6
+switch (class)
+{
+c
The upstream kernel currently has no core rail suspend support (LP0/SC7)
on Tegras - in general the downstream kernel (used e.g. in L4T) is the
reference that has the most functionality on Tegra.
IIRC the MMC subsystem and Tegra MMC driver between upstream and
downstream are currently quite di
tested on TX1 and TX2 and should be applied on the
previously posted Tegra186 support series.
Cheers,
Mikko
Mikko Perttunen (6):
gpu: host1x: Enable Tegra186 syncpoint protection
gpu: host1x: Enable gather filter
gpu: host1x: Improve debug disassembly formatting
gpu: host1x: Disassemble more
Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values
to user pointers instead of writing out the cast manually.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu
This function actually doesn't sleep in the version that was merged.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/channel.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/channel.c
index db9b91d1384c..2fb93c2
-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
---
drivers/gpu/host1x/hw/channel_hw.c | 22 ++
drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12
drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12
3 files changed, 46 insertions(+)
diff
The disassembler for debug dumps was missing some newer host1x opcodes.
Add disassembly support for these.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/debug_hw.c | 57 ---
drivers/gpu/host1x/hw/debug_hw_1x01.c | 3 +-
drivers/gpu/host1x/hw
since that would require extra work and is unnecessary with
the current channel allocation model.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- Changed from set_protection(bool) to enable_protection
- Added some comments
- Added missing check for hv_regs being NULL in
y newlines
and by fixing other small issues.
Signed-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
---
This uses pr_cont, which there are currently talks of being replaced
with something better. I kept using it here for now until there is
some conclusion of what&
this commit.
Signed-off-by: Mikko Perttunen
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
---
drivers/gpu/host1x/Makefile| 3 +-
drivers/gpu/host1x/dev.c | 60 +++-
drivers/gpu/host1x/dev.h | 4 +
drivers/gpu/host1x
Add the Tegra186-specific hypervisor-related register range
properties.
Signed-off-by: Mikko Perttunen
---
v2:
- Dropped incorrect note about cells properties.
.../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 4
1 file changed, 4 insertions(+)
diff --git
a
Add the node for Host1x on the Tegra186, without any subdevices
for now.
Signed-off-by: Mikko Perttunen
---
v2:
- Changed address-cells and size-cells to 1 and fixed the ranges
property correspondingly.
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 ++
1 file changed, 18
Add Tegra186 support for VIC - no changes are required except for new
firmware and compatibility string.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 1 +
drivers/gpu/drm/tegra/vic.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/tegra
Add #power-domain-cells for the BPMP node on Tegra186 so that the power
domain provider may be used.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts
Add a node for the Video Image Compositor on the Tegra186.
Signed-off-by: Mikko Perttunen
---
v2:
- Fixed reg property in accordance with changed parent cells.
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia
.
The series has been tested on the Jetson TX1 (T210) and TX2 (T186)
using the host1x_test test suite available at
http://github.com/cyndis/host1x_test
The series itself is available at
http://github.com/cyndis/linux, branch host1x-t186-1
Cheers,
Mikko
Mikko Perttunen (6):
arm64: tegra: Add
On 05.09.2017 14:10, Daniel Vetter wrote:
Since this is new hw support, is there also open source userspace using
all this?
The VIC HW in Tegra186 is backwards compatible with the one in Tegra210,
which has open userspace (https://github.com/cyndis/vaapi-tegra-driver),
so that userspace shou
since that would require extra work and is unnecessary with
the current channel allocation model.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/dev.h | 16
drivers/gpu/host1x/hw/channel_hw.c | 3 +++
drivers/gpu/host1x/hw/syncpt_hw.c | 26
to the TegraDRM submit path.
Everything was tested on TX1 and TX2 and should be applied on the
previously posted Tegra186 support series.
Cheers,
Mikko
*** BLURB HERE ***
Mikko Perttunen (4):
gpu: host1x: Enable Tegra186 syncpoint protection
gpu: host1x: Enable gather filter
gpu: host1x
Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values
to user pointers instead of writing out the cast manually.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/tegra
-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/channel_hw.c | 22 ++
drivers/gpu/host1x/hw/hw_host1x04_channel.h | 12
drivers/gpu/host1x/hw/hw_host1x05_channel.h | 12
3 files changed, 46 insertions(+)
diff --git a/drivers/gpu/host1x/hw
y newlines
and by fixing other small issues.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/debug.c| 14 ++-
drivers/gpu/host1x/debug.h| 14 ---
drivers/gpu/host1x/hw/debug_hw.c | 46 ++-
drivers/gpu/host1x/hw/debug
On 08/19/2017 01:05 AM, Dmitry Osipenko wrote:
On 18.08.2017 19:15, Mikko Perttunen wrote:
Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values
to user pointers instead of writing out the cast manually.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 9
On 08/19/2017 01:36 AM, Dmitry Osipenko wrote:
On 18.08.2017 19:15, Mikko Perttunen wrote:
Since Tegra186 the Host1x hardware allows syncpoints to be assigned to
specific channels, preventing any other channels from incrementing
them.
Enable this feature where available and assign syncpoints
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