On 05/13/2018 05:16 PM, Andy Shevchenko wrote:
On Tue, May 8, 2018 at 2:44 PM, Mikko Perttunen <mperttu...@nvidia.com> wrote:
The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
multiplexing multiple "virtual UARTs" into a single hardware serial
port. The TC
On 05/13/2018 06:36 PM, Jassi Brar wrote:
On Tue, May 8, 2018 at 5:14 PM, Mikko Perttunen <mperttu...@nvidia.com> wrote:
+config SERIAL_TEGRA_TCU
+ tristate "NVIDIA Tegra Combined UART"
+ depends on ARCH_TEGRA && MAILBOX
+ select
The HSP driver is currently in many places written with the assumption
of only supporting doorbells. Prepare for the addition of shared
mailbox support by removing these assumptions and cleaning up the code.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/mailbox/tegra
The Tegra Combined UART is the proper primary serial port on P2888,
so use it.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194
Tegra HSP blocks that are already controlled by the Tegra
HSP mailbox driver.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/tty/serial/Kconfig | 9 ++
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/tegra-tcu.c | 302
Non-doorbell interrupts are routed through "shared interrupts". These
interrupts can be mapped to various internal interrupt lines. Add
interrupt properties for shared interrupts to the tegra186-hsp device
tree bindings.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
--
but is compatible to tegra186-hsp.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 +---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/
.
The initial use for the mailboxes is the Tegra Combined UART. For this
purpose, we use interrupts to receive data, and spinning to wait for
the transmit mailbox to be emptied to minimize unnecessary overhead.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/mailbox/tegra-hsp.c
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has been sent. The new option is used with the Tegra
Combined UART driver to minimize unnecessary overhead when transmitting
data.
Signed-off-by: Mikko
Add bindings for the Tegra Combined UART device used to talk to the
UART console on Tegra194 systems.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
.../bindings/serial/nvidia,tegra194-tcu.txt| 35 ++
1 file changed, 35 insertions(+)
create mode
patches 4 and 5 add support for the "shared mailbox" primitive
to the Tegra HSP driver.
* patch 6 adds the TCU driver itself
* patches 7 and 8 do the necessary device tree changes.
The series has been tested on the Tegra194 P2972 board.
Thanks,
Mikko
Mikko Perttunen (8):
dt-bind
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has been sent. The new option is used with the Tegra
Combined UART driver to minimize unnecessary overhead when transmitting
data.
Signed-off-by: Mikko
HSP interrupts can be routed through exposed "shared interrupts". These
interrupts can be mapped to various internal interrupt lines. Add
interrupt properties for shared interrupts to the tegra186-hsp device
tree bindings.
Signed-off-by: Mikko Perttunen
Acked-by: Jon Hunter
Review
but is compatible to tegra186-hsp.
Signed-off-by: Mikko Perttunen
Acked-by: Jon Hunter
---
Notes:
v3:
- Added Jon's Acked-by.
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 +---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia
The Tegra Combined UART is the proper primary serial port on P2888,
so use it.
Signed-off-by: Mikko Perttunen
Acked-by: Jon Hunter
---
Notes:
v2:
- Added Jon's Acked-by.
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The HSP driver is currently in many places written with the assumption
of only supporting doorbells. Prepare for the addition of shared
mailbox support by removing these assumptions and cleaning up the code.
Signed-off-by: Mikko Perttunen
Reviewed-by: Jon Hunter
---
Notes:
v2:
- Moved
.
The initial use for the mailboxes is the Tegra Combined UART. For this
purpose, we use interrupts to receive data, and spinning to wait for
the transmit mailbox to be emptied to minimize unnecessary overhead.
Signed-off-by: Mikko Perttunen
Reviewed-by: Jon Hunter
---
Notes:
v3:
- Added define
Tegra HSP blocks that are already controlled by the Tegra
HSP mailbox driver.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- Removed (void) casts for unused variables.
- Changed the uart_set_options() call to be on one line, even if its
over 80 characters.
- Added defines
Add bindings for the Tegra Combined UART device used to talk to the
UART console on Tegra194 systems.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
Acked-by: Jon Hunter
---
Notes:
v2:
- Added Rob's Reviewed-by.
v3:
- Added Jon's Acked-by.
.../bindings/serial
ption to the mailbox
framework.
* patches 4 and 5 add support for the "shared mailbox" primitive
to the Tegra HSP driver.
* patch 6 adds the TCU driver itself
* patches 7 and 8 do the necessary device tree changes.
The series has been tested on the Tegra194 P2972 board.
Mikko Perttunen (8):
On 02.07.2018 16:18, Thierry Reding wrote:
On Mon, Jul 02, 2018 at 02:40:31PM +0300, Mikko Perttunen wrote:
The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
multiplexing multiple "virtual UARTs" into a single hardware serial
port. The TCU is the primary s
On 02.07.2018 16:47, Thierry Reding wrote:
On Mon, Jul 02, 2018 at 04:30:07PM +0300, Mikko Perttunen wrote:
On 02.07.2018 16:18, Thierry Reding wrote:
On Mon, Jul 02, 2018 at 02:40:31PM +0300, Mikko Perttunen wrote:
The Tegra Combined UART (TCU) is a mailbox-based mechanism that allows
FWIW, we had this problem some years ago with the Tegra CPU clock - then
it was determined that a simpler solution was to have the determine_rate
callback support unsigned long rates - so clock drivers that need to
return rates higher than 2^31 can instead implement the determine_rate
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/te
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/soc/tegra/pmc.c | 1 +
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
e required in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (6):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files chang
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/firmware/tegra/bpmp.c
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvid
On 01/16/2018 12:06 AM, Lyude Paul wrote:
It's here! After a lot of investigation, rewrites, and traces, I present
the patch series to implement all known levels of clockgating for
Kepler1 and Kepler2 GPUs.
Starting with Fermi GPUs (this is probably present on earlier GPUs as
well, but with a
On 11.01.2018 23:56, Rob Herring wrote:
On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to bo
Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>
On 01/27/2018 04:28 PM, Julia Lawall wrote:
Check the variable that was most recently initialized.
The semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
//
@@
expression x, y, f, g, e, m;
statement S1
On 07.02.2018 12:21, Marc Zyngier wrote:
Hi Mikko,
On 06/02/18 07:22, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UA
On 10.02.2018 00:54, Rob Herring wrote:
On Tue, Feb 06, 2018 at 09:22:36AM +0200, Mikko Perttunen wrote:
...
index ..dcc6eea52684
--- /dev/null
+++ b/include/dt-bindings/clock/tegra194-clock.h
@@ -0,0 +1,664 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018
On 02/10/2018 12:49 AM, Rob Herring wrote:
On Tue, Feb 06, 2018 at 09:22:34AM +0200, Mikko Perttunen wrote:
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/firmware/tegra/bpmp.c
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186
e required in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/te
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/soc/tegra/pmc.c | 1 +
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files chang
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvid
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
Notes:
v3:
-
e required in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/te
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/soc/tegra/pmc.c | 1 +
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files chang
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/firmware/tegra/bpmp.c
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Notes:
v2:
- add patch
Documentation/devicetree/
AIUI, the PWM framework already exposes a sysfs node with period
information. We should just use that instead of adding a new driver for
this.
In any case, we cannot add something like this to device tree since it's
not a hardware device.
Mikko
On 21.02.2018 08:58, Rajkumar Rampelli wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
Notes:
v4:
-
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/soc/tegra/pmc.c | 1 +
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Notes:
v2:
- add patch
Documentation/devicetree/
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files chang
channel are supported, and channels
are not required to be placed contiguously in memory. The same
configuration also works on T186 so we end up with less code.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
drivers/firmware/tegra/bpmp.c
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com>
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/te
e required in the BPMP driver to support the
new channel layout in Tegra194.
The series has been tested on Tegra186 (Jetson TX2) and Tegra194
(P2972).
Cheers,
Mikko
Mikko Perttunen (7):
firmware: tegra: Simplify channel management
soc/tegra: Add Tegra194 SoC configuration option
soc/tegra: pmc: Ad
On 16.02.2018 14:33, Philippe Ombredanne wrote:
Mikko,
On Thu, Feb 15, 2018 at 3:52 PM, Mikko Perttunen <mperttu...@nvidia.com> wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devic
On 21.02.2018 16:46, Guenter Roeck wrote:
On 02/20/2018 11:15 PM, Mikko Perttunen wrote:
AIUI, the PWM framework already exposes a sysfs node with period
information. We should just use that instead of adding a new driver
for this.
I am kind of lost. Please explain.
Are you saying that we
* 1000;
Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>
but is compatible to tegra186-hsp.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 +---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index
Add bindings for the Tegra Combined UART device used to talk to the
UART console on Tegra194 systems.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Notes:
v2:
- Added Rob's Reviewed-by.
.../bindings/serial/nvidia,tegra194-tcu.txt| 35 ++
1
.
The initial use for the mailboxes is the Tegra Combined UART. For this
purpose, we use interrupts to receive data, and spinning to wait for
the transmit mailbox to be emptied to minimize unnecessary overhead.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- Added defines for some register fields
Tegra HSP blocks that are already controlled by the Tegra
HSP mailbox driver.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- Removed (void) casts for unused variables.
- Changed the uart_set_options() call to be on one line, even if its
over 80 characters.
- Added defines
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has been sent. The new option is used with the Tegra
Combined UART driver to minimize unnecessary overhead when transmitting
data.
Signed-off-by: Mikko
On 22.05.2018 18:36, Jon Hunter wrote:
On 08/05/18 12:43, Mikko Perttunen wrote:
The HSP driver is currently in many places written with the assumption
of only supporting doorbells. Prepare for the addition of shared
mailbox support by removing these assumptions and cleaning up the code
On 22.05.2018 18:15, Jon Hunter wrote:
On 08/05/18 12:43, Mikko Perttunen wrote:
Non-doorbell interrupts are routed through "shared interrupts". These
interrupts can be mapped to various internal interrupt lines. Add
interrupt properties for shared interrupts to the tegra186-hsp d
One potential issue is with host1x clients where userspace processes can
submit jobs with invalid memory accesses (addresses not mapped to
IOMMU). If when such a failure happens, we disable the DMA for the whole
host1x client, unrelated userspace processes may see failures even
though there is
On 08/03/2018 03:54 PM, Jassi Brar wrote:
On Mon, Jul 2, 2018 at 5:10 PM, Mikko Perttunen wrote:
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has been sent. The new option is used with the Tegra
ic. I assume this gets printed through the earlycon
as it's printing out correctly.
Thanks,
Mikko
On 08.08.2018 17:46, Mikko Perttunen wrote:
On 08/08/2018 05:39 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 8:04 PM, Mikko Perttunen wrote:
On 08/08/2018 05:10 PM, Jassi Brar wrote:
On Wed,
On 08/08/2018 05:10 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 5:08 PM, Mikko Perttunen wrote:
On 04.08.2018 13:45, Mikko Perttunen wrote:
On 08/03/2018 03:54 PM, Jassi Brar wrote:
On Mon, Jul 2, 2018 at 5:10 PM, Mikko Perttunen
wrote:
Add a new TXDONE option, TXDONE_BY_BLOCK
On 08/08/2018 05:39 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 8:04 PM, Mikko Perttunen wrote:
On 08/08/2018 05:10 PM, Jassi Brar wrote:
On Wed, Aug 8, 2018 at 5:08 PM, Mikko Perttunen wrote:
On 04.08.2018 13:45, Mikko Perttunen wrote:
On 08/03/2018 03:54 PM, Jassi Brar wrote
On 04.08.2018 13:45, Mikko Perttunen wrote:
On 08/03/2018 03:54 PM, Jassi Brar wrote:
On Mon, Jul 2, 2018 at 5:10 PM, Mikko Perttunen
wrote:
Add a new TXDONE option, TXDONE_BY_BLOCK. With this option, the
send_data function of the mailbox driver is expected to block until
the message has
On 20.07.2018 15:45, Aapo Vienamo wrote:
Parse the pinctrl states from the device tree and implement pad voltage
state reconfiguration in the mmc start_signal_voltage_switch() callback.
This is done in the mmc callback because the order of pad
reconfiguration and sdhci voltage switch depend on
I would maybe say "dt-bindings: mmc: tegra: Add pad voltage control
properties" or similar for the subject - the current kind of looks like
the SDHCI controller is a pinctrl device :)
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Document the pinctrl bin
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra210.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27 +++
1 file changed, 27
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Add pad voltage configuration nodes for sdmmc pads with configurable
voltages on Tegra186.
Signed-off-by: Aapo Vienamo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40
1 file changed
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
Set regulator-min-microvolt property of ldo2 to 1.8 V in
tegra210-p2180.dtsi. ldo2 is used by the sdmmc1 SDHCI controller and its
voltage needs to be adjusted down to 1.8 V to support faster signaling
modes. It appears
Technically this shouldn't be required since VDD_1V8 is always on
anyway, but I think it's nicer to specify regulators anyway, so +1!
Reviewed-by: Mikko Perttunen
On 20.07.2018 15:45, Aapo Vienamo wrote:
On p2180 sdmmc4 is powered from a fixed 1.8 V regulator.
Signed-off-by: Aapo Vienamo
Looks like patch 6 will probably cause tegra-sdhci to start advertising
faster modes (see " if (!IS_ERR(host->mmc->supply.vqmmc))" in
sdhci-tegra.c). With that patch and this, will the SDHCI core start to
try putting us into these higher modes? Clearly that won't work yet
before the upcoming
On 24.07.2018 17:29, Aapo Vienamo wrote:
Implement polling with 10 ms timeout for automatic pad drive strength
calibration.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git
On 24.07.2018 17:34, Aapo Vienamo wrote:
Configure the voltage reference used by the automatic pad drive strength
calibration procedure. The value is a magic number from the TRM.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 14 --
1 file changed, 12
Reviewed-by: Mikko Perttunen
On 24.07.2018 17:34, Aapo Vienamo wrote:
Automatic pad drive strength calibration is performed on a separate pad
identical to the ones used for driving the actual bus. Power on the
calibration pad during the calibration procedure and power it off
afterwards to save
On 24.07.2018 17:34, Aapo Vienamo wrote:
Disable the card clock during automatic pad drive strength calibration
and re-enable it aftewards.
s/aftewards/afterwards/.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 27 +++
1 file changed, 27
On 24.07.2018 17:34, Aapo Vienamo wrote:
Add bindings documentation for pad pull up and pull down offset values to be
programmed before executing automatic pad drive strength calibration.
Signed-off-by: Aapo Vienamo
---
.../bindings/mmc/nvidia,tegra20-sdhci.txt | 32
On 24.07.2018 17:34, Aapo Vienamo wrote:
Parse the pad drive strength calibration offsets from the device tree.
Program the calibration offsets in accordance with the current signaling
mode.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 147
On 24.07.2018 17:34, Aapo Vienamo wrote:
Run the automatic pad calibration after voltage switching if
tegra_host->pad_calib_required is set.
Signed-off-by: Aapo Vienamo
---
drivers/mmc/host/sdhci-tegra.c | 5 +
1 file changed, 5 insertions(+)
diff --git
Thanks!
Reviewed-by: Mikko Perttunen
On 17.07.2018 13:49, Corentin Labbe wrote:
Since ahci_platform_put_resources() use target_pwrs after "devm_" freed
it, we cannot use devm_kcalloc for allocating target_pwrs.
This reverts commit bd0038b1b4f499d814d8f33a55b1df5ea6cf3b85.
Reported
free_const call to __clk_put and add comments to both
functions to remind that the logic in them should be kept in sync.
Fixes: 253160a8ad06 ("clk: core: Copy connection id")
Signed-off-by: Mikko Perttunen
---
drivers/clk/clk.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers
Hi,
I'm seeing the following spew during boot with Tegra210 with the patch
"regulator: core: Link consumer with regulator driver", recently applied
to linux-next:
[1.196664] [ cut here ]
[1.201480] kobject: '(null)' ((ptrval)): is not initialized,
yet
This nas been NAK'd before as harder to read than the current way.
Thanks,
Mikko
On 01/23/2018 10:29 PM, Christopher Díaz Riveros wrote:
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
This issue was detected by using the Coccinelle software.
Signed-off-by: Christopher Díaz Riveros
On 07.03.2018 16:20, Guenter Roeck wrote:
On 03/07/2018 01:47 AM, Rajkumar Rampelli wrote:
On Wednesday 28 February 2018 07:59 PM, Guenter Roeck wrote:
On 02/27/2018 11:03 PM, Mikko Perttunen wrote:
On 02/28/2018 08:12 AM, Rajkumar Rampelli wrote:
On Wednesday 28 February 2018 11:28 AM
Rob,
this binding is for a specific IP block (for measuring/aggregating input
pulses) on the Tegra186 SoC, so I don't think it fits into any generic
binding.
Thanks,
Mikko
On 03/27/2018 05:52 PM, Rob Herring wrote:
On Wed, Mar 21, 2018 at 10:10:38AM +0530, Rajkumar Rampelli wrote:
Supply
On 04/09/2018 04:21 PM, Rob Herring wrote:
On Mon, Apr 9, 2018 at 12:38 AM, Mikko Perttunen <cyn...@kapsi.fi> wrote:
Rob,
Please don't top post to lists.
this binding is for a specific IP block (for measuring/aggregating input
pulses) on the Tegra186 SoC, so I don't think it fits in
Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>
On 23.04.2018 12:54, Dmitry Osipenko wrote:
If IOVA allocation or IOMMU mapping fails, dma_free_wc() is invoked with
size=0 because of a typo, that triggers "kernel BUG at mm/vmalloc.c:124!".
Signed-off-by: Dmitry Osipenko &
On 02/28/2018 08:12 AM, Rajkumar Rampelli wrote:
On Wednesday 28 February 2018 11:28 AM, Guenter Roeck wrote:
On 02/27/2018 09:38 PM, Rajkumar Rampelli wrote:
On Wednesday 21 February 2018 08:20 PM, Guenter Roeck wrote:
On 02/20/2018 10:58 PM, Rajkumar Rampelli wrote:
Add generic PWM based
501 - 600 of 1248 matches
Mail list logo
