Hi Lad,
On 2020-05-13 12:16:00 +0100, Lad, Prabhakar wrote:
> Hi Niklas,
>
> Thank you for the review.
>
> On Tue, May 12, 2020 at 11:26 PM Niklas wrote:
> >
> > Hi Lad,
> >
> > Thanks for your work.
> >
> > On 2020-04-15 11:19:06 +0100,
rmat.height;
> + vin->compose = vin->crop;
> +
> v4l2_rect_map_inside(&vin->crop, &src_rect);
> v4l2_rect_map_inside(&vin->compose, &fmt_rect);
> vin->src_rect = src_rect;
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
Hi Lad,
On 2020-07-25 23:23:13 +0100, Lad, Prabhakar wrote:
> Hi Niklas,
>
> On Sat, Jul 25, 2020 at 9:11 AM Niklas wrote:
> >
> > Hi Lad,
> >
> > On 2020-07-24 22:11:31 +0100, Lad, Prabhakar wrote:
> > > Hi Niklas,
> > >
> > > Thank
media bus configuration flags
> * @source_pad: source pad of remote subdevice
> * @sink_pad:sink pad of remote subdevice
> + * @ycbcr_8b_g: select data pins for YCbCr422-8bit
> *
> */
> struct rvin_parallel_entity {
> @@ -106,6 +110,7 @@ struct rvin_parallel_entity {
>
> unsigned int source_pad;
> unsigned int sink_pad;
> + bool ycbcr_8b_g;
> };
>
> /**
> --
> 2.17.1
>
--
Regards,
Niklas Söderlund
Hi Lad, Hans,
On 2020-08-03 19:11:32 +0100, Lad, Prabhakar wrote:
> Hi Hans,
>
> On Sat, Aug 1, 2020 at 10:04 AM Niklas wrote:
> >
> > Hi Lad,
> >
> > Thanks for your work.
> >
> > On 2020-07-31 10:29:05 +0100, Lad Prabhakar wrote:
> > >
Hi Lad,
On 2020-08-03 20:17:54 +0100, Lad, Prabhakar wrote:
> Hi Niklas,
>
> Thank you for the review.
>
> On Mon, Aug 3, 2020 at 7:06 PM Niklas wrote:
> >
> > Hi Lad,
> >
> > Thanks for your work.
> >
> > On 2020-08-03 17:02:53 +0100,
Hi Lad,
On 2020-08-04 09:04:25 +0100, Lad, Prabhakar wrote:
> Hi Niklas,
>
> On Mon, Aug 3, 2020 at 8:28 PM Niklas wrote:
> >
> > Hi Lad,
> >
> > On 2020-08-03 20:17:54 +0100, Lad, Prabhakar wrote:
> > > Hi Niklas,
> > >
> > > Thank yo
d, Aug 19, 2020 at 3:08 PM Hans Verkuil wrote:
> > > > On 03/08/2020 21:21, Niklas wrote:
> > > > > On 2020-08-03 19:11:32 +0100, Lad, Prabhakar wrote:
> > > > >> On Sat, Aug 1, 2020 at 10:04 AM Niklas wrote:
> > > > >>> On 2020-07-31 10:29:
Hi Lad,
On 2020-07-24 22:11:31 +0100, Lad, Prabhakar wrote:
> Hi Niklas,
>
> Thank you for the review.
>
> On Fri, Jul 24, 2020 at 8:37 PM Niklas wrote:
> >
> > Hi Lad,
> >
> > Thanks for your patch.
> >
> > On 2020-07-24 15:58:51 +0100, La
t; +description:
> + If present this property specifies to selects VIN_G[7:0]
> as data pins for
> + YCbCr422 8-bit data.
> +default: false
> +
> required:
>- remote-endpoint
>
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
Hi Lad,
Thanks for your work.
On 2020-07-16 18:18:32 +0100, Lad Prabhakar wrote:
> Document support for the VIN module in the Renesas RZ/G2H (R8A774E1) SoC.
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Marian-Cristian Rotariu
>
Reviewed-by: Niklas Söderlund
> --
Hi Lad,
Thanks for your patch.
On 2020-07-16 18:18:31 +0100, Lad Prabhakar wrote:
> Add the compatible string for RZ/G2H (R8A774E1) to the list of supported
> SoCs.
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Marian-Cristian Rotariu
>
Reviewed-by
Hi Lad,
Thanks for your work.
On 2020-07-16 18:18:33 +0100, Lad Prabhakar wrote:
> Add the MIPI CSI-2 driver support for RZ/G2H (R8A774E1) SoC.
> The CSI-2 module of RZ/G2H is similar to R-Car H3.
>
> Signed-off-by: Lad Prabhakar
> Reviewed-by: Marian-Cristian Rotariu
>
R
: Lad Prabhakar
> Reviewed-by: Marian-Cristian Rotariu
>
I do not have access to the datasheet so I can't verify the routing
table so I trust it is correct.
Reviewed-by: Niklas Söderlund
> ---
> drivers/media/platform/rcar-vin/rcar-core.c | 40 +
> 1 file
Hi Lad,
Thanks for your work.
On 2020-07-15 12:08:52 +0100, Lad Prabhakar wrote:
> Document RZ/G2H (R8A774E1) SoC bindings.
>
> Signed-off-by: Lad Prabhakar
Reviewed-by: Niklas Söderlund
> ---
> Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml | 1 +
>
Hi Lad,
Thanks for your work.
On 2020-07-15 12:08:53 +0100, Lad Prabhakar wrote:
> From: Marian-Cristian Rotariu
>
> Add r8a774e1 specific compatible string.
>
> Signed-off-by: Marian-Cristian Rotariu
>
> Signed-off-by: Lad Prabhakar
Reviewed-by: Niklas Söderlu
return -EPIPE;
> }
>
> + vin->mbus_code = fmt.format.code;
> +
> switch (fmt.format.field) {
> case V4L2_FIELD_TOP:
> case V4L2_FIELD_BOTTOM:
> --
> 2.20.1
>
--
Regards,
Niklas Söderlund
; Signed-off-by: Lad Prabhakar
Reviewed-by: Niklas Söderlund
> ---
> drivers/media/platform/rcar-vin/rcar-dma.c | 15 ++-
> drivers/media/platform/rcar-vin/rcar-v4l2.c | 4
> 2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/
David wrote:
> Honestly, I think it *is* wrong to sell someone a physical product and then
> not tell them how to make it work. If you're not actually selling them the
> physical product but selling them a way to get a particular thing done, then
> don't represent that you're selling them physical
Hi,
Pavel wrote:
> Something is very wrong with German legal system, I'm afraid.
In this case you are right. Our legal system is often very strange.
__
"Ein Herz für Kinder" - Ihre Spende hilft! Aktion: www.deutschlandse
Hi,
while compiling the DC930 SCSI driver, i got this message:
drivers/built-in.o: In function `dc390_module_init':
tmscsim.c:(.init.text+0x124c4): undefined reference to `pci_module_init'
make: *** [.tmp_vmlinux1] Fehler 1
so i replaced "pci_module_init" with "pci_register_device"
and it works
Hello,
My network driver does not crash like some have reported.
I did an internet search for this and found that it is due to the
firmware in kernel not being set.
Isn't there a way for loading of the tg3 firmware without it needing to
be builtin to the kernel?
Please CC.
Thanks, David
-
From: Niklas Cassel
artpec6_add_pcie_port is called from artpec6_pcie_probe.
artpec6_pcie_probe does not have the __init section marker.
It is wrong to have the marker on artpec6_add_pcie_port
when the marker is not on artpec6_pcie_probe.
Signed-off-by: Niklas Cassel
---
drivers/pci/host/pcie
From: Niklas Cassel
- Increase config size. When using a PCIe switch,
the previous config size only had room for one device.
- Add bus range. Inherited optional property.
- Map downstream I/O to PCI address 0. We can map it to any
address, but let's be consistent with other dr
pointer from the first descriptor to the last
descriptor, a skb will get freed only when the IP has cleared the
own bit of all the descriptors that are using that skb.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 20
1 file changed, 16
On 10/13/2017 06:42 PM, David Laight wrote:
> From: Behalf Of Niklas Cassel
>> Sent: 13 October 2017 17:09
>> Since it is a PCIe endpoint device, rather than the CPU, that is supposed
>> to write to this location, the proper way to get the address to this this
>> locati
On 10/13/2017 06:43 PM, Jingoo Han wrote:
> On Friday, October 13, 2017 12:09 PM, Niklas Cassel wrote:
>>
>> Since it is a PCIe endpoint device, rather than the CPU, that is supposed
>> to write to this location, the proper way to get the address to this this
>> locati
On 10/13/2017 06:47 PM, Jingoo Han wrote:
> On Friday, October 13, 2017 12:09 PM, Niklas Cassel wrote:
>>
>> Since it is a PCIe endpoint device, rather than the CPU, that is supposed
>> to write to this location, the proper way to get the address to this this
>> locati
On 10/13/2017 06:09 PM, Niklas Cassel wrote:
(snip)
Hello Kishon
I just wanted to say that the function
artpec6_pcie_calc_cpu_fixup_mask should work on dra7xx
as well. (I had dra7xx in mind when I wrote it.)
However, I did not want to change pci-dra7xx.c to
also use this function, since your
On 10/31/2017 07:01 AM, Kishon Vijay Abraham I wrote:
> Hi Niklas,
>
> On Monday 30 October 2017 06:12 PM, Niklas Cassel wrote:
>> Certain SoCs need to map the MSI address in raise_irq.
>> To map an address, you first need to call pci_epc_mem_alloc_addr,
>> however, p
efine PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit
devices */
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit
devices */
Regards,
Niklas
DEVICE_TYPE_EP);
>> @@ -700,6 +719,7 @@ static int __init dra7xx_pcie_probe(struct
>> platform_device *pdev)
>> if (ret < 0)
>> goto err_gpio;
>> break;
>> +#endif
Actually, these ifdefs has to stay, otherwise we get build warnings, since we
are calling functions that aren't defined (dra7xx_pcie_ep_unaligned_memaccess,
dra7xx_add_pcie_ep, dra7xx_add_pcie_port).
We could add dummy implementations for these inside an #else block following
the ifdef blocks. However, I think that adding dummy implementations in the
#else block is uglier and more verbose than keeping the ifdefs around the
two cases.
Regards,
Niklas
cie_port).
> We could add dummy implementations for these inside an #else block following
> the ifdef blocks. However, I think that adding dummy implementations in the
> #else block is uglier and more verbose than keeping the ifdefs around the
> two cases.
>
..however, if you prefer dummy implementations inside the #else blocks,
I will of course do that.
Regards,
Niklas
Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control
register, thus overwriting the PCI_MSI_FLAGS_64BIT bit.
By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI
on systems where the RC has set a 64 bit MSI address.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers
ent should definitely be in dra7xx_add_pcie_port().
This is also needed to be able to compile host/ep mode specific code
independently.
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
V3:
* Added Kishon's ack.
drivers/pci/dwc/pci-dra7xx.c | 6 ++
1 file changed, 2 in
Certain registers that pcie-designware-ep tries to write are read-only
registers. However, these registers can become read/write if we first
enable the DBI_RO_WR_EN bit.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-designware-ep.c | 8
1 file changed, 8
This function can be used by all DWC based controllers to raise a MSI
irq. However, certain controllers, like DRA7xx, has a special
convenience register for raising MSI irqs that doesn't require you to
explicitly map the MSI address.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
dr
This is done to better match other drivers such as dra7xx and imx6,
but also to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-artpec6.c | 53 +++---
1 file changed, 29 insertions(+), 24 deletions
This way pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar().
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
V3:
* Added Kishon's ack.
drivers/pci/dwc/pci-dra7xx.c | 9 -
drivers/pci/dwc/pcie-designware-ep.c | 2 +-
drivers/pci/dwc
specific code inside a single ifdef block.
Signed-off-by: Niklas Cassel
---
V3:
* Fixed commit message.
* Moved functions in order to have just a single ifdef for host,
and a single ifdef for ep.
* Removed ifdefs around match table and match table data.
* Removed ifdefs in probe, use dummy
Signed-off-by: Niklas Cassel
---
V3:
* Removed ifdefs around match table and match table data.
* Removed ifdefs in probe, use dummy implementations instead.
drivers/pci/dwc/Kconfig| 23 --
drivers/pci/dwc/pcie-artpec6.c | 162 +++--
2 files
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V3:
* No change.
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 2 ++
1 file changed, 2
Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to
DBI read-only registers") removed the only write using these
defines, but it did not remove the defines.
Remove the defines since they are now unused.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
---
V3:
* Now when there are no ifdefs around the match table entries,
sort them by SoC.
drivers/pci/dwc/pcie-artpec6.c | 162
.
This also fixes a bug for ARTPEC-6, where the cpu to bus address
fixup mask previously was off by one (GENMASK(27, 0), rather than
GENMASK(28, 0)), which is another reason why the it is a good idea
to calculate the mask by using values from device tree.
Signed-off-by: Niklas Cassel
---
V3:
* No
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V3:
* No change.
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
b/Documentation/devicetree
The previous handling was a bit unorthodox and would have been a bit
bloated once more DWC based controllers added support for ep mode.
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
V3:
* Added Kishon's ack.
drivers/pci/dwc/Kconfig
This greatly improves readability.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-artpec6.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index
that it will work on all systems.
This is essentially the same thing as allocating a buffer in a driver,
to which the endpoint will write to. To do this, we use the DMA API.
Signed-off-by: Niklas Cassel
---
V3:
* No change.
drivers/pci/dwc/pcie-designware-host.c | 15 ---
drivers/pci
e_irq, instead we pre-allocate
a page in dw_pcie_ep_init, so this page can later be used to map/unmap
the MSI address in raise_irq.
Signed-off-by: Niklas Cassel
---
V3:
* Use ep->page_size rather than PAGE_SIZE.
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/dwc/pcie-designware.h
-dra7xx to better prepare for endpoint mode in other
DWC based PCIe drivers.
New in V3:
Fixed all review comments, for detailed changes, see the changelog
in each patch.
Niklas Cassel (17):
PCI: dwc: Use DMA-API for allocating MSI data
PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC
On 10/31/2017 10:38 PM, Niklas Cassel wrote:
>>>>
>>>> static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>>>> {
>>>> @@ -681,6 +697,7 @@ static int __init dra7xx_pcie_probe(struct
>>>> platform_device *pdev)
>&
irqs that are always enabled are:
LPI and PMT.
Looking at dwmac4_core.c, the irqs that are always enabled are:
PMT.
To be able to read the LPI irq status, we need to enable the LPI
irq also for dwmac4.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 7
s that are always enabled are:
LPI and PMT.
Looking at dwmac4_core.c, the irqs that are always enabled are:
PMT.
To be able to read the LPI irq status, we need to enable the LPI
irq also for dwmac4.
Signed-off-by: Niklas Cassel
---
Changes since v1:
Fixed two typos in the commit message.
dia: v4l: async: Fix notifier complete callback error
> handling")
> Signed-off-by: Colin Ian King
Reviewed-by: Niklas Söderlund
> ---
> drivers/media/v4l2-core/v4l2-async.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/media/v4l2-core/v4l2-async.c
>
On 11/02/2017 10:13 AM, Arnd Bergmann wrote:
> On Tue, Oct 31, 2017 at 11:39 PM, Niklas Cassel
> wrote:
>> Signed-off-by: Niklas Cassel
>
> It seems like you are missing a changelog text. Please explain what
> your work is good for
> in any patch you send.
You ar
-dra7xx to better prepare for endpoint mode in other
DWC based PCIe drivers.
New in V4:
Fixed all commit messages so that they are readable without the title.
Replaced ifdefs in pci-dra7xx and pcie-artpec6 by using the
IS_ENABLED macro. (Thanks Arnd!)
Niklas Cassel (17):
PCI: dwc: Use the DMA-API to
Remove the static keyword from dw_pcie_ep_reset_bar() so that
pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar().
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/pci-dra7xx.c | 9 -
drivers/pci/dwc/pcie-designware-ep.c | 2
Split artpec6_pcie_establish_link() into smaller functions
to better match other drivers such as dra7xx and imx6.
This is also done to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 53 +++---
1 file
Refactor the Kconfig and Makefile handling for host/ep mode, since
the previous handling was a bit unorthodox and would have been a bit
bloated once more DWC based controllers added support for ep mode.
Signed-off-by: Niklas Cassel
Acked-by: Kishon Vijay Abraham I
---
drivers/pci/dwc/Kconfig
silently dropped by the compiler,
including static functions and structures that are referenced indirectly
from there.
Suggested-by: Arnd Bergmann
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pci-dra7xx.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/dwc/pci-dra7xx.c
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/Kconfig| 23 +--
drivers/pci/dwc/pcie-artpec6.c | 152
Use BIT and GENMASK macros to improve readability.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index
Add support for the ARTPEC-7 SoC in the artpec6 driver.
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/axis
.
This also fixes a bug for ARTPEC-6, where the cpu to bus address
fixup mask previously was off by one (GENMASK(27, 0), rather than
GENMASK(28, 0)). This is another reason to calculate the mask by
using values from device tree.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pci-dra7xx.c
Add support for the ARTPEC-7 SoC in the artpec6 driver.
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 162
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions
Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to
DBI read-only registers") removed the only write using these
defines, but it did not remove the defines.
Remove the defines since they are now unused.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 3 -
to struct dw_pcie,
the pp->ops assignment should definitely be in dra7xx_add_pcie_port().
This is done so that the compiler (in a later commit) can remove more
code when enabling only one of the two supported modes (host/ep) in
the dra7xx driver.
Signed-off-by: Niklas Cassel
Acked-by: Kishon
ivers will
not use this generic function, even if they can.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 34 ++
drivers/pci/dwc/pcie-designware.h| 9 +
2 files changed, 43 insertions(+)
diff --git a/drivers/pci/dwc/pcie-desig
Certain registers that pcie-designware-ep tries to write to are read-only
registers. However, these registers can become read/write if we first
enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after
writing these registers.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie
e_irq.
Pre-allocate a page in dw_pcie_ep_init(), so that this page can later
be used to map/unmap the MSI address in raise_irq.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 10 ++
drivers/pci/dwc/pcie-designware.h| 2 ++
2 files changed, 12 insertions(+)
. To do this, we use the DMA API.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-host.c | 15 ---
drivers/pci/dwc/pcie-designware.h | 3 ++-
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-host.c
b/drivers/pci/dwc
-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 4 +++-
drivers/pci/dwc/pcie-designware.h| 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c
b/drivers/pci/dwc/pcie-designware-ep.c
index d53d5f168363..c92ab87fd660 100644
On 11/03/2017 11:23 AM, Arnd Bergmann wrote:
> On Fri, Nov 3, 2017 at 10:56 AM, Niklas Cassel wrote:
>> On 11/02/2017 10:13 AM, Arnd Bergmann wrote:
> What I meant is that you can remove the #ifdef entirely if you add
>
> if (!IS_ENABLED(CONFIG
dra7xx_pcie_shutdown should be static.
This patch introduces a new sparse warning.
On Wed, Oct 11, 2017 at 9:32 PM, Bjorn Helgaas wrote:
> On Wed, Sep 20, 2017 at 10:54:15AM +0530, Keerthy wrote:
>> Add shutdown handler to cleanly turn off clocks. This will help
>> in cases of kexec where in a n
On 10/18/2017 10:03 AM, Kishon Vijay Abraham I wrote:
> Hi Bjorn,
>
> On Tuesday 17 October 2017 05:13 AM, Bjorn Helgaas wrote:
>> On Fri, Oct 13, 2017 at 06:09:11PM +0200, Niklas Cassel wrote:
>>> Signed-off-by: Niklas Cassel
>>> ---
>>> .../devicetree
On 10/19/2017 09:59 AM, Christoph Hellwig wrote:
> On Mon, Oct 16, 2017 at 06:43:26PM -0500, Bjorn Helgaas wrote:
>> understand it. I guess the idea is to build pcie-artpec6.o if either
>> CONFIG_PCIE_ARTPEC6_HOST or CONFIG_PCIE_ARTPEC6_EP is set (or both).
>>
>> Is this really the simplest way to
in the of match table
The only function I'm hesitant about is .stop_link,
since it is in dw_pcie_ops, however, right now it
is only used in pcie-designware-ep.c
Would you prefer me to make them #ifdef PCIE_ARTPEC6_EP ?
I can do a similar patch for pci-dra7xx.
Regards,
Niklas
Previously, dw_pcie_ep_set_msi() wrote all bits in the Message Control
register, thus overwriting the PCI_MSI_FLAGS_64BIT bit.
By clearing the PCI_MSI_FLAGS_64BIT bit, we break MSI
on systems where the RC has set a 64 bit MSI address.
Signed-off-by: Niklas Cassel
---
V2:
* Clarified commit
that it will work on all systems.
This is essentially the same thing as allocating a buffer in a driver,
to which the endpoint will write to. To do this, we use the DMA API.
Signed-off-by: Niklas Cassel
---
V2:
* Sort headers.
* MSI with captial letters in error print.
* Don't chan
ent should definitely be in dra7xx_add_pcie_port().
This is also needed to be able to compile host/ep mode specific code
independently.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/pci-dra7xx.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --gi
This function can be used by all DWC based controllers to raise a MSI
irq. However, certain controllers, like DRA7xx, has a special
convenience register for raising MSI irqs that doesn't require you to
explicitly map the MSI address.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in
This is done to better match other drivers such as dra7xx and imx6,
but also to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel
---
V2:
* Changed the order of the functions to be more logical.
drivers/pci/dwc/pcie-artpec6.c | 53 +++---
1
This way you will not build and include unused code
when only building for only one mode.
Moved dra7xx_pcie_enable_wrapper_interrupts() in order
to avoid adding an extra ifdef block.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/pci-dra7xx.c | 36
e_irq, instead we pre-allocate
a page in dw_pcie_ep_init, so this page can later be used to map/unmap
the MSI address in raise_irq.
Signed-off-by: Niklas Cassel
---
V2:
* No change.
drivers/pci/dwc/pcie-designware-ep.c | 8
drivers/pci/dwc/pcie-designware.h| 2 ++
2 files changed, 10 inser
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V2:
* Split out the DT binding change to a self contained patch.
* Added Rob's ack (from V1). No chan
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
---
V2:
* DT binding change is now in a separate commit.
* Changed the order of the functions to be more logical.
drivers/pci/dwc
Signed-off-by: Niklas Cassel
---
V2:
* DT binding change is now in a separate commit.
* Removed local copy of dw_pcie_ep_reset_bar, it is now part of
pcie-designware-ep.c.
* Removed raise_msi_irq, it is now part of pcie-designware-ep.c.
* Refactored Kconfig and Makefile handling.
* Added ifdefs
.
This also fixes a bug for ARTPEC-6, where the cpu to bus address
fixup mask previously was off by one (GENMASK(27, 0), rather than
GENMASK(28, 0)), which is another reason why the it is a good idea
to calculate the mask by using values from device tree.
Signed-off-by: Niklas Cassel
---
V2
Signed-off-by: Niklas Cassel
Acked-by: Rob Herring
---
V2:
* Split out the DT binding change to a self contained patch.
* Added Rob's ack (from V1). No change to this file since V1.
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++-
1 file changed, 2 insertions(+), 1 del
Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to
DBI read-only registers") removed the only write using these
defines, but it did not remove the defines.
Remove the defines since they are now unused.
Signed-off-by: Niklas Cassel
---
V2:
* Changed commit message to inclu
This greatly improves readability.
Signed-off-by: Niklas Cassel
---
V2:
* No change.
drivers/pci/dwc/pcie-artpec6.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index
The previous handling was a bit unorthodox and would have been a bit
bloated once more DWC based controllers added support for ep mode.
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/Kconfig | 45 ++---
drivers/pci/dwc
This way pci-dra7xx.c does not need its own copy of dw_pcie_ep_reset_bar().
Signed-off-by: Niklas Cassel
---
V2:
* New patch in this series.
drivers/pci/dwc/pci-dra7xx.c | 9 -
drivers/pci/dwc/pcie-designware-ep.c | 2 +-
drivers/pci/dwc/pcie-designware.h| 5 +
3 files
Certain registers that pcie-designware-ep tries to write are read-only
registers. However, these registers can become read/write if we first
enable the DBI_RO_WR_EN bit.
Signed-off-by: Niklas Cassel
---
V2:
* No change.
drivers/pci/dwc/pcie-designware-ep.c | 8
1 file changed, 8
first letter in summary for all patches.
Moved DT binding changes to self contained patches.
Fixed all review comments, for detailed changes, see the note for in patch.
Niklas Cassel (17):
PCI: dwc: Use DMA-API for allocating MSI data
PCI: designware-ep: dw_pcie_ep_set_msi() should only set
SZ_4K;
^
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/smem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index bf4bd71ab53f..b77573eed596 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drive
be
compile tested even when building for other architectures.
Changes since v3:
-Picked up Vinod's Reviewed-by tags.
-Rebased against v4.19-rc1
Niklas Cassel (6):
soc: qcom: smem: Add missing include of sizes.h
soc: qcom: llcc-slice: Add missing include of sizes.h
soc: qcom: sm
QCOM_SMD_RPM builds perfectly fine without CONFIG_OF set.
Remove the bogus depends of OF.
Signed-off-by: Niklas Cassel
Reviewed-by: Vivek Gautam
Reviewed-by: Vinod Koul
---
drivers/soc/qcom/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/Kconfig b
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