Re: [PATCH] RISC-V: Handle R_RISCV_32 in modules

On Mon, 11 Jun 2018 00:54:00 PDT (-0700), sch...@suse.de wrote: On Jun 08 2018, Palmer Dabbelt wrote: On Thu, 07 Jun 2018 03:27:27 PDT (-0700), sch...@suse.de wrote: With CONFIG_MODVERSIONS=y the R_RISCV_32 relocation is used by the __kcrctab section. Signed-off-by: Andreas Schwab

Re: [PATCH 3/3] riscv: fix __user annotation for __copy_user()

On Mon, 11 Jun 2018 20:00:08 PDT (-0700), luc.vanoostenr...@gmail.com wrote: On Mon, Jun 11, 2018 at 12:01:37PM -0700, Palmer Dabbelt wrote: On Sat, 09 Jun 2018 14:42:12 PDT (-0700), luc.vanoostenr...@gmail.com wrote: > On Sat, Jun 09, 2018 at 01:00:08PM -0700, Palmer Dabbelt wrote: > &g

Re: [PATCH] riscv: pass machine size to sparse

On Mon, 28 May 2018 23:14:20 PDT (-0700), yamada.masah...@socionext.com wrote: 2018-05-29 15:11 GMT+09:00 Christoph Hellwig : On Mon, May 28, 2018 at 06:35:05PM +0200, Luc Van Oostenryck wrote: By default, sparse assumes a 64bit machine when compiled on x86-64 and 32bit when compiled on

Re: [PATCH] riscv/ftrace: Fix the problem modules cannot find _mcount

I've rewritten the commit message to match what this patch actually does. Assuming it's OK, I'll include it as part of the commits for this merge window. Thanks!

[PATCH] riscv/ftrace: Export _mcount when FUNCTION_GRAPH_TRACER isn't set

is to export _mcount whenever CONFIG_FUNCTION_TRACER is defined. This matches what every other architecture is doing. Signed-off-by: Alan Kao Cc: Greentime Hu Cc: Zong Li Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/mcount.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH 1/2] MAINTAINERS: Add myself as a maintainer for SiFive's drivers

to handle this. Signed-off-by: Palmer Dabbelt --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9c125f705f78..a8f906d1d1e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12764,6 +12764,14 @@ F: drivers/media/usb/siano/ F: drivers

[PATCH 2/2] MAINTAINERS: Update Albert's email, he's back at Berkeley

When I was adding a MAINTAINERS entry for SiFive's drivers I realized that Albert's email is out of date -- he's gone back to Berkeley, so his SiFive email is technically defunct. This patch updates his entry to a current email address, hosted at Berkeley. Signed-off-by: Palmer Dabbelt

RISC-V Related MAINTAINERS Changes

There have been a few developments in the last few months: Albert is back at Berkeley, and SiFive is beginning to submit drivers. This patch set reflects these changes.

Re: [PATCHv2 15/16] atomics/treewide: make unconditional inc/dec ops optional

atomic_fetch_add_unless(atomic_t *v, int a, int u) { As far as the RISC-V stuff goes: this works for me, as I always like to have less code in the arch port. Acked-by: Palmer Dabbelt Thanks!

Re: [PATCHv2 02/16] atomics/treewide: remove redundant atomic_inc_not_zero() definitions

(atomic64_t *v) { Acked-by: Palmer Dabbelt Thanks!

Re: [PATCHv2 04/16] atomics/treewide: make atomic_fetch_add_unless() optional

nline long __atomic64_add_unless(atomic64_t *v, long a, long u) Acked-by: Palmer Dabbelt Thanks!

Re: [PATCHv2 01/16] atomics/treewide: s/__atomic_add_unless/atomic_fetch_add_unless/

_t *v, int a, int u) +static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) { int c, old; c = atomic_read(v); Acked-by: Palmer Dabbelt Thanks!

Re: [PATCHv2 13/16] atomics/treewide: make test ops optional

ifndef CONFIG_GENERIC_ATOMIC64 -ATOMIC_OP(inc_and_test, inc, ==, 0, 64) -ATOMIC_OP(dec_and_test, dec, ==, 0, 64) -#endif - -#undef ATOMIC_OP - /* This is required to provide a full barrier on success. */ static __always_inline int atomic_fetch_add_unless(atomic_t *v, int a, int u) { Acked-by: Palmer Dabbelt

Re: [PATCHv2 03/16] atomics/treewide: make atomic64_inc_not_zero() optional

that return, so they need a full barrier. Acked-by: Palmer Dabbelt Thanks!

Re: [PATCHv2 11/16] atomics/riscv: define atomic64_fetch_add_unless()

atomic_add_unless() atop of this, provided it is given a preprocessor definition. No functional change is intended as a result of this patch. Signed-off-by: Mark Rutland Acked-by: Peter Zijlstra (Intel) Cc: Boqun Feng Cc: Will Deacon Cc: Palmer Dabbelt Cc: Albert Ou --- arch/riscv/include/asm

Re: [PATCH] riscv: pass machine size to sparse

On Thu, 31 May 2018 08:35:54 PDT (-0700), luc.vanoostenr...@gmail.com wrote: On Thu, May 31, 2018 at 05:09:21AM -0700, Palmer Dabbelt wrote: On Mon, 28 May 2018 23:14:20 PDT (-0700), yamada.masah...@socionext.com wrote: > 2018-05-29 15:11 GMT+09:00 Christoph Hellwig : > > On Mon, May

Re: [PATCH] riscv: add riscv-specific predefines to CHECKFLAGS

On Thu, 31 May 2018 08:42:01 PDT (-0700), luc.vanoostenr...@gmail.com wrote: RISC-V uses the macro __riscv_xlen, predefined by GCC, to make the distinction between 32 or 64 bit code. However, sparse doesn't know anything about this macro which lead to wrong warnings and failures. Fix this by

[PATCH] RISC-V: Add early printk support via the SBI console

This code lives entirely within the RISC-V arch code. I've left it within an "#ifdef CONFIG_EARLY_PRINTK" despite always having EARLY_PRINTK support on RISC-V just in case someone wants to remove it. Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/se

Re: [PATCH] MAINTAINERS: Add Daniel Lustig as a LKMM reviewer

On Fri, 22 Jun 2018 14:48:56 PDT (-0700), Daniel Lustig wrote: On 6/22/2018 2:17 PM, Palmer Dabbelt wrote: Dan runs the RISC-V memory model working group. I've been forwarding him LKMM emails that end up in my inbox, but I'm far from an expert in this stuff. He requested to be added

[PATCH 1/3] RISC-V: Don't include irq-riscv-intc.h

This file has never existed in the upstream kernel, but it's guarded by an #ifdef that's also never existed in the upstream kernel. As a part of our interrupt controller refactoring this header is no longer necessary, but this reference managed to sneak in anyway. Signed-off-by: Palmer Dabbelt

Driver for the RISC-V Interrupt Controller

The RISC-V ISA mandantes the presence of a simple, per-hart (hardware thread) interrupt controller availiable to supervisor mode. This patch set adds a driver for this interrupt controller. The patch set itself has been around in various flavors for a while, but as far as I remember it's never

[PATCH 2/3] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs

From: Palmer Dabbelt This patch adds documentation on the RISC-V local interrupt controller, which is a per-hart interrupt controller that manages all interrupts entering a RISC-V hart. This interrupt controller is present on all RISC-V systems. Signed-off-by: Palmer Dabbelt

[PATCH] MAINTAINERS: Add Daniel Lustig as a LKMM reviewer

Dan runs the RISC-V memory model working group. I've been forwarding him LKMM emails that end up in my inbox, but I'm far from an expert in this stuff. He requested to be added as a reviewer, which seem sane to me as it'll take a human out of the loop. CC: Daniel Lustig Signed-off-by: Palmer

[PATCH 3/3] irqchip: RISC-V Local Interrupt Controller Driver

From: Palmer Dabbelt This patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt controller manages software interrupts, timer interrupts, and hardware interrupts (which are routed via the platform

[PATCH 1/5] irq: Port the ARM IRQ drivers to GENERIC_IRQ_MULTI_HANDLER

that used to select MULTI_IRQ_HANDLER, but only when MULTI_IRQ_HANDLER doesn't exist. I'll then convert every architecture over from MULTI_IRQ_HANDLER to GENERIC_IRQ_MULTI_HANDLER before removing the extra MULTI_IRQ_HANDLER scaffolding. CC: Shea Levy CC: Arnd Bergmann Signed-off-by: Palmer

[PATCH 3/5] arm64: Use the new GENERIC_IRQ_MULTI_HANDLER

MULTI_IRQ_HANDLER instead. Reviewed-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt --- arch/arm64/Kconfig | 4 +--- arch/arm64/include/asm/irq.h | 2 -- arch/arm64/kernel/irq.c | 10 -- 3 files changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/arm64/Kconfig b/arch

[PATCH 5/5] irq: Remove MULTI_IRQ_HANDLER as it's now obselete

Now that every user of MULTI_IRQ_HANDLER has been convereted over to use GENERIC_IRQ_MULTI_HANDLER we can remove the references to MULTI_IRQ_HANDLER. Signed-off-by: Palmer Dabbelt --- drivers/irqchip/Kconfig | 24 kernel/irq/Kconfig | 1 - 2 files changed, 8

Re: Finish the GENERIC_IRQ_MULTI_HANDLER conversion

On Thu, Jun 21, 2018 at 11:17 AM, Palmer Dabbelt wrote: > A while ago I sent a patch set that adds a GENERIC_IRQ_MULTI_HANDLER, > which is an exact copy of the existing IRQ_MULTI_HANDLER support in the > arm port, which is being used unconditionally by arm64 and

[PATCH 2/5] arm: Convert to GENERIC_IRQ_MULTI_HANDLER

marked as __ro_after_init. Signed-off-by: Palmer Dabbelt --- arch/arm/Kconfig | 19 +++ arch/arm/include/asm/irq.h | 5 - arch/arm/include/asm/mach/arch.h | 2 +- arch/arm/kernel/entry-armv.S | 10 ++ arch/arm/kernel/irq.c| 10

[PATCH 4/5] openrisc: Use the new GENERIC_IRQ_MULTI_HANDLER

It appears that openrisc copied arm64's GENERIC_IRQ_MULTI_HANDLER code (which came from arm). I wanted to make this generic so I could use it in the RISC-V port. This patch converts the openrisc code to use the generic version. Acked-by: Stafford Horne Signed-off-by: Palmer Dabbelt --- arch

Re: [PATCH] MAINTAINERS: Add Daniel Lustig as a LKMM reviewer

> Acked-by: Paul E. McKenney > > > commit 9d01337e4724be4d34bfe848a7c64d14bfdb89ea > > gpg: Signature made Fri 22 Jun 2018 03:35:24 PM PDT > > gpg:using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 > > gpg: issuer "pal...@dab

Re: [PATCH 2/3] dt-bindings: Add "sifive" vendor prefix

On Tue, 01 May 2018 09:14:39 PDT (-0700), r...@kernel.org wrote: On Sat, Apr 28, 2018 at 10:37:56PM +, Wesley Terpstra wrote: Will do, thanks! Don't top post to lists. I've applied this. I assume you'll have things other than the PWM... Thanks! We have a handful of out-of-tree drivers

[PATCH 1/2] RISC-V: Remove duplicate command-line parsing logic

a ro root=/dev/vda ro" Before this patch: [0.00] Kernel command line: root=/dev/vda ro root=/dev/vda ro After this patch: [0.00] Kernel command line: root=/dev/vda ro Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com&g

[PATCH 2/2] RISC-V: Remove mem_end command line processing

This is just some cruft left over from before the port converted to device tree. The right way to handle memory regions is to specify them in the device tree, which BBL (our simplest bootloader) is already capable of doing. This patch simply removes the cruft. Signed-off-by: Palmer Dabbelt <

[GIT PULL] RISC-V changes for 4.15-rc8

. Christoph Hellwig (2): riscv: remove CONFIG_MMU ifdefs riscv: rename SR_* constants to match the spec Karsten Merker (1): RISC-V: Add a basic defconfig Palmer Dabbelt (1): RISC-V: Make __NR_riscv_flush_icache

Re: [patches] [RFC] RISC-V: Don't set CLONE_BACKWARDS

On Tue, 09 Jan 2018 00:11:45 PST (-0800), h...@lst.de wrote: On Mon, Jan 08, 2018 at 05:27:56PM -0800, Palmer Dabbelt wrote: During the glibc upstreaming it was suggested that CLONE_BACKWARDS was a deprecated ABI decision. I think we just copied it from ARM, but I don't see any reason to favor

[RFC] RISC-V: Don't set CLONE_BACKWARDS

<adhemerval.zane...@linaro.org> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- arch/riscv/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 2c6adf12713a..02076f3a2883 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kcon

[PATCH v2] RISC-V: Make __NR_riscv_flush_icache visible to userspace

From: Palmer Dabbelt <pal...@dabbelt.com> We were hoping to avoid making this visible to userspace, but it looks like we're going to have to because QEMU's user-mode emulation doesn't want to emulate a vDSO. Having vDSO-only system calls was a bit unothodox anyway, so I think in this cas

Re: [PATCH v6 02/12] drivers: base: cacheinfo: setup DT cache properties early

properties. That change helps to clarify its one remaining use (matching cacheinfo nodes that represent shared caches) which will be used by the ACPI/PPTT code in the following patches. Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Albert Ou <alb...@sifive.com> Signed-off-by: Jeremy Linton

Re: [PATCH] MIPS: use generic GCC library routines from lib/

dd notrace to lib/ucmpdi2.c? Works for me. Do you want to add a patch to this set? Since it's a dependency of this patch it seems to make a bit more sense to just keep here. Mine looks like commit dba01764391cbd6e636595f7b957357b2cf2c14a Author: Palmer Dabbelt <pal...@sifive.com> Date:

Re: [PATCH] MIPS: use generic GCC library routines from lib/

by several architectures. This commit removes several generic GCC library routines from arch/mips/lib/ in favour of similar routines from lib/. Signed-off-by: Antony Pavlov <antonynpav...@gmail.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Ralf Baechle <r...@linux-mips.org> Cc: linux-m

[PATCH 2/2] RISC-V: Move to the new asm-generic IRQ handler

an additional load to the interrupt latency, but there's a lot of tuning left to be done there on RISC-V so I think it's OK for now. Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- arch/riscv/Kconfig| 1 + arch/riscv/include/asm/Kbuild | 1 + arch/riscv/kernel/entry.S

Use arm64's scheme for registering first-level IRQ handlers on RISC-V

This patch set has been sitting around for a while, but it got a bit lost in the shuffle. In RISC-V land we currently couple do_IRQ (the C entry point for interrupt handling) to our first-level interrupt controller. While this isn't completely crazy (as the first-level interrupt controller is

[PATCH 1/2] asm-generic: Add a generic set_handle_irq

From: Palmer Dabbelt <pal...@dabbelt.com> I've copied this from arm64, but it appears to be the same code that's in arm and openrisc. I wanted to use it for RISC-V's interrupt handler as well, so despite this only being a handful of lines of code it seems worth having a generic v

Re: [PATCH v6 02/12] drivers: base: cacheinfo: setup DT cache properties early

On Wed, 17 Jan 2018 10:08:27 PST (-0800), sudeep.ho...@arm.com wrote: (Sorry, somehow I missed this email until I saw Jeremy's reply today) On 15/01/18 16:07, Palmer Dabbelt wrote: On Mon, 15 Jan 2018 04:33:38 PST (-0800), sudeep.ho...@arm.com wrote: On Fri, Jan 12, 2018 at 06:59:10PM -0600

Re: [PATCH] MIPS: use generic GCC library routines from lib/

/libgcc.h -- if it's used from anywhere else, it should be possible to use include/linux/libgcc.h instead. Assuming it still seems sane do to that I can go give the rest of the patch set another shot. I'm a bit new to this, but I think I should do something like Reviewed-by: Palmer Dabbelt

[PATCH v2 2/4] arm64: Use the new MULTI_IRQ_HANDLER

instead. Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/irq.h | 2 -- arch/arm64/kernel/irq.c | 10 -- 3 files changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig

Re: [patches] Re: [PATCH v2 4/4] RISC-V: Move to the new generic IRQ handler

On Thu, 25 Jan 2018 00:31:53 PST (-0800), sho...@gmail.com wrote: On Wed, Jan 24, 2018 at 07:07:56PM -0800, Palmer Dabbelt wrote: The old mechanism for handling IRQs on RISC-V was pretty ugly: the arch code looked at the Kconfig entry for our first-level irqchip driver and called

[PATCH] Update the RISC-V MAINTAINERS file

port is coordinated. This patch changes the RISC-V maintainers entry to reflect these new bits of infrastructure. Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS

[PATCH v2 1/4] arm: Make set_handle_irq and handle_arch_irq generic

/arm to kernel/irq/handle.c. Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- arch/arm/Kconfig | 5 - arch/arm/include/asm/irq.h | 5 - arch/arm/kernel/entry-armv.S | 6 -- arch/arm/kernel/irq.c| 10 -- include/linux/irq.h

Make set_handle_irq and handle_arch_irq generic

This is the second version of a patch set titled "Use arm64's scheme for registering first-level IRQ handlers on RISC-V". That patch set's cover letter is still the best way to describe what's going on, so I'm just copying it here: This patch set has been sitting around for a while, but it

[PATCH v2 3/4] openrisc: Use the new MULTI_IRQ_HANDLER

It appears that openrisc copied arm64's MULTI_IRQ_HANDLER code (which came from arm). I wanted to make this generic so I could use it in the RISC-V port. This patch converts the openrisc code to use the generic version. Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- arch/op

[PATCH v2 4/4] RISC-V: Move to the new generic IRQ handler

an additional load to the interrupt latency, but there's a lot of tuning left to be done there on RISC-V so I think it's OK for now. Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- arch/riscv/Kconfig| 1 + arch/riscv/include/asm/Kbuild | 1 + arch/riscv/kernel/entry.S

Re: [patches] Re: [PATCH 1/2] asm-generic: Add a generic set_handle_irq

On Thu, 18 Jan 2018 07:45:13 PST (-0800), Christoph Hellwig wrote: I think this should not be asm-generic and lib, but kernel/irq/handle.c and include/linux/irq.h, under the CONFIG_MULTI_IRQ_HANDLER symbol already used by arm. Also for completeness of the series please convert arm, arm64 and

Re: [patches] Re: [GIT PULL] RISC-V: We have a new mailing list and git repo!

On Fri, 26 Jan 2018 15:13:19 PST (-0800), Linus Torvalds wrote: On Fri, Jan 26, 2018 at 2:39 PM, Palmer Dabbelt <pal...@sifive.com> wrote: I can understand if it's too late to get this into 4.15, but given that it's not a code change I was hoping it'd still be OK. No problem. Somethin

[GIT PULL] RISC-V: We have a new mailing list and git repo!

: Signature made Fri 26 Jan 2018 08:02:15 AM PST gpg:using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 gpg:issuer "pal...@dabbelt.com" gpg: Good signature from "Palmer Dabbelt <pal...@dabbelt.com>" [ultimate] gpg: aka "Pa

Re: [PATCH v3 2/2] MIPS: use generic GCC library routines from lib/

his commit removes several generic GCC library routines from arch/mips/lib/ in favour of similar routines from lib/. Signed-off-by: Antony Pavlov <antonynpav...@gmail.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Matt Redfearn <matt.redfe...@mips.com> Cc: James Hogan <jho...@

Re: [PATCH v2 1/2] Add notrace to lib/ucmpdi2.c

On Tue, 30 Jan 2018 14:42:01 PST (-0800), antonynpav...@gmail.com wrote: From: Palmer Dabbelt <pal...@sifive.com> As part of the MIPS conversion to use the generic GCC library routines, Matt Redfearn discovered that I'd missed a notrace on __ucmpdi2(). This patch rectifies the proble

Re: [PATCH 07/20] riscv: Remove ARCH_WANT_OPTIONAL_GPIOLIB select

Thanks! (If you want these through my tree, just say something.) Reviewed-by: Palmer Dabbelt <pal...@sifive.com>

Re: [PATCH 06/20] riscv: Remove ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select

elect COMMON_CLK Thanks! Reviewed-by: Palmer Dabbelt <pal...@sifive.com>

Re: [patches] [PATCH] RISC-V: Enable IRQ during exception handling

On Fri, 02 Feb 2018 01:45:28 PST (-0800), Christoph Hellwig wrote: Looks fine: Reviewed-by: Christoph Hellwig Thanks, I'm still working through my FOSDEM-related email backlog. I'll target this for the next RC, as it seems like a small enough fix. It should be in the next

Re: [PATCH 07/20] riscv: Remove ARCH_WANT_OPTIONAL_GPIOLIB select

ipped through, the symbol has been renamed RISCV_INTC. A patch to remove it is Reviewed-by: Palmer Dabbelt <pal...@sifive.com> (and like the other ones, if you want it through my tree just say something)

Re: [patches] [PATCH v3 0/6] Add dynamic ftrace support for RISC-V platforms

On Thu, 18 Jan 2018 07:45:39 PST (-0800), noner...@gmail.com wrote: This patch set includes the building blocks of dynamic ftrace features for RISC-V machines. Changes in v3: - Replace the nops at the tracer call sites into a "call ftrace_stub" instruction for better understanding (1/6 and

Re: [PATCH] tile/pci_gx: Make setup_pcie_rc_delay __init

Helgaas <bhelg...@google.com> Cc: Palmer Dabbelt <pal...@dabbelt.com> Cc: Chris Metcalf<cmetc...@mellanox.com> Cc: Andrew Morton <a...@linux-foundation.org> Signed-off-by: Dou Liyang <douly.f...@cn.fujitsu.com> --- arch/tile/kernel/pci_gx.c | 2 +- 1 file changed, 1 ins

Re: [GIT PULL] RISC-V changes for 4.16

Adding linux-kernel, which I forgot. Sorry! On Wed, 07 Feb 2018 09:58:15 PST (-0800), Palmer Dabbelt wrote: The following changes since commit d8a5b80568a9cb66810e75b182018e9edb68e8ff: Linux 4.15 (2018-01-28 13:20:33 -0800) are available in the git repository at: ssh://g

Re: [PATCH 07/20] riscv: Remove ARCH_WANT_OPTIONAL_GPIOLIB select

On Tue, 06 Feb 2018 01:47:00 PST (-0800), linus.wall...@linaro.org wrote: On Mon, Feb 5, 2018 at 2:21 AM, Ulf Magnusson wrote: The ARCH_WANT_OPTIONAL_GPIOLIB symbol was removed in commit 65053e1a7743 ("gpio: delete ARCH_[WANTS_OPTIONAL|REQUIRE]_GPIOLIB"). GPIOLIB should

Re: [PATCH] riscv: kconfig: Remove RISCV_IRQ_INTC select

On Thu, 08 Feb 2018 14:54:46 PST (-0800), ulfali...@gmail.com wrote: The RISCV_IRQ_INTC configuration symbol is undefined, but RISCV selects it. Quoting Palmer Dabbelt: It looks like this slipped through, the symbol has been renamed RISCV_INTC. No RISCV_INTC configuration

Re: [PATCH] lib: Rename compiler intrinsic selects to GENERIC_LIB_*

-by: Matt Redfearn <matt.redfe...@mips.com> Thanks! Do you want me to take this in my tree? Reviewed-by: Palmer Dabbelt <pal...@sifive.com> --- arch/riscv/Kconfig | 6 +++--- lib/Kconfig| 12 ++-- lib/Makefile | 12 ++-- 3 files changed, 15 inser

Re: [PATCH] lib: Rename compiler intrinsic selects to GENERIC_LIB_*

On Tue, 13 Feb 2018 14:49:37 PST (-0800), jho...@kernel.org wrote: On Tue, Feb 13, 2018 at 01:48:18PM -0800, Palmer Dabbelt wrote: On Fri, 09 Feb 2018 05:22:52 PST (-0800), matt.redfe...@mips.com wrote: > When these are included into arch Kconfig files, maintaining > alphabetical or

Re: [patches] Re: [PATCH v4 0/6] Add dynamic ftrace support for RISC-V platforms

On Tue, 20 Feb 2018 18:45:39 PST (-0800), alan...@andestech.com wrote: On Tue, Feb 13, 2018 at 01:13:15PM +0800, Alan Quey-Liang Kao(高魁良) wrote: This patch set includes the building blocks of dynamic ftrace features for RISC-V machines. Changes in v4: - Organize code structure according to

Re: [RFC PATCH 4/7] kconfig: support new special property shell

On Sun, 11 Feb 2018 12:06:35 PST (-0800), Linus Torvalds wrote: On Sun, Feb 11, 2018 at 11:53 AM, Linus Torvalds wrote: Well, it's still not a very *big* bump. With modern distros being at 7.3, and people testing pre-releases of gcc-8, something like gcc-4.5 is

Re: [PATCH RFC] riscv/barrier: Define __smp_{mb,rmb,wmb}

On Tue, 20 Feb 2018 02:17:28 PST (-0800), parri.and...@gmail.com wrote: Introduce __smp_{mb,rmb,wmb}, and rely on the generic definitions for smp_{mb,rmb,wmb}. A first consequence is that smp_{mb,rmb,wmb} map to a compiler barrier on !SMP (while their definition remains unchanged on SMP). As a

Re: [PATCH] riscv: Implement free_initrd_mem.

On Tue, 20 Feb 2018 05:50:43 PST (-0800), s...@shealevy.com wrote: Signed-off-by: Shea Levy --- arch/riscv/mm/init.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index c77df8142be2..1c832b541e95 100644 ---

[GIT PULL] RISC-V: Cleanups for 4.16-rc3

parse_dtb to improve code readability Palmer Dabbelt (1): RISC-V: kconfig cleanups Ulf Magnusson (3): riscv: Remove ARCH_WANT_OPTIONAL_GPIOLIB select riscv: kconfig: Remove RISCV_IRQ_INTC select riscv: Remove ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select zong...@gmail.com (1):

Re: [patches] [PATCH v4 0/6] Add dynamic ftrace support for RISC-V platforms

On Mon, 12 Feb 2018 21:13:15 PST (-0800), alan...@andestech.com wrote: This patch set includes the building blocks of dynamic ftrace features for RISC-V machines. Changes in v4: - Organize code structure according to changes in v3 - Rebase onto the riscv-linux-4.15 branch at github's

Re: [patches] [PATCH v3] riscv/ftrace: Add basic support

On Mon, 18 Dec 2017 01:52:48 PST (-0800), noner...@gmail.com wrote: This patch contains basic ftrace support for RV64I platform. Specifically, function tracer (HAVE_FUNCTION_TRACER), function graph tracer (HAVE_FUNCTION_GRAPH_TRACER), and a frame pointer test (HAVE_FUNCTION_GRAPH_FP_TEST) are

Re: [patches] [PATCH] irqchip/riscv-plic: fix address alignment of the plic enable bits

y about that. I think it's cleaner to use a 'u32 *' instead of 'void *' here, something more like this (which I haven't even compiled) commit 2424a65ce079ecbe16fbedc704b88b6f04f8b97a Author: Palmer Dabbelt <pal...@sifive.com> Date: Wed Dec 20 19:31:41 2017 -0800 void* -> u32* in PLI

Re: [patches] [PATCH] RISC-V: Support built-in dtb

On Wed, 20 Dec 2017 01:14:31 PST (-0800), zong...@gmail.com wrote: Build the dtb into the kernel image. If the DTB is given via bootloader, the external DTB is adopted first. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 4 arch/riscv/Makefile |

Re: [patches] [PATCH] RISC-V: Support built-in dtb

On Thu, 21 Dec 2017 12:43:20 PST (-0800), Arnd Bergmann wrote: On Thu, Dec 21, 2017 at 9:32 PM, Palmer Dabbelt <pal...@sifive.com> wrote: On Wed, 20 Dec 2017 01:14:31 PST (-0800), zong...@gmail.com wrote: I've added Arnd and Olof, in case they have a bit more perspective here.

Finish the GENERIC_IRQ_MULTI_HANDLER conversion

A while ago I sent a patch set that adds a GENERIC_IRQ_MULTI_HANDLER, which is an exact copy of the existing IRQ_MULTI_HANDLER support in the arm port, which is being used unconditionally by arm64 and openrisc. GENERIC_IRQ_MULTI_HANDLER is currently being used by the RISC-V port. I managed to

Re: [PATCH 3/3] irqchip: RISC-V Local Interrupt Controller Driver

On Fri, 22 Jun 2018 17:08:58 PDT (-0700), rdun...@infradead.org wrote: On 06/22/2018 04:20 PM, Palmer Dabbelt wrote: From: Palmer Dabbelt This patch adds a driver that manages the local interrupts on each RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. The local interrupt

Re: Finish the GENERIC_IRQ_MULTI_HANDLER conversion

On Sun, 24 Jun 2018 06:15:25 PDT (-0700), t...@linutronix.de wrote: On Thu, 21 Jun 2018, Palmer Dabbelt wrote: A while ago I sent a patch set that adds a GENERIC_IRQ_MULTI_HANDLER, which is an exact copy of the existing IRQ_MULTI_HANDLER support in the arm port, which is being used

Re: simplified RISC-V interrupt and clocksource handling v2

-by: Palmer Dabbelt is warranted. What's the best way to go about merging this? There's quite a bit of arch/riscv diff here so I don't mind taking it through the RISC-V tree, but there's also some irqchip and clocksource stuff as well so I'm not sure if that's OK to do.

Re: [PATCH 2/3] dt-bindings: interrupt-controller: RISC-V local interrupt controller docs

On Mon, 25 Jun 2018 13:04:48 PDT (-0700), christ...@boehmwalder.at wrote: On Fri, Jun 22, 2018 at 04:20:05PM -0700, Palmer Dabbelt wrote: From: Palmer Dabbelt This patch adds documentation on the RISC-V local interrupt controller, which is a per-hart interrupt controller that manages all

Re: [PATCH] riscv: remove unnecessary of_platform_populate call

. Neither of those apply here, so remove the call. Cc: Palmer Dabbelt Cc: Albert Ou Cc: linux-ri...@lists.infradead.org Signed-off-by: Rob Herring --- arch/riscv/kernel/setup.c | 5 - 1 file changed, 5 deletions(-) Ping? Sorry for not saying anything, I don't have a good scheme

Re: [PATCH v9 04/12] RISC-V: Init and Halt Code

), mark.rutl...@arm.com wrote: > On Tue, Sep 26, 2017 at 06:56:30PM -0700, Palmer Dabbelt wrote: >> +/* >> + * This is particularly ugly: it appears we can't actually get the >> definition >> + * of task_struct here, but we need access to the CPU this task is running >&

Re: [PATCH 1/6] RISC-V: simplify software interrupt / IPI code

RQ_HANDLED; } static void Acked-by: Palmer Dabbelt I think it's probably easier to have the whole patch set go through the IRQ tree, so I won't put these in the RISC-V tree unless someone says something.

Re: [PATCH 2/6] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h

INTERRUPT_CAUSE_TIMER 5 -#define INTERRUPT_CAUSE_EXTERNAL9 - void riscv_timer_interrupt(void); #include Acked-by: Palmer Dabbelt

Re: [PATCH v2] riscv: Add support to no-FPU systems

On Tue, 26 Jun 2018 21:22:26 PDT (-0700), alan...@andestech.com wrote: This patch adds an option, CONFIG_FPU, to enable/disable floating procedures. Also, some style issues are fixed. Signed-off-by: Alan Kao Cc: Greentime Hu Cc: Zong Li --- arch/riscv/Kconfig | 9

Re: [PATCH] RISC-V: Add the directive for alignment of stvec's value

On Wed, 20 Jun 2018 18:40:07 PDT (-0700), z...@andestech.com wrote: The stvec's value must be 4 byte alignment by specification definition. This directive avoids to stvec be set the non-alignment value by the following code in head.S /* Point stvec to virtual address of intruction after satp

Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation

On Wed, 08 Aug 2018 07:16:14 PDT (-0700), robh...@kernel.org wrote: On Tue, Aug 7, 2018 at 8:17 PM Palmer Dabbelt wrote: On Mon, 06 Aug 2018 13:59:48 PDT (-0700), robh...@kernel.org wrote: > On Thu, Aug 2, 2018 at 4:08 PM Atish Patra wrote: >> >> On 8/2/18 4:50 AM, Christop

Re: [PATCH 6/8] dt-bindings: interrupt-controller: RISC-V PLIC documentation

On Wed, 08 Aug 2018 09:15:58 PDT (-0700), robh...@kernel.org wrote: On Wed, Aug 8, 2018 at 8:59 AM Christoph Hellwig wrote: On Wed, Aug 08, 2018 at 08:29:50AM -0600, Rob Herring wrote: > Version numbers on the individual patches would be nice... We've never done these in the subsystems I'm

Re: [RFC] RISC-V: Fix !CONFIG_SMP compilation error

On Fri, 10 Aug 2018 11:31:08 PDT (-0700), atish.pa...@wdc.com wrote: On 8/6/18 4:17 PM, Atish Patra wrote: Enabling both CONFIG_PERF_EVENTS without !CONFIG_SMP generates following compilation error. arch/riscv/include/asm/perf_event.h:80:2: error: expected specifier-qualifier-list before

Re: [PATCH v3 1/2] RISC-V: Define sys_riscv_flush_icache when SMP=n

On Fri, 10 Aug 2018 11:47:15 PDT (-0700), li...@roeck-us.net wrote: On Fri, Aug 10, 2018 at 11:27:37AM -0700, Palmer Dabbelt wrote: On Fri, 10 Aug 2018 01:38:04 PDT (-0700), Christoph Hellwig wrote: >On Thu, Aug 09, 2018 at 03:19:51PM -0700, Palmer Dabbelt wrote: >>This would be

Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation

On Fri, 10 Aug 2018 09:57:03 PDT (-0700), robh...@kernel.org wrote: On Thu, Aug 9, 2018 at 12:29 AM Palmer Dabbelt wrote: On Wed, 08 Aug 2018 16:32:07 PDT (-0700), robh...@kernel.org wrote: > On Wed, Aug 8, 2018 at 1:38 PM Palmer Dabbelt wrote: >> >> On Wed, 08 Aug 2018 07:1

Re: [PATCH 03/11] dt-bindings: interrupt-controller: RISC-V PLIC documentation

On Wed, 08 Aug 2018 16:32:07 PDT (-0700), robh...@kernel.org wrote: On Wed, Aug 8, 2018 at 1:38 PM Palmer Dabbelt wrote: On Wed, 08 Aug 2018 07:16:14 PDT (-0700), robh...@kernel.org wrote: > On Tue, Aug 7, 2018 at 8:17 PM Palmer Dabbelt wrote: >> >> On Mon, 06 Aug 2018 13:5

Re: [PATCH v3 1/2] RISC-V: Define sys_riscv_flush_icache when SMP=n

On Fri, 10 Aug 2018 01:38:04 PDT (-0700), Christoph Hellwig wrote: On Thu, Aug 09, 2018 at 03:19:51PM -0700, Palmer Dabbelt wrote: This would be necessary to make non-SMP builds work, but there is another error in the implementation of our syscall linkage that actually just causes

Re: [PATCH] spi-nor: add support for is25wp256d

On Sat, 04 Aug 2018 02:27:54 PDT (-0700), marek.va...@gmail.com wrote: On 08/04/2018 03:49 AM, Palmer Dabbelt wrote: From: "Wesley W. Terpstra" This is used of the HiFive Unleashed development board. Signed-off-by: Wesley W. Terpstra Signed-off-by: Palmer Dabbelt --- drivers/m

Re: RISC-V: Don't use a global include guard for uapi/asm/syscalls.h

On Sat, 04 Aug 2018 01:54:38 PDT (-0700), Christoph Hellwig wrote: >> index 818655b0d535..882a6aa09a33 100644 >> --- a/arch/riscv/include/uapi/asm/syscalls.h >> +++ b/arch/riscv/include/uapi/asm/syscalls.h >> @@ -1,10 +1,11 @@ >> -/* SPDX-License-Identifier: GPL-2.0 */ >> +//

[PATCH v2] RISC-V: Don't use a global include guard for uapi/asm/syscalls.h

is the canonical way to do it. Cc: Marcus Comstedt Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/unistd.h| 5 + arch/riscv/include/uapi/asm/syscalls.h | 15 +-- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv

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