Hi Andre,
> Subject: Re: [PATCH V9 1/2] dt-bindings: mailbox: add binding doc for the
> ARM SMC/HVC mailbox
>
[...]
> > + supported identifier are passed from consumers, or listed in the
> > + the arm,func-id
>
> ^
> This is now obsolete
From: Peng Fan
Introduce HOLE/ECC_REGION flag and in_hole helper to ease the check
of hole region. The ECC_REGION is also introduced here which is
preparing for programming support. ECC_REGION could only be programmed
once, so need take care.
Signed-off-by: Peng Fan
---
V2:
Rebased on latest
From: Peng Fan
The fuse programming from non-secure world is blocked, so we could
only use Arm Trusted Firmware SIP call to let ATF program fuse.
Because there is ECC region that could only be programmed once,
so add a heler in_ecc to check the ecc region.
Signed-off-by: Peng Fan
---
V2
since merge window is open?
Thanks,
Peng.
>
> Thanks,
> srini
> > Thanks,
> > Peng.
> >
> >>
> >> From: Peng Fan
> >>
> >> The fuse programming from non-secure world is blocked, so we could
> >> only use Arm Trusted Firmware SI
From: Peng Fan
V7:
Typo fix
#mbox-cells changed to 0
Add a new header file arm-smccc-mbox.h
Use ARM_SMCCC_IS_64
Andre,
The function_id is still kept in arm_smccc_mbox_cmd, because arm,func-id
property is optional, so clients could pass function_id to mbox driver.
V6:
Switch to per-channel a
From: Peng Fan
The ARM SMC/HVC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Lt
From: Peng Fan
This mailbox driver implements a mailbox which signals transmitted data
via an ARM smc (secure monitor call) instruction. The mailbox receiver
is implemented in firmware and can synchronously return data when it
returns execution to the non-secure world again.
An asynchronous
From: Peng Fan
This mailbox driver implements a mailbox which signals transmitted data
via an ARM smc (secure monitor call) instruction. The mailbox receiver
is implemented in firmware and can synchronously return data when it
returns execution to the non-secure world again.
An asynchronous
From: Peng Fan
V8:
Add missed arm-smccc-mbox.h
V7:
Typo fix
#mbox-cells changed to 0
Add a new header file arm-smccc-mbox.h
Use ARM_SMCCC_IS_64
Andre,
The function_id is still kept in arm_smccc_mbox_cmd, because arm,func-id
property is optional, so clients could pass function_id to mbox
From: Peng Fan
The ARM SMC/HVC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Lt
Hi Florian
> Subject: Re: [PATCH V8 2/2] mailbox: introduce ARM SMC based mailbox
>
> Hi Peng,
>
> On 9/23/2019 6:14 PM, Peng Fan wrote:
> > From: Peng Fan
> >
> > This mailbox driver implements a mailbox which signals transmitted
> > data via an ARM smc
Hi Andre,
> Subject: Re: [PATCH V7 0/2] mailbox: arm: introduce smc triggered mailbox
>
> On 23/09/2019 07:36, Peng Fan wrote:
>
> Hi Peng,
>
> thanks for the update!
>
> > From: Peng Fan
> >
> > V7:
> > Typo fix
> > #mbox-cells chang
Hi Stephen,
> Subject: Re: [PATCH] clk: imx8mn: fix int pll clk gate
>
> Quoting peng@nxp.com (2019-08-13 18:53:12)
> > From: Peng Fan
> >
> > To Frac pll, the gate shift is 13, however to Int PLL the gate shift
> > is 11.
> >
> > Cc:
> &
From: Peng Fan
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.
Signed-
From: Peng Fan
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."
So set BYPASS when RESETB is changed from 0 to 1 to avoid glit
Hi Rob,
> Subject: Re: [PATCH v3 1/2] dt-bindings: mailbox: add binding doc for the ARM
> SMC/HVC mailbox
>
> On Mon, Jul 15, 2019 at 4:10 AM Peng Fan wrote:
> >
> > From: Peng Fan
> >
> > The ARM SMC/HVC mailbox binding describes a firmware interface to
&g
Hi Sudeep,
> Subject: Re: [PATCH v3 1/2] dt-bindings: mailbox: add binding doc for the ARM
> SMC/HVC mailbox
>
> This looks much better now.
>
> On Mon, Jul 15, 2019 at 10:10:10AM +, Peng Fan wrote:
> > From: Peng Fan
> >
> > The ARM SMC/HVC mailbox bi
Hi Abel, Aisheng, Leonard and all
> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
> clk
>
> > > > +
> > > > + return clk_mux_val_to_index(hw, mux->table, mux->flags, val); }
> > >
> > > You don't have to redefinition them if they're the same as clk_mux_ops.
>
> Subject: Re: [RFC PATCH 3/4] drm/etnaviv: Change order of enabling clocks to
> fix boot on i.MX8MM
>
> On 30.04.20 16:35, Lucas Stach wrote:
> > Am Donnerstag, den 30.04.2020, 12:46 + schrieb Schrempf Frieder:
> >> From: Frieder Schrempf
> >>
> >> On some i.MX8MM devices the boot hangs when
From: Peng Fan
i.MX7ULP's ARM core clock design is totally different compared
with i.MX7D/8M SoCs which supported by imx-cpufreq-dt. It needs
get_intermediate and target_intermedate to configure clk MUX ready,
before let OPP configure ARM cor
From: Peng Fan
When booting xen on i.MX8QM, met:
"
[3.602128] Unable to handle kernel paging request at virtual address
00272d40
[3.610804] Mem abort info:
[3.613905] ESR = 0x9604
[3.617332] EC = 0x25: DABT (current EL), IL = 32 bits
[3.623211] SET = 0
age_boundary(phys, size) are true, it will create
> > contiguous region. So when free, we need to free contiguous region use
> > upper check condition.
> >
> > Signed-off-by: Peng Fan
> > ---
> > drivers/xen/swiotlb-xen.c | 4 ++--
> > 1 file changed, 2 ins
> Subject: Re: [PATCH] xen/swiotlb: correct the check for
> xen_destroy_contiguous_region
>
> On 28.04.20 09:33, peng@nxp.com wrote:
> > From: Peng Fan
> >
> > When booting xen on i.MX8QM, met:
> > "
> > [3.602128] Unable to
From: Peng Fan
The soc device register code will be moved to drivers/soc/imx/,
the code needs the cpu type definitions. So let's move the cpu
type definitions to a header.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/mxc.h | 22 +-
include/soc/imx/cpu.h
From: Peng Fan
This is preparation to move imx_soc_device_init to drivers/soc/imx/
There is no reason to must put dt devices under /sys/devices/soc0,
they could also be under /sys/devices/platform, so we could
pass NULL as parent when calling of_platform_default_populate.
Following soc-imx8.c
From: Peng Fan
Move the soc device register code to drivers/soc/imx to align with
i.MX8.
Signed-off-by: Peng Fan
---
V2:
Use CONFIG_ARM to guard compile
arch/arm/mach-imx/cpu.c | 166 ---
drivers/soc/imx/Makefile | 3 +
drivers/soc/imx/soc-imx.c
From: Peng Fan
V2:
Keep i.MX1/2/3/5 cpu type for completness
Correct return value in patch 1/3
use CONFIG_ARM to guard compile soc-imx.c in patch 3/3
V1:
https://patchwork.kernel.org/cover/11433689/
RFC version :
https://patchwork.kernel.org/cover/11336433/
Nothing changed in v1, just
From: Peng Fan
Select ARM_GIC_V3, then it is able to use gic v3 driver in aarch32
mode linux on aarch64 hardware. For aarch64 mode, it not hurts
to select ARM_GIC_V3.
Acked-by: Arnd Bergmann
Signed-off-by: Peng Fan
---
drivers/soc/imx/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1
Hi Shawn,
> Subject: [PATCH] soc: imx: select ARM_GIC_V3 for i.MX8M
Forget to use v2 and mention that this is resend
https://patchwork.kernel.org/patch/11435941/
If you need v2, I could resend with v2.
Thanks,
Peng.
>
> From: Peng Fan
>
> Select ARM_GIC_V3, then it is abl
From: Peng Fan
The PLL enum definition is not used, so drop it.
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-imx8mn.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 28467db10c69..6ab6e9228962 100644
--- a
> Subject: Re: [PATCH] clk: imx: imx8mn: drop unused pll enum
>
> Quoting Peng Fan (2019-10-15 00:05:53)
> > From: Peng Fan
> >
> > The PLL enum definition is not used, so drop it.
> >
> > Signed-off-by: Peng Fan
> > ---
>
> Was it
From: Peng Fan
We should not rely on U-Boot to configure the phy reset.
So introduce phy-reset-gpios property to let Linux handle phy reset
itself.
Signed-off-by: Peng Fan
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot
From: Peng Fan
We should not rely on U-Boot to configure the phy reset.
So introduce phy-reset-gpios property to let Linux handle phy reset
itself.
Signed-off-by: Peng Fan
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts
> Subject: Re: [PATCH 1/2] arm64: dts: imx8mm-evk: add phy-reset-gpios for
> fec1
>
> Hi,
>
> On 19-10-21 09:21, Peng Fan wrote:
> > From: Peng Fan
> >
> > We should not rely on U-Boot to configure the phy reset.
> > So introduce phy-reset-gpios propert
From: Peng Fan
We should not rely on bootloader to configure the phy reset.
So introduce phy-reset-gpios property to let Linux handle phy reset
itself.
Signed-off-by: Peng Fan
Reviewed-by: Marco Felsch
---
V2:
U-Boot->bootloader
Add R-b tag
arch/arm64/boot/dts/freescale/imx8mm-evk.
From: Peng Fan
We should not rely on bootloader to configure the phy reset.
So introduce phy-reset-gpios property to let Linux handle phy reset
itself.
Signed-off-by: Peng Fan
---
V2:
U-Boot->bootloader
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 1 +
1 file changed, 1 insert
In case cma_init_reserved_mem failed, need to free the memblock allocated
by memblock_reserve or memblock_alloc_range.
Signed-off-by: Peng Fan
---
V1:
code inspection, I do not met failure in cma_init_reserved_mem.
mm/cma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
Hi Andrew
> -Original Message-
> From: Andrew Morton [mailto:a...@linux-foundation.org]
> Sent: 2019年2月15日 4:38
> To: Peng Fan
> Cc: labb...@redhat.com; mho...@suse.com; vba...@suse.cz;
> iamjoonsoo@lge.com; r...@linux.vnet.ibm.com;
> m.szyprow...@samsung.com;
oop check. In case we do have nr_groups equals with NR_CPUS,
we could also avoid memory access out of bounds.
Signed-off-by: Peng Fan
---
mm/percpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/percpu.c b/mm/percpu.c
index db86282fd024..c5c750781628 100644
--- a/mm/perc
arm64_memory_present is doing same thing as memblocks_present, so
let's use common code memblocks_present instead of platform
specific arm64_memory_present.
Signed-off-by: Peng Fan
---
arch/arm64/mm/init.c | 20 +---
1 file changed, 1 insertion(+), 19 deletions(-)
diff --
Hi
> -Original Message-
> From: h...@infradead.org [mailto:h...@infradead.org]
> Sent: 2019年1月21日 16:29
> To: Peng Fan
> Cc: m...@redhat.com; jasow...@redhat.com; sstabell...@kernel.org;
> h...@infradead.org; virtualizat...@lists.linux-foundation.org;
> xen-de...
> -Original Message-
> From: h...@infradead.org [mailto:h...@infradead.org]
> Sent: 2019年1月28日 16:00
> To: Peng Fan
> Cc: h...@infradead.org; Stefano Stabellini ;
> m...@redhat.com; jasow...@redhat.com; xen-de...@lists.xenproject.org;
> linux-remotep...@vger.ker
el panic.
With this patch, vring_use_dma_api will return false, and
vring_map_one_sg will return sg_phys(sg) which is the correct phys
address in the predefined memory region.
vring_map_one_sg -> vring_use_dma_api
-> sg_phys(sg)
Signed-off-by: Peng Fan
---
drivers/virtio/virt
> -Original Message-
> From: Stefano Stabellini [mailto:sstabell...@kernel.org]
> Sent: 2019年1月23日 4:00
> To: Peng Fan
> Cc: m...@redhat.com; jasow...@redhat.com; sstabell...@kernel.org;
> h...@infradead.org; xen-de...@lists.xenproject.org;
> linux-remotep...@v
Hi stefano,
> -Original Message-
> From: Stefano Stabellini [mailto:sstabell...@kernel.org]
> Sent: 2019年1月24日 7:44
> To: h...@infradead.org
> Cc: Stefano Stabellini ; Peng Fan
> ; m...@redhat.com; jasow...@redhat.com;
> xen-de...@lists.xenproject.org; linux-remot
Hi,
> -Original Message-
> From: h...@infradead.org [mailto:h...@infradead.org]
> Sent: 2019年1月24日 5:14
> To: Stefano Stabellini
> Cc: h...@infradead.org; Peng Fan ; m...@redhat.com;
> jasow...@redhat.com; xen-de...@lists.xenproject.org;
> linux-remotep...@vger.ker
Hi Aisheng,
> Subject: RE: [PATCH V2 2/4] nvmem: imx: add i.MX8 nvmem driver
>
> > From: Peng Fan
> > Sent: Wednesday, May 8, 2019 10:56 AM
> >
> > This patch adds i.MX8 nvmem ocotp driver to access fuse via RPC to
> > i.MX8 system controller.
> >
>
There is no audio_pll2_clk registered, it should be audio_pll2_out.
Cc:
Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-imx8mm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/c
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
move address/size-cells below compatible, add "scu"
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
No change
V2:
rename patch title, add review tag
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 979a95c915b6..32b85102b857 100644
--- a/arch
: Stephen Boyd
Cc: Anson Huang
Cc: devicet...@vger.kernel.org
Reviewed-by: Rob Herring
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
Move OCOTP to end, add example, add "scu"
.../devicetree/bindings/arm/freescale/fsl,scu.txt | 22
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Peng Fan
---
V3:
Use
Hi Srinivas,
> Subject: Re: [PATCH V3 2/4] nvmem: imx: add i.MX8 nvmem driver
>
>
>
> On 15/05/2019 08:53, Peng Fan wrote:
> > This patch adds i.MX8 nvmem ocotp driver to access fuse via RPC to
> > i.MX8 system controller.
> >
> > Cc: Srinivas Kandag
The rate_discrete needs to be assigned to clk->rate_discrete,
then scmi_clk_round_rate could get the value.
Fixes: 5f6c6430e904 ("firmware: arm_scmi: add initial support for clock
protocol")
Signed-off-by: Peng Fan
---
drivers/firmware/arm_scmi/clock.c | 2 ++
1 file changed,
kernel.org/patchwork/patch/812999/
Cc: Andre Przywara
Signed-off-by: Peng Fan
---
drivers/mailbox/Kconfig | 7 ++
drivers/mailbox/Makefile| 2 +
drivers/mailbox/arm-smc-mailbox.c | 154
include/linux/mailbox/arm-smc-mailb
The ARM SMC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Ltd.
Signed-off-by
mware/tree/scmi
Peng Fan (2):
DT: mailbox: add binding doc for the ARM SMC mailbox
mailbox: introduce ARM SMC based mailbox
.../devicetree/bindings/mailbox/arm-smc.txt| 96 +
drivers/mailbox/Kconfig| 7 +
drivers/m
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Cc:
Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
Reviewed-by: Jacky Bai
---
V3:
Move Fixes Tag to correct place
V2:
Update c
for the serval parts, instead
we could provide one device tree and let Firmware to runtime disable
the device tree nodes for those modules that are disable(fused).
Signed-off-by: Peng Fan
---
Currently NXP vendor use U-Boot to set status to disabled for devices
that could not function,
https
Add fusable-node property for OCOTP
Signed-off-by: Peng Fan
---
arch/arm/boot/dts/imx6ull.dtsi | 7 +++
arch/arm/boot/dts/imx6ulz.dtsi | 6 ++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 22e4a307fa59..b616ed6ee4bf
> Subject: Re: [RFC 1/2] dt-bindings: imx-ocotp: Add fusable-node property
>
> On 20.05.2019 06:06, Peng Fan wrote:
> > Introduce fusable-node property for i.MX OCOTP driver.
> > The property will only be used by Firmware(eg. U-Boot) to runtime
> > disable the nodes
From: Peng Fan
Add i.MX8QXP ocotp node
Cc: Rob Herring
Cc: Mark Rutland
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Anson Huang
Cc: Daniel Baluta
Cc: devicet...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Reviewed-by
From: Peng Fan
Build in CONFIG_NVMEM_IMX_OCOTP_SCU.
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Shawn Guo
Cc: Andy Gross
Cc: Maxime Ripard
Cc: Olof Johansson
Cc: Jagan Teki
Cc: Bjorn Andersson
Cc: Leonard Crestez
Cc: Marc Gonzalez
Cc: Enric Balletbo i Serra
Cc: linux-arm-ker
Hi Shawn,
> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: 2019年5月23日 20:53
> To: Peng Fan
> Cc: srinivas.kandaga...@linaro.org; robh...@kernel.org;
> s.ha...@pengutronix.de; feste...@gmail.com; dl-linux-imx
> ; linux-kernel@vger.kernel
Hi Jassi,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> On Thu, May 23, 2019 at 12:50 AM Peng Fan wrote:
> >
> > This is a modified version from Andre Przywara's patch series
> >
> https://eur01.safelinks.protection.out
Hi Florian,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> Hi,
>
> On 5/22/19 10:50 PM, Peng Fan wrote:
> > This is a modified version from Andre Przywara's patch series
> >
> https://eur01.safelinks.protection.outlook.com/?u
Hi Sudeep,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> On Thu, May 23, 2019 at 10:30:50AM -0700, Florian Fainelli wrote:
> > Hi,
> >
> > On 5/22/19 10:50 PM, Peng Fan wrote:
> > > This is a modified version from Andre Przywara&
Hi Andre,
> Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox
>
> On 24/05/2019 18:56, Sudeep Holla wrote:
> > On Thu, May 23, 2019 at 10:30:50AM -0700, Florian Fainelli wrote:
>
> Hi,
>
> >> On 5/22/19 10:50 PM, Peng Fan wrote:
> >&
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
No change
V2:
rename patch title, add review tag
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 979a95c915b6..32b85102b857 100644
--- a/arch
: Stephen Boyd
Cc: Anson Huang
Cc: devicet...@vger.kernel.org
Reviewed-by: Rob Herring
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
Move OCOTP to end, add example, add "scu"
.../devicetree/bindings/arm/freescale/fsl,scu.txt | 22
Signed-off-by: Peng Fan
---
V3:
Add R-b tag
V2:
move address/size-cells below compatible, add "scu"
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Peng Fan
---
V3:
Use
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller(SCU), the ocotp controller is being controlled
by the SCU, so Linux need use RPC to SCU for ocotp handling. This
patch adds binding doc for i.MX8 SCU OCOTP driver.
Signed-off-by: Peng Fan
Cc: Rob Herring
Cc: Mark
Build in CONFIG_NVMEM_IMX_OCOTP_SCU.
Signed-off-by: Peng Fan
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Shawn Guo
Cc: Andy Gross
Cc: Maxime Ripard
Cc: Olof Johansson
Cc: Jagan Teki
Cc: Bjorn Andersson
Cc: Leonard Crestez
Cc: Marc Gonzalez
Cc: Enric Balletbo i Serra
Cc: linux-arm-ker
Add i.MX8QXP ocotp node
Signed-off-by: Peng Fan
Cc: Rob Herring
Cc: Mark Rutland
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: Aisheng Dong
Cc: Anson Huang
Cc: Daniel Baluta
Cc: devicet...@vger.kernel.org
Cc: linux-arm-ker
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Signed-off-by: Peng Fan
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
---
drivers
Hi Aisheng,
> Subject: RE: [PATCH 2/4] nvmem: imx: add i.MX8 nvmem driver
>
> > From: Peng Fan
> > Sent: Sunday, May 5, 2019 9:28 PM
> > Subject: [PATCH 2/4] nvmem: imx: add i.MX8 nvmem driver
> >
> > This patch adds i.MX8 nvmem ocotp driver to access fuse vi
Hi Aisheng,
> Subject: RE: [PATCH 1/4] dt-bindings: fsl: scu: add ocotp binding
>
> > From: Peng Fan
> > Sent: Sunday, May 5, 2019 9:28 PM
> >
> > NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> > controller(SCU), the ocotp controller is
This patch adds i.MX8 nvmem ocotp driver to access fuse via
RPC to i.MX8 system controller.
Cc: Srinivas Kandagatla
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Pengutronix Kernel Team
Cc: Fabio Estevam
Cc: NXP Linux Team
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Peng Fan
---
V2:
Add
Cc: Shawn Guo
Cc: Ulf Hansson
Cc: Stephen Boyd
Cc: Anson Huang
Cc: devicet...@vger.kernel.org
Signed-off-by: Peng Fan
---
V2:
Move OCOTP to end, add example, add "scu"
.../devicetree/bindings/arm/freescale/fsl,scu.txt | 22 ++
1 file changed, 22 insertions(+)
-by: Peng Fan
---
V2:
move address/size-cells below compatible, add "scu"
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 0683ee2a48ae..72
Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan
---
V2:
rename patch title, add review tag
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index eb31c20e9914..9d8a512fc3d5 100644
--- a/arch/arm64/configs
From: Peng Fan
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.
Cc:
From: Peng Fan
V3:
Drop interrupt
Introduce transports for mem/reg usage
Add chan-id for mem usage
Convert to yaml format
V2:
This is a modified version from Andre Przywara's patch series
https://lore.kernel.org/patchwork/cover/812997/.
The modification are mostly:
Introduce arm,num-
From: Peng Fan
The ARM SMC/HVC mailbox binding describes a firmware interface to trigger
actions in software layers running in the EL2 or EL3 exception levels.
The term "ARM" here relates to the SMC instruction as part of the ARM
instruction set, not as a standard endorsed by ARM Lt
From: Peng Fan
This mailbox driver implements a mailbox which signals transmitted data
via an ARM smc (secure monitor call) instruction. The mailbox receiver
is implemented in firmware and can synchronously return data when it
returns execution to the non-secure world again.
An asynchronous
From: Peng Fan
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Cc:
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
---
drivers/clk/imx/clk-imx8mn.c | 12 ++--
1 file
domain, PERF_LEVEL_SET,
> + &fc->level_set_addr, &fc->level_set_db);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LEVEL_GET,
> + &fc->level_get_addr, NULL);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_SET,
> + &fc->limit_set_addr, &fc->limit_set_db);
> + scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_GET,
> + &fc->limit_get_addr, NULL);
> + *p_fc = fc;
> +}
> +
> /* Device specific ops */
> static int scmi_dev_domain_id(struct device *dev) { @@ -494,6 +636,9
> @@ static int scmi_perf_protocol_init(struct scmi_handle *handle)
>
> scmi_perf_domain_attributes_get(handle, domain, dom);
> scmi_perf_describe_levels_get(handle, domain, dom);
> +
> + if (dom->perf_fastchannels)
> + scmi_perf_domain_init_fc(handle, domain, &dom->fc_info);
> }
>
> handle->perf_ops = &perf_ops;
Reviewed-by: Peng Fan
> --
> 2.17.1
2
> +domain,
> u32 *level, bool poll)
> {
> int ret;
> @@ -387,6 +469,20 @@ static int scmi_perf_level_get(const struct
> scmi_handle *handle, u32 domain,
> return ret;
> }
>
> +static int scmi_perf_level_get(const struct scmi_handle *handle, u32
> domain,
> +u32 *level, bool poll)
> +{
> + struct scmi_perf_info *pi = handle->perf_priv;
> + struct perf_dom_info *dom = pi->dom_info + domain;
> +
> + if (dom->fc_info && dom->fc_info->level_get_addr) {
> + *level = ioread32(dom->fc_info->level_get_addr);
> + return 0;
> + }
> +
> + return scmi_perf_mb_level_get(handle, domain, level, poll); }
> +
> static bool scmi_perf_fc_size_is_valid(u32 msg, u32 size) {
> if ((msg == PERF_LEVEL_GET || msg == PERF_LEVEL_SET) && size == 4)
Reviewed-by: Peng Fan
> --
> 2.17.1
* @clk_ops: pointer to set of clock protocol operations
> * @sensor_ops: pointer to set of sensor protocol operations
> + * @reset_ops: pointer to set of reset protocol operations
> * @perf_priv: pointer to private data structure specific to performance
> * protocol(for internal use only)
> * @clk_priv: pointer to private data structure specific to clock @@ -204,6
> +225,8 @@ struct scmi_sensor_ops {
> * protocol(for internal use only)
> * @sensor_priv: pointer to private data structure specific to sensors
> * protocol(for internal use only)
> + * @reset_priv: pointer to private data structure specific to reset
> + * protocol(for internal use only)
> */
> struct scmi_handle {
> struct device *dev;
> @@ -212,11 +235,13 @@ struct scmi_handle {
> struct scmi_clk_ops *clk_ops;
> struct scmi_power_ops *power_ops;
> struct scmi_sensor_ops *sensor_ops;
> + struct scmi_reset_ops *reset_ops;
> /* for protocol internal use */
> void *perf_priv;
> void *clk_priv;
> void *power_priv;
> void *sensor_priv;
> + void *reset_priv;
> };
>
> enum scmi_std_protocol {
> @@ -226,6 +251,7 @@ enum scmi_std_protocol {
> SCMI_PROTOCOL_PERF = 0x13,
> SCMI_PROTOCOL_CLOCK = 0x14,
> SCMI_PROTOCOL_SENSOR = 0x15,
> + SCMI_PROTOCOL_RESET = 0x16,
> };
Reviewed-by: Peng Fan
>
> struct scmi_device {
> --
> 2.17.1
Hi Stephen,
> Subject: Re: [PATCH] clk: imx: imx8mm: fix audio pll setting
>
> Quoting Peng Fan (2019-07-14 19:55:43)
> > From: Peng Fan
> >
> > The AUDIO PLL max support 650M, so the original clk settings violate
> > spec. This patch makes the output 78643200
ARM64, need use __GFP_DMA32.
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/xen/mm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c index
> e1d44b903dfc..a95e76d18bf9 100644
> --- a/arch/arm/xen/mm.c
>
Hi All,
> Subject: [PATCH v3 2/2] mailbox: introduce ARM SMC based mailbox
Any comments with this patch?
>
> From: Peng Fan
>
> This mailbox driver implements a mailbox which signals transmitted data via
> an ARM smc (secure monitor call) instruction. The mailbox receiver i
Hi Jassi,
> -Original Message-
> From: Jassi Brar [mailto:jassisinghb...@gmail.com]
> Sent: 2019年6月21日 0:50
> To: Peng Fan
> Cc: Rob Herring ; Mark Rutland
> ; Sudeep Holla ; Florian
> Fainelli ; , Sascha Hauer ;
> dl-linux-imx ; Shawn Guo ;
> feste...@gmail.c
Hi Sudeep,
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Thu, Jun 20, 2019 at 10:21:09AM +0000, Peng Fan wrote:
> > Hi Sudeep,
> >
> > > Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
> > >
> > >
Hi Jassi
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Mon, Jun 3, 2019 at 3:28 AM wrote:
> >
> > From: Peng Fan
> >
> > This mailbox driver implements a mailbox which signals transmitted
> > data via an ARM smc (secure
Hi All,
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Tue, Jun 25, 2019 at 2:30 AM Peng Fan wrote:
> >
> > Hi Jassi
> >
> > > Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
> > >
Hi Andre,
> Subject: Re: [PATCH V2 2/2] mailbox: introduce ARM SMC based mailbox
>
> On Mon, 3 Jun 2019 09:32:42 -0700
> Florian Fainelli wrote:
>
> Hi,
>
> > On 6/3/19 1:30 AM, peng@nxp.com wrote:
> > > From: Peng Fan
> > >
> > >
Hi Shawn, Stephen
> Subject: Re: linux-next: Fixes tag needs some work in the imx-mxs tree
>
> On Fri, Jun 07, 2019 at 07:46:52AM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > In commit
> >
> > f6a8ff82ce68 ("clk: imx: imx8mm: correct audio_pll2_clk to
> > audio_pll2_out")
> >
> > Fixes tag
Hi Rob,
> Subject: Re: [PATCH V2 1/2] DT: mailbox: add binding doc for the ARM SMC
> mailbox
>
> On Mon, Jun 03, 2019 at 04:30:04PM +0800, peng@nxp.com wrote:
> > From: Peng Fan
> >
> > The ARM SMC mailbox binding describes a firmware interface to trigger
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