m-kernel/2015-March/332615.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/332608.html
[4] https://lwn.net/Articles/740994/
[5] https://lkml.org/lkml/2017/12/19/537
Sricharan R (2):
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: cpufreq: Document ope
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names properties newly
.../devicetree/bindings/clock/qcom,hfp
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] updated to include clocks and clock-names property newly
.../devicetree/bi
-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Signed-off-by: Sricharan
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Acked-by: Viresh Kumar
[Sricharan: updated to use dev_pm_opp_set_prop_name and
nvmem apis]
Signed-off-by: Sricharan R
[Thierry Escande: upd
itching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
[v10] Updated to add clocks and clock-names property newly
.../devicetr
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
Fix all nodes to use proper GIC_* macros for the interrupt type and the
interrupt trigger settings to avoid the boot warnings.
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 41 ++---
1 file changed, 24 insertions(+), 17 deletions(-)
diff
Hi Stephen,
On 5/30/2018 9:25 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-24 22:40:11)
>> Hi Bjorn,
>>
>> On 5/24/2018 11:09 PM, Bjorn Andersson wrote:
>>> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
>>>
>>>> From: Stephen Bo
urn ret;
> + }
> +
> + q6v5->state = qcom_smem_state_get(&pdev->dev, "stop", &q6v5->stop_bit);
> + if (IS_ERR(q6v5->state)) {
> + dev_err(&pdev->dev, "failed to acquire stop state\n");
> + return
adsp->ready_irq = ret;
> -
> - ret = adsp_request_irq(adsp, pdev, "handover", adsp_handover_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->handover_irq = ret;
> -
> - ret = adsp_request_irq(adsp, pdev, "stop-a
gt;
> - disable_irq(qproc->handover_irq);
> -
> - if (!qproc->proxy_unvoted) {
> + ret = qcom_q6v5_unprepare(&qproc->q6v5);
> + if (ret) {
> q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
>qproc-&
Hi Stephen,
On 5/31/2018 1:11 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-30 21:57:20)
>> Hi Stephen,
>>
>> On 5/30/2018 9:25 PM, Stephen Boyd wrote:
>>> Quoting Sricharan R (2018-05-24 22:40:11)
>>>> Hi Bjorn,
>>>>
>>>>
Hi Sibi,
On 6/1/2018 8:48 PM, Sibi S wrote:
> Hi Sricharan,
>
> On 06/01/2018 11:46 AM, Sricharan R wrote:
>> Hi Bjorn,
>> Thanks for this much needed consolidation.
>>
>> On 5/23/2018 10:50 AM, Bjorn Andersson wrote:
>>> Shared between all Hexagon V
Reviewed-by: Abhishek Sahu
Tested-by: Varadarajan Narayanan
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++
2 files changed, 20 insertions(+)
create mode 100644 arch/arm/boot/dts
Add serial, i2c, bam, spi, qpic peripheral nodes.
While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 12 ---
arch/arm64/boot/dts/qcom/ipq8074.dtsi
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 54 +++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
1 file changed, 156 insertions(+), 1 deletion
Add the common data for all dk07 based boards.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/boot/dts
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
2 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 112 insertions(+), 1 deletion(-)
create
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
arch/arm/boot/dts/qcom
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index
Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8
arch/arm/boot/dts/qcom-ipq4019.dtsi
dressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (12):
ARM: dts: ipq4
Hi Rob,
On 8/17/2018 8:39 PM, Rob Herring wrote:
> Hi, this email is from Rob's (experimental) review bot. I found a couple
> of common problems with your patch. Please see below.
>
> On Tue, 14 Aug 2018 17:42:32 +0530, Sricharan R wrote:
>> The kryo cpufreq driver reads
Hi Niklas,
On 10/22/2018 9:00 PM, Niklas Cassel wrote:
> On Mon, Oct 22, 2018 at 09:39:03AM +0530, Sricharan R wrote:
>> Hi Stephen,
>>
>> On 10/18/2018 1:46 AM, Stephen Boyd wrote:
>>> Quoting Stephen Boyd (2018-10-17 08:44:12)
>>>> Quoting Sricharan R
Hi Stephen,
On 10/18/2018 1:46 AM, Stephen Boyd wrote:
> Quoting Stephen Boyd (2018-10-17 08:44:12)
>> Quoting Sricharan R (2018-09-20 06:03:31)
>>>
>>>
>>> On 9/20/2018 1:54 AM, Craig wrote:
>>>> Yup, this patch seems to have fixed the hi
agon board eeprom client on i2c bus1
[V2] Addressed comments from Ivan T. Ivanov, Andy Gross
[v1] Initial Version
Andy Gross (1):
i2c: qup: Add V2 tags support
Sricharan R (5):
i2c: qup: Change qup_wait_writeready function to use for all timeouts
i2c: qup: Add bam dma capabilities
i2c: qup
qup_wait_writeready waits only on a output fifo empty event.
Change the same function to accept the event and data length
to wait as parameters. This way the same function can be used for
timeouts in otherplaces as well.
Signed-off-by: Sricharan R
---
drivers/i2c/busses/i2c-qup.c | 30
transfer more than 256 bytes,
without a 'stop' which is not possible otherwise.
Signed-off-by: Sricharan R
---
[v2] Addressed comments from Ivan T. Ivanov
drivers/i2c/busses/i2c-qup.c | 371 ++-
1 file changed, 366 insertions(+), 5 deletion
Signed-off-by: Sricharan R
---
[v2] Used macros for interrupts property.
arch/arm/boot/dts/qcom-msm8974.dtsi | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 2d11641..c2e8711 100644
Signed-off-by: Sricharan R
---
[v2] Changed dma channel names as per comments.
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index c2e8711..5cb0772 100644
--- a/arch/arm/boot
upport for the same.
For each block a data_write/read tag and data_len tag is added to
the output fifo. For the final block of data write_stop/read_stop
tag is used.
Signed-off-by: Andy Gross
Signed-off-by: Sricharan R
---
[v2] Addressed comments from Ivan T. Ivanov
drivers/i2c/busses/i2c-q
port for the same.
This is required for some clients like touchscreen which keeps
incrementing counts across individual transfers and 'STOP' bit inbetween
resets the counter, which is not required.
Signed-off-by: Sricharan R
---
drivers/i2c/busses/i2c-qup.c | 199 +
Hi Ivan,
On 04/14/2015 08:46 PM, Ivan T. Ivanov wrote:
Hi Sricharan,
On Sat, 2015-04-11 at 12:39 +0530, Sricharan R wrote:
From: Andy Gross
QUP from version 2.1.1 onwards, supports a new format of
i2c command tags. Tag codes instructs the controller to
perform a operation like read/write
Hi Ivan,
On 04/15/2015 02:19 PM, Ivan T. Ivanov wrote:
Hi Sricharan,
On Wed, 2015-04-15 at 12:09 +0530, Sricharan R wrote:
+/* frequency definitions for high speed and max speed */
+#define I2C_QUP_CLK_FAST_FREQ 100
This is fast mode, if I am not mistaken.
ya, up to 1MHZ
Hi Ivan,
Sorry resending again, because wrapping seemed to be
somehow wrong in my previous response.
On 04/15/2015 02:19 PM, Ivan T. Ivanov wrote:
Hi Sricharan,
On Wed, 2015-04-15 at 12:09 +0530, Sricharan R wrote:
+/* frequency definitions for high speed and max speed */
+#define
Hi Ivan,
On 04/16/2015 02:06 PM, Ivan T. Ivanov wrote:
Hi Sricharan,
On Wed, 2015-04-15 at 20:14 +0530, Sricharan R wrote:
+#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
Could you explain what is this for?
This is a new feature in the V2 version of the controller,
to
agon board eeprom client on i2c bus1
[V3] Added support to coalesce each i2c_msg in i2c_msgs for fifo and
block mode in Patch 2. Also addressed further code comments.
[V2] Addressed comments from Ivan T. Ivanov, Andy Gross [v1] Initial Version
Andy Gross (1):
i2c: qup: Add V2 tags support
Sric
qup_wait_writeready waits only on a output fifo empty event.
Change the same function to accept the event and data length
to wait as parameters. This way the same function can be used for
timeouts in otherplaces as well.
Signed-off-by: Sricharan R
---
[v3] Addressed comments from Andy Gross
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 2c26151..d741856 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index e265ec1..2c26151 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
upport for the same.
For each block a data_write/read tag and data_len tag is added to
the output fifo. For the final block of data write_stop/read_stop
tag is used.
Signed-off-by: Andy Gross
Signed-off-by: Sricharan R
---
[V3] Addressed comments from Andy Gross
to coalesce each i2c_msg i
port for the same.
This is required for some clients like touchscreen which keeps
incrementing counts across individual transfers and 'STOP' bit inbetween
resets the counter, which is not required.
Signed-off-by: Sricharan R
---
drivers/i2c/busses/i2c-qup.c | 200 +
transfer more than 256 bytes,
without a 'stop' which is not possible otherwise.
Signed-off-by: Sricharan R
---
[V3] Addressed comments from Andy Gross
to use macros for qup_i2c_wait_ready function.
drivers/i2c/busses/i2c-qup.c | 415 +
Hi,
On 04/12/2015 03:42 AM, Sergei Shtylyov wrote:
Hello.
On 04/11/2015 10:09 AM, Sricharan R wrote:
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b
Patch 'fix ARM_SMMU_FEAT_TRANS_OPS condition' changed the check
for ARM_SMMU_FEAT_TRANS_OPS to be based on presence of stage1 check,
but used (id & ID0_ATOSNS) instead of !(id & ID0_ATOSNS).
Fix it here.
Signed-off-by: Sricharan R
---
drivers/iommu/arm-smmu.c | 2 +-
1 file ch
Hi Vinod,
Thanks for the review.
On 5/18/2018 5:52 PM, Vinod wrote:
> On 14-05-18, 16:16, Sricharan R wrote:
>
>> +static int q6v5_reset(struct q6v5 *qproc)
>> +{
>> +u32 ret;
>> +int val, i;
>> +
>> +/* Assert resets, stop c
Hi,
On 5/18/2018 5:59 PM, Vinod wrote:
> On 14-05-18, 16:16, Sricharan R wrote:
>
>> +static int q6v5_wcss_start(struct rproc *rproc)
>> +{
>> +struct q6v5 *qproc = rproc->priv;
>> +int ret = 0;
>
> Superfluous initialization
>
ok.
>
operations ended
>> up being line wrapped and harder to read using some modify(reg, mask,
>> val) helper. That said, the function isn't very pretty in it's current
>> state either...
>
> Agreed :) and i thought modify make help it make better
>
>> One
Hi Gregory,
On 2/27/2018 8:28 PM, Gregory CLEMENT wrote:
> Hi Sricharan,
>
> On mar., févr. 27 2018, Sricharan R wrote:
>
>> From: Stephen Boyd
>>
>> Register a cpufreq-generic device whenever we detect that a
>> "qcom,krait" compatible CPU
Hi Viresh,
On 4/3/2018 9:53 AM, Viresh Kumar wrote:
> On 03-04-18, 08:11, Sricharan R wrote:
>> Right, i was adding a similar one for krait cores [1]. There is code common
>> in the
>> init sequence across both (little). Do you suggest to make them common ?
>
>
Hi Bjorn,
On 5/29/2018 9:37 AM, Bjorn Andersson wrote:
> On Wed 23 May 07:48 PDT 2018, Sricharan R wrote:
>> On 5/23/2018 1:07 PM, Vinod wrote:
>>> On 22-05-18, 23:58, Bjorn Andersson wrote:
>>>> On Tue 22 May 23:05 PDT 2018, Vinod wrote:
>>>>&
)
Signed-off-by: Sricharan R
[bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c]
Signed-off-by: Bjorn Andersson
---
Fixed review comments from Vinod.
Retained the reg read/update/write sequence instead of modify for
readability
In q6v5_wcss_powerdown SSCAON_CONFIG bits
Hi Vinod,
On 6/5/2018 11:49 AM, Vinod wrote:
> On 05-06-18, 11:12, Sricharan R wrote:
>
>> +config QCOM_Q6V5_WCSS
>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>> +depends on OF && ARCH_QCOM
>> +depend
Hi Vinod,
On 6/5/2018 10:10 PM, Vinod Koul wrote:
> On 05-06-18, 18:26, Sricharan R wrote:
>> Hi Vinod,
>>
>> On 6/5/2018 11:49 AM, Vinod wrote:
>>> On 05-06-18, 11:12, Sricharan R wrote:
>>>
>>>> +config QCOM_Q6V5_WCSS
>>>> +
Hi Vinod,
On 6/6/2018 12:19 PM, Vinod wrote:
> Hi Sricharan,
>
> On 06-06-18, 12:09, Sricharan R wrote:
>
>>>>>> +config QCOM_Q6V5_WCSS
>>>>>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>>>>>&
Hi Bjorn,
On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>
>> On 06-06-18, 09:17, Bjorn Andersson wrote:
>>> On Tue 05 Jun 05:56 PDT 2018, Sricharan R wrote:
>>>
>>>> Hi Vinod,
>>>>
>>&g
Hi Bjorn,
On 6/7/2018 11:18 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 22:29 PDT 2018, Sricharan R wrote:
>
>> Hi Bjorn,
>>
>> On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
>>> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
>>>
>>>> On 06-06-18, 0
is m and wcss
> is y. Why don't we see link fail for glink being n? Yes I understand that
> platform uses wcss but am curious how that works out :)
For glink being n, the stub functions gets linked, and not for glink=m.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus
Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8
arch/arm/boot/dts/qcom-ipq4019.dtsi
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
arch/arm/boot/dts/qcom
dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (12):
ARM: dts: ipq4019: Add a default chosen node
ARM: dts: ipq4
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 112 insertions(+), 1 deletion(-)
create
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
2 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a
Add serial, i2c, bam, spi, qpic peripheral nodes.
While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 156 +-
1 file changed
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
1 file changed, 156 insertions(+), 1 deletion
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 62 ++-
1 file changed, 52 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts
Reviewed-by: Abhishek Sahu
Acked-by: Bjorn Andersson
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/boot/dts
Add the common data for all dk07 based boards.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +
2 files changed, 65 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
Reviewed-by: Abhishek Sahu
Tested-by: Varadarajan Narayanan
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++
2 files changed, 20 insertions(+)
create mode 100644 arch/arm/boot/dts
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index
Hi Niklas,
On 4/4/2019 10:39 AM, Niklas Cassel wrote:
> From: Sricharan R
>
> The kryo cpufreq driver reads the nvmem cell and uses that data to
> populate the opps. There are other qcom cpufreq socs like krait which
> does similar thing. Except for the interpretation of the re
Hi Tony,
On Wednesday 05 February 2014 07:41 PM, Sricharan R wrote:
> Tony,
>
> On Wednesday 05 February 2014 06:41 PM, Sricharan R wrote:
>> On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
>>> On Mon, 3 Feb 2014, Sricharan R wrote:
>>>>> I al
only one
controller's input line. The crossbar device is used to map
a peripheral input to a free mpu's interrupt controller line.
Cc: Benoit Cousson
Cc: Santosh Shilimkar
Cc: Rajendra Nayak
Cc: Tony Lindgren
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/dra7.dtsi |8
x-omap/msg99540.html
Sricharan R (7):
DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
ARM: DTS: DRA: Add crossbar device binding
ARM: DTS: DRA: Replace peripheral interrupt numbers with crossbar
inputs
ARM: DTS: DRA
Enable the crossbar IP support for DRA7xx soc.
Cc: Santosh Shilimkar
Cc: Rajendra Nayak
Cc: Tony Lindgren
Signed-off-by: Sricharan R
---
arch/arm/mach-omap2/Kconfig|1 +
arch/arm/mach-omap2/omap4-common.c |4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach
t, so that it is setup to handle the
irqchip callbacks.
Cc: Thomas Gleixner
Cc: Linus Walleij
Cc: Santosh Shilimkar
Cc: Russell King
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Marc Zyngier
Cc: Grant Likely
Cc: Rob Herring
Signed-off-by: Sricharan R
Acked-by: Kumar Gala (for DT binding po
and wakeup gen code
cannot rely on these numbers to access the irq registers. Instead
use the hwirq element of the irq_data which represent the physical
irq number.
Cc: Santosh Shilimkar
Cc: Rajendra Nayak
Cc: Tony Lindgren
Signed-off-by: Sricharan R
---
arch/arm/mach-omap2/omap-wakeupgen.c
r
Cc: Rajendra Nayak
Cc: Tony Lindgren
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/dra7.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8b93b7a..fd58a09 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts
Cousson
Cc: Santosh Shilimkar
Cc: Rajendra Nayak
Cc: Tony Lindgren
Signed-off-by: Sricharan R
---
arch/arm/boot/dts/dra7.dtsi | 86 +--
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7
hould be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner
Cc: Linus Walleij
Cc: Santosh Shilimkar
Cc: Russell King
Cc: Tony Lindgren
Cc: Rajendra Nayak
Cc: Marc Zyngier
Cc: Grant Likely
Cc: Rob Herring
Signed-off-by: Sricharan R
---
[V2] Added de
5c3b0740fda4684dae4:
>>
>> ARM: DTS: DRA7: Add routable-irqs property for gic node (2014-03-03
>> 19:53:25 +0530)
>
> Thanks applying all except for the crossbar ones into
> omap-for-v3.15/dt.
>
> Please resend the last three patches once the dependencies
> are merged
sizeof(struct cb_device *), GFP_KERNEL);
> + cb = kzalloc(sizeof(*cb), GFP_KERNEL);
>
> if (!cb)
> return -ENOMEM;
Yes. correct. Thanks for the catch.
Acked-by: Sricharan R
Regards,
Sricharan
--
To unsubscribe from this list: send the line "unsubs
Hi Tony,
On Wednesday 08 January 2014 05:25 AM, Tony Lindgren wrote:
> * Tony Lindgren [140107 15:10]:
>> * Sricharan R [131229 22:30]:
>>> On Friday 27 December 2013 07:19 PM, Sricharan R wrote:
>>>> On Thursday 26 December 2013 11:14 PM, Santosh Shilimkar wrote:
Hi Rajendra,
On Tuesday 12 November 2013 11:11 AM, Rajendra Nayak wrote:
> On Tuesday 05 November 2013 06:44 PM, Sricharan R wrote:
>> Enable the crossbar IP support for DRA7xx soc.
>>
>> Cc: Santosh Shilimkar
>> Cc: Rajendra Nayak
>> Cc: Tony Lindgr
Hi Thomas,
On Tuesday 01 October 2013 08:37 PM, Santosh Shilimkar wrote:
> On Tuesday 01 October 2013 10:53 AM, Rob Herring wrote:
>> On 10/01/2013 08:57 AM, Santosh Shilimkar wrote:
>>> On Tuesday 01 October 2013 09:48 AM, Rob Herring wrote:
>>>> On 10/01/20
it updating the DRA7.dtsi file for adding the routable-irqs
property in to a separate patch
Previous discussions that led to this is at
https://lkml.org/lkml/2013/9/18/540
The V1 post of these patches is at
https://lkml.org/lkml/2013/9/30/283
Sricharan R (7):
DRIVERS: IRQCHIP:
301 - 400 of 985 matches
Mail list logo
