From: Jiaxun Yang
This yeeloong_laptop module enables access to sensors, battery,
video camera switch, external video connector event, and some
additional buttons.
This driver was orginally from linux-loongson-community. I Just do
some clean up and port to mainline kernel tree.
Signed-off-by
From: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/loongson.h | 6 ++
arch/mips/loongson64/common/cmdline.c| 7 +++
2 files changed, 13 insertions(+)
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h
b/arch/mips/include/asm
From: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/ec_kb3310b.h | 170 +++
arch/mips/loongson64/lemote-2f/ec_kb3310b.c| 2 +-
arch/mips/loongson64/lemote-2f/ec_kb3310b.h| 188 -
arch/mips/loongson64
From: Jiaxun Yang
Signed-off-by: Jiaxun Yang
---
arch/mips/loongson64/lemote-2f/Makefile | 2 +-
arch/mips/loongson64/lemote-2f/platform.c | 45 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/loongson64/lemote-2f/platform.c
To operate EC from platform driver, this head file need able to be include
from anywhere. This patch just move ec_kb3310b.h to include dir and
clean up ec_kb3310b.h.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/ec_kb3310b.h | 170 +++
arch/mips/loongson64
This patch just add pdev during boot to load the platform driver
Signed-off-by: Jiaxun Yang
---
arch/mips/loongson64/lemote-2f/Makefile | 2 +-
arch/mips/loongson64/lemote-2f/platform.c | 45 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644
-community. I Just do
some clean up and port to mainline kernel tree.
Signed-off-by: Jiaxun Yang
---
drivers/platform/mips/Kconfig | 18 +
drivers/platform/mips/Makefile |3 +
drivers/platform/mips/yeeloong_laptop.c | 1143 +++
3 files changed, 1164
Since lemote-2f/marchtype.c need to get cmdline from loongson.h
this patch simply copy kernel command line from arcs_cmdline
to fix that issue
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/loongson.h | 6 ++
arch/mips/loongson64/common/cmdline.c| 7
Since lemote-2f/marchtype.c need to get cmdline from loongson.h
this patch simply copy kernel command line from arcs_cmdline
to fix that issue.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/loongson.h | 6 ++
arch/mips/loongson64/common/cmdline.c| 7
-community. I Just do
some clean up and port to mainline kernel tree.
Signed-off-by: Jiaxun Yang
---
drivers/platform/mips/Kconfig | 19 +
drivers/platform/mips/Makefile |3 +
drivers/platform/mips/yeeloong_laptop.c | 1142 +++
3 files changed, 1164
This patch just add pdev during boot to load the platform driver
Signed-off-by: Jiaxun Yang
---
arch/mips/loongson64/lemote-2f/Makefile | 2 +-
arch/mips/loongson64/lemote-2f/platform.c | 27 +++
2 files changed, 28 insertions(+), 1 deletion(-)
create mode 100644
To operate EC from platform driver, this head file need able to be include
from anywhere. This patch just move ec_kb3310b.h to include dir and
clean up ec_kb3310b.h.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/ec_kb3310b.h | 170 +++
arch/mips/loongson64
t you know that we have a problem here.
--
Jiaxun Yang
signature.asc
Description: This is a digitally signed message part
ir b) $ cd c) $ wget
> http://git.ingenic.cn:8082/bj/repo d) $ chmod +x repo
>
Repo is a sourcecode managing system used by Android. The gerrit is
still here but need extra premission to reach. Now ingenic release
there soucecode by "Baidu Netdisk". It's hard to access by foreign
users. So we put the shourcecode here: https://github.com/Ingenic-commu
nity/linux-xburst-bsp
Thanks
--
Jiaxun Yang
ag interface with standard MIPS cores, maybe we need some
modification on openocd). So maybe I can help in testing this after I
get my broad. Just ask if you need any help.
Thanks
--
Jiaxun Yang
在 2018-03-07三的 20:35 +0530，PrasannaKumar Muralidharan写道：
> Hi James,
>
> Seems Jiaxun is interested in the board and is willing to help.
>
> I have been told that Ingenic is focusing on IoT market and X1000 is
> intended for IoT segment. I think that they would be selling several
> 100Ks of chip
has_cpu_mips*_user to decide witch level should be
displayed in cpuinfo to prevent misleading userspace programs.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/cpu-features.h | 39
arch/mips/kernel/proc.c | 22 ++--
2 files changed
All loongson-3 processors support mips64r2 usermode instructions.
However 3A1000 3B1000 3B1500 should be treated as mips64r1 in kernel.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips
has_cpu_mips*_user to decide which level should be
displayed in cpuinfo to prevent misleading userspace programs.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/cpu-features.h | 39
arch/mips/kernel/proc.c | 22 ++--
2 files changed
All loongson-3 processors support mips32r2 mips64r2 usermode instructions.
However 3A1000 3B1000 3B1500 should be treated as r1 in kernel.
Signed-off-by: Jiaxun Yang
---
arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips
在 2018-03-22四的 22:21 +，James Hogan写道：
> On Fri, Mar 16, 2018 at 03:55:16PM +0800, Huacai Chen wrote:
> > diff --git a/arch/mips/boot/compressed/decompress.c
> > b/arch/mips/boot/compressed/decompress.c
> > index fdf99e9..5ba431c 100644
> > --- a/arch/mips/boot/compressed/decompress.c
> > +++ b/
0f10 and should have
CPB feature according AMD product specifications, however
their Fn8000_0007_EDX is 0x6599, indicating they don't
support CPB feature.
Since whole F17h should support CPB, we set the cap for all of
them.
Cc: sta...@vger.kernel.org
Signed-off-by: Jiaxun Yang
---
arch
x00810f10 and should have
CPB feature according AMD product specifications, however
their Fn8000_0007_EDX is 0x6599, indicating they don't
support CPB feature.
Signed-off-by: Jiaxun Yang
---
arch/x86/kernel/cpu/amd.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --
specific
WRITE_ONCE looks more reasonable, because it the eliminate the "non-cohrency".
So we can solve the bug from the root.
Thanks.
--
Jiaxun Yang
在2024年2月26日二月 上午8:04，maobibo写道：
> On 2024/2/26 下午2:12, Huacai Chen wrote:
>> On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
>>>
>>>
>>>
>>> On 2024/2/24 下午5:13, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> Instruction cpucfg can be u
在2024年2月27日二月 上午3:14，maobibo写道：
> On 2024/2/27 上午4:02, Jiaxun Yang wrote:
>>
>>
>> 在2024年2月26日二月 上午8:04，maobibo写道：
>>> On 2024/2/26 下午2:12, Huacai Chen wrote:
>>>> On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
>>>>>
>>>>
oport (Microsoft)
Reviewed-by: Jiaxun Yang
MIPS should go arch_numa at some point as well.
Thanks
- Jiaxun
> ---
> arch/mips/include/asm/mach-loongson64/mmzone.h | 4 ++--
> arch/mips/loongson64/numa.c| 8
> 2 files changed, 6 insertions(+), 6 deletion
Hi
More works should be done after rework on clk and other drivers
accepted.
Thanks.
Loongson-1B&C have totally identical GS232 core, so merge
them into same CPU config.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig| 38 +---
arch/mips/include/asm/cpu-type.h | 3 +--
arch/mips/loongson32/Kconfig | 4 ++--
3 files changed
It's going to be enabled by DeviceTree
Signed-off-by: Jiaxun Yang
---
.../include/asm/mach-loongson32/platform.h| 1 -
arch/mips/loongson32/common/platform.c| 30 ---
arch/mips/loongson32/ls1b/board.c | 1 -
3 files changed, 32 deletions(-)
diff
Initial DeviceTree support for loongson32
Also remove the old IRQ driver since it have been replaced
by generic LS1X_IRQ.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig| 5 +-
arch/mips/loongson32/common/Makefile | 2 +-
arch/mips/loongson32/common/irq.c| 196
Add devicetree skeleton for ls1b and ls1c
Signed-off-by: Jiaxun Yang
---
arch/mips/boot/dts/loongson/Makefile | 6 ++
arch/mips/boot/dts/loongson/ls1b.dts | 21 +
arch/mips/boot/dts/loongson/ls1c.dts | 25 ++
arch/mips/boot/dts/loongson/ls1x.dtsi | 117
Hi Rob,
Thanks for your reply, I have some questions on that:
在 2019/3/12 下午8:28, Rob Herring 写道:
On Tue, Mar 12, 2019 at 4:16 AM Jiaxun Yang wrote:
Add devicetree skeleton for ls1b and ls1c
Signed-off-by: Jiaxun Yang
---
+/ {
+ model = "Loongson LS1B";
+
This patch add of support by split the clk_hw register and
clkdev register, then handle the of clk_hw via
of_clk_hw_onecell_get.
Signed-off-by: Jiaxun Yang
---
drivers/clk/loongson1/clk-loongson1b.c | 176 +++--
drivers/clk/loongson1/clk-loongson1c.c | 144
The patch introduces options for loongson1 clocks so we can
select the driver we need.
Signed-off-by: Jiaxun Yang
---
drivers/clk/Kconfig| 1 +
drivers/clk/Makefile | 2 +-
drivers/clk/loongson1/Kconfig | 27 +++
drivers/clk/loongson1/Makefile
Add of support for ls1c-clock and ls1b-clock
Loongson-1 is a series of MIPS MCUs.
This patch add the clock bindings for loongson-1b and
loongson-1c clock subsystem.
Signed-off-by: Jiaxun Yang
---
.../bindings/clock/loongson1-clock.txt| 11 ++
include/dt-bindings/clock/ls1b-clock.h| 20 +++
include
v1->v2: Fix SPDX-License-Identifier
v2->v3: Rework according suggestions from Marc Zyngier, Thanks.
v3->v4: Rework the driver into a single chip driver.
This controller appeared on Loongson-1 family MCUs
including Loongson-1B and Loongson-1C.
Signed-off-by: Jiaxun Yang
---
drivers/irqchip/Kconfig| 9 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ls1x.c | 196 +
3 files changed, 206
Dt-bindings doc about Loongson-1 interrupt controller.
Signed-off-by: Jiaxun Yang
---
.../loongson,ls1x-intc.txt| 24 +++
1 file changed, 24 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt
diff
Add of support for ls1c-clock and ls1b-clock
v2: Move of declear into per clk file
The patch introduces options for loongson1 clocks so we can
select the driver we need.
Signed-off-by: Jiaxun Yang
---
drivers/clk/Kconfig| 1 +
drivers/clk/Makefile | 2 +-
drivers/clk/loongson1/Kconfig | 27 +++
drivers/clk/loongson1/Makefile
This patch add of support by split the clk_hw register and
clkdev register, then handle the of clk_hw via
of_clk_hw_onecell_get.
Signed-off-by: Jiaxun Yang
---
drivers/clk/loongson1/clk-loongson1b.c | 197 -
drivers/clk/loongson1/clk-loongson1c.c | 164
Loongson-1 is a series of MIPS MCUs.
This patch add the clock bindings for loongson-1b and
loongson-1c clock subsystem.
Signed-off-by: Jiaxun Yang
---
.../bindings/clock/loongson1-clock.txt| 11 ++
include/dt-bindings/clock/ls1b-clock.h| 20 +++
include
On Wed, Feb 24, 2021, at 9:02 PM, Jinyang He wrote:
> detect_memory_region() was committed by Commit 4d9f77d25268 ("MIPS: add
> detect_memory_region()"). Then it was equipped by Commit dd63b00804a5
> ("MIPS: ralink: make use of the new memory detection code") and
> Commit 9b75733b7b5e ("MIPS: at
iointc1 node.
>
> Signed-off-by: Jiaxun Yang
> Signed-off-by: Qing Zhang
> Signed-off-by: Xingxing Su
You should document dt binding changes.
Thanks
- Jiaxun
> ---
> drivers/irqchip/irq-loongson-liointc.c | 55 +-
> 1 file changed, 46 insertions(+), 9 delet
On Tue, Feb 9, 2021, at 5:32 PM, Qing Zhang wrote:
> Distinguish between 3A series CPU and 2K1000 CPU UART0.
>
> Signed-off-by: Jiaxun Yang
> Signed-off-by: Qing Zhang
> Signed-off-by: Xingxing Su
Personally I don't like this kind of quirk.
Probably we should use e
On Sun, Jan 31, 2021, at 4:14 PM, Jinyang He wrote:
> CONFIG_64BIT is confusing. N32 also pass parameters by a0~a7.
Do we have NEW kernel build?
CONFIG_64BIT assumed N64 as kernel ABI.
-Jiaxun
>
> Signed-off-by: Jinyang He
> ---
> arch/mips/kernel/mcount.S | 4 ++--
> 1 file changed, 2 in
On Mon, Feb 1, 2021, at 9:12 AM, Jinyang He wrote:
> On 01/31/2021 06:38 PM, Jiaxun Yang wrote:
>
> >
> > On Sun, Jan 31, 2021, at 4:14 PM, Jinyang He wrote:
> >> CONFIG_64BIT is confusing. N32 also pass parameters by a0~a7.
> > Do we have NEW kernel build
On Mon, Feb 8, 2021, at 9:14 PM, Tiezhu Yang wrote:
> According to MIPS EJTAG Specification [1], a Debug Breakpoint
> exception occurs when an SDBBP instruction is executed, the
> CP0_DEBUG bit DBp indicates that a Debug Breakpoint exception
> occurred, just check bit DBp for SDBBP is more accur
On Tue, Feb 9, 2021, at 12:32 AM, Jiaxun Yang wrote:
>
>
> On Mon, Feb 8, 2021, at 9:14 PM, Tiezhu Yang wrote:
> > According to MIPS EJTAG Specification [1], a Debug Breakpoint
> > exception occurs when an SDBBP instruction is executed, the
> > CP0_DEBUG bit
在 2021/2/26 上午9:37, Jinyang He 写道:
On 02/24/2021 11:40 PM, Jiaxun Yang wrote:
On Wed, Feb 24, 2021, at 9:02 PM, Jinyang He wrote:
detect_memory_region() was committed by Commit 4d9f77d25268 ("MIPS: add
detect_memory_region()"). Then it was equipped by Commit dd63b00804a5
("MIP
+ compatible = "pci0014,7a24.0",
Just wonder if using such compatible string is allowed?
I've saw some some usages like mine in the tree, such as
arch/x86/platform/ce4100/falconfalls.dts, and
arch/mips/boot/dts/img/boston.dts.
If that's allowed, should we surpress these warnings in checkpatch
script?
Thanks.
--
Jiaxun Yang
Jiaxun Yang (2):
irqchip: loongson-pci-msi: Fix a typo in Kconfig
irqchip: loongson-*: Fix COMPILE_TEST
drivers/irqchip/Kconfig| 2 +-
drivers/irqchip/irq-loongson-htpic.c | 4
drivers/irqchip/irq-loongson-htvec.c | 4
drivers/irqchip/irq-loongson-liointc.c
spurious_interrupt helper only exists on MIPS and x86,
so define a dummy function on other architectures to fix
COMPILE_TEST.
Reported-by: kbuild test robot
Signed-off-by: Jiaxun Yang
---
drivers/irqchip/irq-loongson-htpic.c | 4
drivers/irqchip/irq-loongson-htvec.c | 4
drivers
PCH MSI driver's tittle was wrong.
My stupid mistake.
Fixes: cca8fbff2585 ("irqchip: Add Loongson PCH MSI controller")
Signed-off-by: Jiaxun Yang
---
drivers/irqchip/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/
After 2f96593ecc37 ("of_address: Add bus type match for pci ranges parser"),
the last user of of_bus_pci_get_flags when CONFIG_PCI is disabled had gone.
This caused unused function warning when compiling without CONFIG_PCI.
Fix by guarding it with CONFIG_PCI.
Signed-off-by: Jiaxun Yang
在 2020/7/29 下午6:31, Stephen Rothwell 写道:
Hi all,
After merging the mips tree, today's linux-next build (powerpc
allnoconfig) produced this warning:
drivers/of/address.c:104:21: warning: 'of_bus_pci_get_flags' defined but not
used [-Wunused-function]
104 | static unsigned int of_bus_pci_g
在 2020/7/30 上午9:40, Stephen Rothwell 写道:
Hi Jiaxun,
On Thu, 30 Jul 2020 09:04:40 +0800 Jiaxun Yang wrote:
Btw: Neither James nor Ralf is still active at Linux-MIPS.
Interesting. I have just them listed as my contacts for MIPS. Should
I change to just Thomes (Thomas Bogendoerfer
)?
Yes
Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig| 21 +
arch/mips/kernel/cpu-probe.c | 12 +++-
2 files changed, 32
Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
---
arch/mips/Kconfig| 21 +
arch/mips/kernel/cpu-probe.c | 12 +++-
2 files changed, 32
在 2020/7/31 下午12:24, Florian Fainelli 写道:
Disable pref 30 by utilizing the standard quirk method and matching the
affected SoCs: 7344, 7346, 7425.
Signed-off-by: Florian Fainelli
---
arch/mips/bmips/setup.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/mips/b
于 2020年5月13日 GMT+08:00 下午8:15:40, Thomas Gleixner 写到:
>Thomas Gleixner writes:
>> Jiaxun Yang writes:
>>> +
>>> +struct pch_msi_data {
>>> + spinlock_t msi_map_lock;
>>> + phys_addr_t doorbell;
>>> + u32
于 2020年5月14日 GMT+08:00 下午9:16:38, Jiaxun Yang 写到:
>This controller can be found on Loongson-2K SoC, Loongson-3
>systems with RS780E/LS7A PCH.
>
>The RS780E part of code was previously located at
>arch/mips/pci/ops-loongson3.c and now it can use generic PCI
>driver implementat
ou can pick it for now.
[...]
[1]: https://lkml.org/lkml/2020/4/11/1088
--
Jiaxun Yang
在 2020/8/11 下午5:31, Xingxing Su 写道:
Commit c34b26b98caca48ec9ee9 ("KVM: MIPS: clean up redundant 'kvm_run'
parameters") remove the 'kvm_run' parameter in kvm_vz_gpsi_lwc2.
The following build error:
arch/mips/kvm/vz.c: In function ‘kvm_trap_vz_handle_gpsi’:
arch/mips/kvm/vz.c:1243:43: error:
在 2020/8/11 下午10:37, Jiaxun Yang 写道:
在 2020/8/11 下午5:31, Xingxing Su 写道:
Commit c34b26b98caca48ec9ee9 ("KVM: MIPS: clean up redundant 'kvm_run'
parameters") remove the 'kvm_run' parameter in kvm_vz_gpsi_lwc2.
The following build error:
a
Requested by downstream distros, a Kconfig option for default
IEEE 754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
Reviewed-by: WANG Xuerui
Reviewed-by: Serge Semin
Reviewed-by: Huacai Chen
--
v2: Reword according to Xuerui's sugge
在 2020/8/3 上午5:46, Maciej W. Rozycki 写道:
On Fri, 31 Jul 2020, Serge Semin wrote:
Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.
That's what should have been here in the first place. Thanks!
Well,
This is causing lscpu segfault. So probably worthy to
include it as a part of mips-fixes.
Jiaxun Yang (2):
MIPS: cacheinfo: Add missing VCache
MIPS: Loongson64: Set cluster for cores
arch/mips/kernel/cacheinfo.c | 34 ++
arch/mips/loongson64/smp.c | 2
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang
---
arch/mips/kernel/cacheinfo.c | 34 ++
1 file changed, 26 insertions(+), 8
在 2020/8/1 14:11, Jiaxun Yang 写道:
Requested by downstream distros, a Kconfig option for default
IEEE 754 conformance mode allows them to set their mode to
relaxed by default.
Signed-off-by: Jiaxun Yang
Reviewed-by: WANG Xuerui
Reviewed-by: Serge Semin
Reviewed-by: Huacai Chen
--
v2
在 2020/8/6 下午3:09, Tiezhu Yang 写道:
Loongson processors have a writecombine issue that maybe failed to
write back framebuffer used with ATI Radeon or AMD GPU at times,
after commit 8a08e50cee66 ("drm: Permit video-buffers writecombine
mapping for MIPS"), there exists some errors such as blurred
在 2020/8/6 下午6:17, Thomas Bogendoerfer 写道:
On Thu, Aug 06, 2020 at 04:32:13PM +0800, Tiezhu Yang wrote:
On 08/06/2020 03:39 PM, Jiaxun Yang wrote:
在 2020/8/6 下午3:09, Tiezhu Yang 写道:
Loongson processors have a writecombine issue that maybe failed to
write back framebuffer used with ATI
在 2020/8/7 上午12:52, Thomas Bogendoerfer 写道:
On Thu, Aug 06, 2020 at 07:56:20PM +0800, Jiaxun Yang wrote:
Our current problem is Loongson's writecombine implementation seems buggy.
This is our platform issue rather than target hardware issue.
ok, so simply clear cpu_data[0].writecombin
在 2020/8/7 下午5:38, Álvaro Fernández Rojas 写道:
Current board declarations are a mess. Let's put some order and make them
follow the same structure.
Also remove board declarations tabs and double whitespace in the header.
Signed-off-by: Álvaro Fernández Rojas
---
arch/mips/bcm63xx/boards/boa
在 2020/8/8 上午12:45, Paul Cercueil 写道:
Hi Zhou,
Le sam. 8 août 2020 à 0:23, Zhou Yanjie a
écrit :
Hi Paul,
I'm not too sure if remove "cpu-feature-overrides.h" will cause some
problems for X2000, because according to my current test on X2000, I
found that it is somewhat different from th
Do not override ejtag feature to 0 as Loongson 3A1000+ do have ejtag.
For watch, as KVM emulated CPU doesn't have watch feature, we should
not enable it unconditionally.
Signed-off-by: Jiaxun Yang
---
This patch should go into mips-fixes tree as watch feature is blocking
KVM guest boot in
在 2020/8/8 下午9:41, Thomas Bogendoerfer 写道:
On Sat, Aug 08, 2020 at 03:25:02PM +0800, Tiezhu Yang wrote:
Loongson processors have a writecombine issue that maybe failed to
write back framebuffer used with ATI Radeon or AMD GPU at times,
after commit 8a08e50cee66 ("drm: Permit video-buffers wri
kvm/emulate.c:1939:2: note: here
1939 | case lw_op:
Just fix it.
Signed-off-by: Jiaxun Yang
Reviewed-by: Huacai Chen
---
This is blocking KVM MIPS from build, so it needs to get into 5.9.
---
arch/mips/kvm/emulate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/m
.cprestore is removed as we don't except Position Independent
zboot ELF.
.noreorder is also removed and rest instructions is massaged
to improve readability.
t9 register is used to indirect jump as MIPS ABI requirement.
Reported-by: Paul Cercueil
Signed-off-by: Jiaxun Yang
---
arch/mips
On Mon, Dec 21, 2020, at 10:09 PM, Paul Cercueil wrote:
> Hi Jiaxun,
>
> Le lun. 21 déc. 2020 à 21:00, Jiaxun Yang a
> écrit :
> > .cprestore is removed as we don't except Position Independent
> > zboot ELF.
> >
> > .noreorder is also removed and res
在 2020/12/8 15:44, Qing Zhang 写道:
Add spi-ls7a binding documentation.
Signed-off-by: Qing Zhang
---
Documentation/devicetree/bindings/spi/spi-ls7a.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-ls7a.txt
Hi
在 2020/12/8 15:44, Qing Zhang 写道:
add spi and amd node support.
Hi Qing,
Thanks for your patch.
What is AMD node?
Also given that different boards may have different flash, is it a wise
idea to hardcode here?
Thanks.
- Jiaxun
Signed-off-by: Qing Zhang
---
v2:
- Add spi about pci
machines.
Signed-off-by: Jiaxun Yang
Cc: sta...@vger.kernel.org # 5.4+
--
v2: Specify touchpad to ELAN0634
v3: Stupid missing ! in v2
v4: Correct acpi_dev_present usage (Hans)
---
drivers/platform/x86/ideapad-laptop.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a
Paul Cercueil
Signed-off-by: Jiaxun Yang
--
v2: Remove start label (paul)
---
arch/mips/boot/compressed/head.S | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 409cb483a9ff..977218c
n-and-side-channel-vulnerabilities/
Signed-off-by: Jiaxun Yang
---
arch/mips/kernel/cpu-probe.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 03adeed58efb..2460783dbdb1 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch
Add infrastructure to display CPU vulnerabilities.
As most MIPS CPU vendors are dead today and we can't confirm
vulnerabilities states with them, we'll display vulnerabilities
as "Unknown" by default and override them in cpu-probe.c
Signed-off-by: Jiaxun Yang
--
Loongson64C is known to be vulnerable to meltdown according to
PoC from Rui Wang .
Loongson64G defended these side-channel attack by silicon.
Signed-off-by: Jiaxun Yang
---
arch/mips/kernel/cpu-probe.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch
Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.
Signed-off-by: Jiaxun Yang
Reviewed-by: Tiezhu Yang
Tested-by: Tiezhu Yang
---
arch/mips/kernel/cacheinfo.c | 34
cluster is required for cacheinfo to set shared_cpu_map correctly.
Signed-off-by: Jiaxun Yang
Reviewed-by: Tiezhu Yang
Tested-by: Tiezhu Yang
---
arch/mips/loongson64/smp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index
在 2020/12/30 上午11:08, Jiaxun Yang 写道:
.cprestore is removed as we don't expect Position Independent
zboot ELF.
.noreorder is also removed and rest instructions are massaged
to improve readability.
t9 register is used for indirect jump as MIPS ABI requirement.
start label is removed
Paul Cercueil
Signed-off-by: Jiaxun Yang
--
v2: Remove start label (paul)
---
arch/mips/boot/compressed/head.S | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 409cb483a9ff..070b2fb
在 2020/12/31 23:43, WANG Xuerui 写道:
Hi Jiaxun,
On 12/30/20 11:23 AM, Jiaxun Yang wrote:
Loongson64C is known to be vulnerable to meltdown according to
PoC from Rui Wang .
Loongson64G defended these side-channel attack by silicon.
"Loongson64G mitigated it in hardware"?
Sig
在 2020/12/31 23:38, WANG Xuerui 写道:
Hi Jiaxun,
Overall a nice step towards a more conformant arch/mips! Some nits
below though.
On 12/30/20 11:23 AM, Jiaxun Yang wrote:
Add infrastructure to display CPU vulnerabilities.
As most MIPS CPU vendors are dead today and we can't co
在 2020/12/25 下午6:35, Qing Zhang 写道:
Switch the DT binding to a YAML schema to enable the DT validation.
Signed-off-by: Qing Zhang
---
v4: fix warnings/errors about running 'make dt_binding_check'
---
.../devicetree/bindings/spi/loongson,spi-ls7a.yaml | 46 ++
1 file cha
在 2021/3/5 上午7:08, Maciej W. Rozycki 写道:
On Thu, 4 Mar 2021, Tiezhu Yang wrote:
This is a known bug [2] with Clang, as Simon Atanasyan said,
"There is no plan on support O32 for MIPS64 due to lack of
resources".
Huh? Is that a joke? From the o32 psABI's point of view a MIPS64 CPU is
ex
在 2021/3/4 下午7:00, Qing Zhang 写道:
We don't need them anymore, They are uniform on all Loongson64 systems
and have been fixed in DeviceTree.loongson3_platform_init is replaced
with DTS + driver.
Signed-off-by: Jiaxun Yang
Signed-off-by: Qing Zhang
Acked-by: Jiaxun Yang
Hmm, why it
在 2021/3/4 下午7:00, Qing Zhang 写道:
The purpose of separating loongson_system_configuration from boot_param.h
is to keep the other structure consistent with the firmware.
Signed-off-by: Jiaxun Yang
Signed-off-by: Qing Zhang
Acked-by: Jiaxun Yang
- Jiaxun
---
.../include/asm/mach
在 2021/3/5 11:12, HongJieDeng 写道:
From: Hongjie Deng
We need more stack space, xori/ori no longer apply when
_THREAD_MASK exceeds 16 bits
Signed-off-by: Hongjie Deng
---
arch/mips/include/asm/stackframe.h | 8
arch/mips/kernel/genex.S | 6 ++
2 files changed, 1
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