Hi Marc,
> On 10/9/19 6:01 AM, Appana Durga Kedareswara Rao wrote:
> > Hi,
> >
> >
> >> On 18.3.2019 13.32, Appana Durga Kedareswara rao wrote:
> >>> AXI CAN IP and CANPS IP supports tx fifo empty feature, this patch
> >>> updates the flags
AXI CANIP doesn't support tx fifo empty interrupt feature(TXFEMP),
update the flags filed in the driver for AXI CAN case accordingly.
Fixes: 3281b380ec9f ("can: xilinx_can: Fix flags field initialization for axi
can and canps")
Reported-by: Anssi Hannula
Signed-off-by: Appana Durga K
Hi,
> On 18.3.2019 13.32, Appana Durga Kedareswara rao wrote:
> > AXI CAN IP and CANPS IP supports tx fifo empty feature, this patch
> > updates the flags field for the same.
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> >
> > ---
> > dr
Hi Alan,
Did you get a chance to send your framework changes to upstream?
@Moritz Fischer: If Alan couldn't send his patch series, Can we take this patch
series??
Please let me know your thoughts on this.
Regards,
Kedar.
> On Fri, Jul 27, 2018 at 1:22 AM, Appana Durga Kedareswara rao
>
n the case of deferred probe.
Fixes: b1201e44 ("can: xilinx CAN controller support")
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Venkatesh Yadav Abbarapu
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 3 ++-
1 file changed, 2 insertions(+), 1 del
ti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 29 -
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index 2d3399e..c9b951b
From: Srinivas Neeli
While calculating bitrate for the data phase, the driver is using phase
segment 1 of the arbitration phase instead of the data phase.
Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames")
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by
For CANFD 2.0 IP configuration existing driver is using incorrect mask
values for FSR register FL and RI fields.
Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames")
Signed-off-by: Appana Durga Kedareswara rao
Acked-by: Shubhrajyoti Datta
Signed-off-by: Michal Simek
--
essary fsr register checks in
xcanfd_rx() API.
Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames")
Reviewed-by: Radhey Shyam Pandey
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Michal Simek
---
drivers/net/ca
g in the commit description
Appana Durga Kedareswara rao (3):
can: xilinx_can: Fix FSR register handling in the rx path
can: xilinx_can: Fix the data updation logic for CANFD FD frames
can: xilinx_can: Fix FSR register FL and RI mask values for canfd 2.0
Srinivas Neeli (1):
can: xilinx_can: Fix
Hi Marc,
Thanks for the review.
> On 8/12/19 9:28 AM, Appana Durga Kedareswara rao wrote:
> > This patch series fixes below issues
> > --> Bugs in the driver w.r.to CANFD 2.0 IP support Defer the probe if
> > --> clock is not found
> >
> > Appa
Hi Marc,
Thanks for the review...
> On 8/12/19 9:28 AM, Appana Durga Kedareswara rao wrote:
> > From: Venkatesh Yadav Abbarapu
> >
> > It's not always the case that clock is already available when can
> > driver get probed at the first time, e.g. the clock is p
From: Venkatesh Yadav Abbarapu
It's not always the case that clock is already available when can
driver get probed at the first time, e.g. the clock is provided by
clock wizard which may be probed after can driver. So let's defer
the probe when devm_clk_get() call fails and give it chance to
try
commit c223da689324 ("can: xilinx_can: Add support for CANFD FD frames")
is writing data to a wrong offset for FD frames.
This patch fixes this issue.
Reviewed-by: Radhey Shyam Pandey
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Mi
essary fsr register checks in
xcanfd_rx() API.
Reviewed-by: Radhey Shyam Pandey
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 139 ---
1 file changed, 63 inserti
From: Srinivas Neeli
While calculating bitrate for the data phase, the driver is using phase
segment 1 of the arbitration phase instead of the data phase.
Signed-off-by: Srinivas Neeli
Acked-by: Shubhrajyoti Datta
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 2 +-
1 file
For CANFD 2.0 IP configuration existing driver is using incorrect mask
values for FSR register FL and RI fields.
Signed-off-by: Appana Durga Kedareswara rao
Acked-by: Shubhrajyoti Datta
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 13 ++---
1 file changed, 10
This patch series fixes below issues
--> Bugs in the driver w.r.to CANFD 2.0 IP support
--> Defer the probe if clock is not found
Appana Durga Kedareswara rao (3):
can: xilinx_can: Fix FSR register handling in the rx path
can: xilinx_can: Fix the data updation logic for CANFD FD frames
Hi Marc,
Friendly ping !!
> -Original Message-
> From: Appana Durga Kedareswara Rao
> Sent: Tuesday, April 23, 2019 12:08 PM
> To: 'Marc Kleine-Budde' ; 'w...@grandegger.com'
> ; 'da...@davemloft.net' ;
> Michal Simek
> Cc: 'linux-...@vger.kernel.org' ;
>
Hi Andre,
>
> On 3/9/19 3:07 PM, Appana Durga Kedareswara rao wrote:
> > While stress testing the CAN interface on xilinx axi can in loopback
> > mode getting message "write: no buffer space available"
> > Increasing device tx queue length resolved the a
While stress testing the CAN interface on xilinx axi can
in loopback mode getting message "write: no buffer space available"
Increasing device tx queue length resolved the above mentioned issue.
Signed-off-by: Appana Durga Kedareswara rao
---
--> Network devices default tx_queu
> -Original Message-
> From: Radhey Shyam Pandey
> Sent: Saturday, September 29, 2018 10:48 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ; Radhey Shyam Pandey
> Cc: dmaeng...@vger.kernel.org; linux-arm-ker..
> -Original Message-
> From: Radhey Shyam Pandey
> Sent: Saturday, September 29, 2018 10:48 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ; Radhey Shyam Pandey
> Cc: dmaeng...@vger.kernel.org; linux-arm-ker..
Pandey
Reviewed-by: Appana Durga Kedareswara Rao
Regards,
Kedar.
> ---
> Changes for v2:
> New patch- Preparatory change for 4/4 fix.
> ---
> drivers/dma/xilinx/xilinx_dma.c |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xili
Pandey
Reviewed-by: Appana Durga Kedareswara Rao
Regards,
Kedar.
> ---
> Changes for v2:
> New patch- Preparatory change for 4/4 fix.
> ---
> drivers/dma/xilinx/xilinx_dma.c |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xili
Hi,
Thanks for the patch...
>
> In axidma alloc_chan_resources merge BD and cyclic BD allocation.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
Acked-for-series: Appana Durga Kedareswara rao
Regards,
Kedar.
> ---
> drivers/dma/xilin
Hi,
Thanks for the patch...
>
> In axidma alloc_chan_resources merge BD and cyclic BD allocation.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
Acked-for-series: Appana Durga Kedareswara rao
Regards,
Kedar.
> ---
> drivers/dma/xilin
Hi Alan,
Thanks for the review...
> On Fri, Jul 27, 2018 at 1:22 AM, Appana Durga Kedareswara rao
> wrote:
>
> Hi Appana,
>
> There should be some documentation for the debugfs added under
> Documentation/driver-api/fpga/
>
> Also there are a lot of
Hi Alan,
Thanks for the review...
> On Fri, Jul 27, 2018 at 1:22 AM, Appana Durga Kedareswara rao
> wrote:
>
> Hi Appana,
>
> There should be some documentation for the debugfs added under
> Documentation/driver-api/fpga/
>
> Also there are a lot of
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara
This patch adds support for readback of FPGA configuration data and registers.
Usage:
Readback of PL configuration data
cat /sys/kernel/debug/fpga/fpga0/image
Readback of PL configuration registers
cat /sys/kernel/debug/fpga/f8007000.devcfg/cfg_reg
Signed-off-by: Appana Durga
This patch adds support for readback of FPGA configuration data and registers.
Usage:
Readback of PL configuration data
cat /sys/kernel/debug/fpga/fpga0/image
Readback of PL configuration registers
cat /sys/kernel/debug/fpga/f8007000.devcfg/cfg_reg
Signed-off-by: Appana Durga
Hi Alan,
Thanks for the review...
> > In Zynq Case it supports two types of the readback (Configuration registers,
> Configuration data(fpga image)) which may not be the same case for other
> vendors.
> > Since I need to support both the use cases I have differentiated them using
>
Hi Alan,
Thanks for the review...
> > In Zynq Case it supports two types of the readback (Configuration registers,
> Configuration data(fpga image)) which may not be the same case for other
> vendors.
> > Since I need to support both the use cases I have differentiated them using
>
Hi Alan,
Thanks for the review...
> Another minor thing.
>
> > +
> >
> +/**
> **
> > +/
>
> Let's keep the coding style consistent by not having
Sure will fix in v4...
> '***'
>
> >
Hi Alan,
Thanks for the review...
> Another minor thing.
>
> > +
> >
> +/**
> **
> > +/
>
> Let's keep the coding style consistent by not having
Sure will fix in v4...
> '***'
>
> >
Hi Alan,
Thanks for the review...
> >
> >
> >> > +static bool readback_type;
> >> > +module_param(readback_type, bool, 0644);
> >> > +MODULE_PARM_DESC(readback_type,
> >> > + "readback_type 0-configuration register read "
> >> > + "1- configuration
Hi Alan,
Thanks for the review...
> >
> >
> >> > +static bool readback_type;
> >> > +module_param(readback_type, bool, 0644);
> >> > +MODULE_PARM_DESC(readback_type,
> >> > + "readback_type 0-configuration register read "
> >> > + "1- configuration
Hi Moritz,
Thanks for the review...
> Can you please make the commit message such that you have full sentences?
>
> "Add support for readback of FPGA configuration data and registers" of
> example.
Sure will fix in v4.
>
> >
> > Usage:
> > Readback of PL configuration registers
>
Hi Moritz,
Thanks for the review...
> Can you please make the commit message such that you have full sentences?
>
> "Add support for readback of FPGA configuration data and registers" of
> example.
Sure will fix in v4.
>
> >
> > Usage:
> > Readback of PL configuration registers
>
ys/module/zynqmp_fpga/parameters/readback_type
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v3:
--> Added support for pl configuration data readback
--> Improved the pl configuration register readback logic.
Changes for v2:
-->
ys/module/zynqmp_fpga/parameters/readback_type
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v3:
--> Added support for pl configuration data readback
--> Improved the pl configuration register readback logic.
Changes for v2:
-->
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara
This patch adds support for Read-back of
configuration registers in zynq.
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v2:
--> Removed locks from the read ops as
lock handling is done in the framework.
drivers/fpga/zynq-fpga.c |
This patch adds support for Read-back of
configuration registers in zynq.
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v2:
--> Removed locks from the read ops as
lock handling is done in the framework.
drivers/fpga/zynq-fpga.c |
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara
ger, not one entry for the whole
> framework, so
>
> cat /sys/kernel/debug/fpga/fpga0/image
Sure will fix in v2...
>
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> >
> > ---
> > drivers/fpga/fpga-mgr.c | 52
> ++
ger, not one entry for the whole
> framework, so
>
> cat /sys/kernel/debug/fpga/fpga0/image
Sure will fix in v2...
>
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> >
> > ---
> > drivers/fpga/fpga-mgr.c | 52
> ++
This patch adds support for Read-back of
configuration registers in zynq.
Signed-off-by: Appana Durga Kedareswara rao
---
drivers/fpga/zynq-fpga.c | 254 +++
1 file changed, 254 insertions(+)
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq
This patch adds support for Read-back of
configuration registers in zynq.
Signed-off-by: Appana Durga Kedareswara rao
---
drivers/fpga/zynq-fpga.c | 254 +++
1 file changed, 254 insertions(+)
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/readback
Signed-off-by: Appana Durga Kedareswara rao
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/readback
Signed-off-by: Appana Durga Kedareswara rao
>
> The AXI VDMA core supports Vertical flip in S2MM path when Enable Vertical
> Flip (Advanced tab) is selected. To allow vertical flip programming define an
> optional 'xlnx,enable-vert-flip' channel child node property.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
>
> The AXI VDMA core supports Vertical flip in S2MM path when Enable Vertical
> Flip (Advanced tab) is selected. To allow vertical flip programming define an
> optional 'xlnx,enable-vert-flip' channel child node property.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
>
> Vertical flip state is exported in xilinx_vdma_config and depending on IP
> configuration(c_enable_vert_flip) vertical flip state is programmed in
> hardware.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
Acked-by: Kedareswara rao Appana
> ---
>
>
> Vertical flip state is exported in xilinx_vdma_config and depending on IP
> configuration(c_enable_vert_flip) vertical flip state is programmed in
> hardware.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
Acked-by: Kedareswara rao Appana
> ---
>
Hi,
Thanks for the review...
>On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi,
>>
>> >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara
>> >Rao
>> >wrote:
>> >> Hi,
>&g
Hi,
Thanks for the review...
>On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi,
>>
>> >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara
>> >Rao
>> >wrote:
>> >> Hi,
>&g
Hi,
>On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi,
>>
>>
>> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8);
>> >> >> + xdev->common.src_addr_widths = BIT(addr_width /
Hi,
>On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi,
>>
>>
>> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8);
>> >> >> + xdev->common.src_addr_widths = BIT(addr_width /
Hi,
>> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8);
>> >> + xdev->common.src_addr_widths = BIT(addr_width / 8);
>> >
>> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers?
>> >What is value of addr_width here typically? Usually controllers can
>> >support different
Hi,
>> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8);
>> >> + xdev->common.src_addr_widths = BIT(addr_width / 8);
>> >
>> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers?
>> >What is value of addr_width here typically? Usually controllers can
>> >support different
Hi Vinod,
Thanks for the review
>> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct
>xilinx_dma_device *xdev,
>> chan->direction = DMA_MEM_TO_DEV;
>> chan->id = chan_id;
>> chan->tdest = chan_id;
>> +
Hi Vinod,
Thanks for the review
>> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct
>xilinx_dma_device *xdev,
>> chan->direction = DMA_MEM_TO_DEV;
>> chan->id = chan_id;
>> chan->tdest = chan_id;
>> +
Hi,
>>> >BTW whats with LINUX tag in patches, pls drop them
>>>
>>> Ok will mention the Linux tag info in the cover letter patch from the
>>> next patch series on wards...
>>
>>Please wrap your replies within 80chars. It is very hard to read! I have
>>reflown
>for
>>readability
>
>Sure will
Hi,
>>> >BTW whats with LINUX tag in patches, pls drop them
>>>
>>> Ok will mention the Linux tag info in the cover letter patch from the
>>> next patch series on wards...
>>
>>Please wrap your replies within 80chars. It is very hard to read! I have
>>reflown
>for
>>readability
>
>Sure will
Hi Vinod,
>On Wed, Jan 03, 2018 at 05:13:29AM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi Vinod,
>>
>> Thanks for the review...
>>
>> >
>> >On Thu, Dec 21, 2017 at 03:41:37PM +0530, Kedareswara rao Appana wrote:
>> >
>> &
Hi Vinod,
>On Wed, Jan 03, 2018 at 05:13:29AM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi Vinod,
>>
>> Thanks for the review...
>>
>> >
>> >On Thu, Dec 21, 2017 at 03:41:37PM +0530, Kedareswara rao Appana wrote:
>> >
>> &
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:37PM +0530, Kedareswara rao Appana wrote:
>
>Fix title here too
Sure will fix in v2...
>
>BTW whats with LINUX tag in patches, pls drop them
Ok will mention the Linux tag info in the cover letter patch from the next
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:37PM +0530, Kedareswara rao Appana wrote:
>
>Fix title here too
Sure will fix in v2...
>
>BTW whats with LINUX tag in patches, pls drop them
Ok will mention the Linux tag info in the cover letter patch from the next
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:36PM +0530, Kedareswara rao Appana wrote:
>
>same issue for patch title here too
Ok will fix in v2...
>
>> when hardware is idle we need to toggle the SG bit in the control
>> register, inorder to update new value to
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:36PM +0530, Kedareswara rao Appana wrote:
>
>same issue for patch title here too
Ok will fix in v2...
>
>> when hardware is idle we need to toggle the SG bit in the control
>> register, inorder to update new value to
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:35PM +0530, Kedareswara rao Appana wrote:
>
>Patch title should say what is does, not the cause/effect
Sure will fix in v2...
>
>An apt title might be "populate dma caps properly"
>
>> When client driver uses
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:35PM +0530, Kedareswara rao Appana wrote:
>
>Patch title should say what is does, not the cause/effect
Sure will fix in v2...
>
>An apt title might be "populate dma caps properly"
>
>> When client driver uses
Hi,
Thanks for the review...
>
>On Thu, Dec 07, 2017 at 10:51:02AM +0530, Kedareswara rao Appana wrote:
>
>> @@ -2029,6 +2006,7 @@ static int xilinx_dma_terminate_all(struct
>> dma_chan *dchan)
>>
>> /* Remove and free all of the descriptors in the lists */
>>
Hi,
Thanks for the review...
>
>On Thu, Dec 07, 2017 at 10:51:02AM +0530, Kedareswara rao Appana wrote:
>
>> @@ -2029,6 +2006,7 @@ static int xilinx_dma_terminate_all(struct
>> dma_chan *dchan)
>>
>> /* Remove and free all of the descriptors in the lists */
>>
Hi Vinod,
>
>On Thu, Dec 07, 2017 at 10:51:01AM +0530, Kedareswara rao Appana wrote:
>> This patch series fixes below bugs in DMA and VDMA IP's
>> ---> Added channel idle checks in the driver before submitting the buffer
>descriptor to h/w.
>> ---> Fixes bug in Multi frame sotres handling in VDMA
Hi Vinod,
>
>On Thu, Dec 07, 2017 at 10:51:01AM +0530, Kedareswara rao Appana wrote:
>> This patch series fixes below bugs in DMA and VDMA IP's
>> ---> Added channel idle checks in the driver before submitting the buffer
>descriptor to h/w.
>> ---> Fixes bug in Multi frame sotres handling in VDMA
Hi Mike Looijmans,
Thanks for the review...
Sorry for the long delay in the reply...
Please find comments inline...
>On 14-01-17 06:35, Kedareswara rao Appana wrote:
>> When VDMA is configured for more than one frame in the h/w.
>> For example h/w is configured for n number
Hi Mike Looijmans,
Thanks for the review...
Sorry for the long delay in the reply...
Please find comments inline...
>On 14-01-17 06:35, Kedareswara rao Appana wrote:
>> When VDMA is configured for more than one frame in the h/w.
>> For example h/w is configured for n number
Hi Vinod,
Thanks for the review...
[Snip]
> > > Btw how and when does DMA stop, assuming it is circular it never
> > > would, isn't there a valid/stop flag associated with a descriptor
> > > which tells DMA engine what to do next
> >
> > There are two registers that controls the
Hi Vinod,
Thanks for the review...
[Snip]
> > > Btw how and when does DMA stop, assuming it is circular it never
> > > would, isn't there a valid/stop flag associated with a descriptor
> > > which tells DMA engine what to do next
> >
> > There are two registers that controls the
Hi Vinod,
Thanks for the review...
[Snip]
> >
> > > On Sat, Jan 07, 2017 at 12:15:30PM +0530, Kedareswara rao Appana wrote:
> > > > When driver is handling AXI DMA SoftIP When user submits multiple
> > > > descriptors back to back on the S2MM(recv) side with the current
> > > > driver
Hi Vinod,
Thanks for the review...
[Snip]
> >
> > > On Sat, Jan 07, 2017 at 12:15:30PM +0530, Kedareswara rao Appana wrote:
> > > > When driver is handling AXI DMA SoftIP When user submits multiple
> > > > descriptors back to back on the S2MM(recv) side with the current
> > > > driver
Hi Vinod,
Thanks for the review...
>
> On Fri, Jan 13, 2017 at 04:28:11AM +, Appana Durga Kedareswara Rao
> wrote:
> > Hi Vinod,
> >
> > Thanks for the review...
> > >
> > > On Sat, Jan 07, 2017 at 12:15:28PM +0530, Kedareswa
Hi Vinod,
Thanks for the review...
>
> On Fri, Jan 13, 2017 at 04:28:11AM +, Appana Durga Kedareswara Rao
> wrote:
> > Hi Vinod,
> >
> > Thanks for the review...
> > >
> > > On Sat, Jan 07, 2017 at 12:15:28PM +0530, Kedareswa
Hi Vinod,
Thanks for the review...
>
> On Sat, Jan 07, 2017 at 12:15:28PM +0530, Kedareswara rao Appana wrote:
> > Add channel idle state to ensure that dma descriptor is not
> > submitted when VDMA engine is in progress.
>
> any reason why you want to make your own varible and not use
Hi Vinod,
Thanks for the review...
>
> On Sat, Jan 07, 2017 at 12:15:28PM +0530, Kedareswara rao Appana wrote:
> > Add channel idle state to ensure that dma descriptor is not
> > submitted when VDMA engine is in progress.
>
> any reason why you want to make your own varible and not use
Hi Vinod,
Thanks for the review...
>
> On Sat, Jan 07, 2017 at 12:15:29PM +0530, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered
Hi Vinod,
Thanks for the review...
>
> On Sat, Jan 07, 2017 at 12:15:29PM +0530, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered
Hi Vinod,
Thanks for the review...
> On Sat, Jan 07, 2017 at 12:15:30PM +0530, Kedareswara rao Appana wrote:
> > When driver is handling AXI DMA SoftIP When user submits multiple
> > descriptors back to back on the S2MM(recv) side with the current
> > driver flow the last buffer
Hi Vinod,
Thanks for the review...
> On Sat, Jan 07, 2017 at 12:15:30PM +0530, Kedareswara rao Appana wrote:
> > When driver is handling AXI DMA SoftIP When user submits multiple
> > descriptors back to back on the S2MM(recv) side with the current
> > driver flow the last buffer
Hi Rob,
Thanks for the review...
[Snip]
> > -- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> >> > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> >> > @@ -66,6 +66,8 @@ Optional child node properties:
> >> > Optional child node properties for VDMA:
Hi Rob,
Thanks for the review...
[Snip]
> > -- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> >> > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> >> > @@ -66,6 +66,8 @@ Optional child node properties:
> >> > Optional child node properties for VDMA:
Hi Rob,
Thanks for the review
> On Wed, Jan 04, 2017 at 07:05:53PM +0530, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered the
Hi Rob,
Thanks for the review
> On Wed, Jan 04, 2017 at 07:05:53PM +0530, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered the
Hi
Thanks for the review...
>
> Hi Kedar,
>
>
> On 04-01-2017 06:54, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered the DMA
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