The following commit has been merged into the timers/core branch of tip:
Commit-ID: 397dc6f7ca3c858dc95800f299357311ccf679e6
Gitweb:
https://git.kernel.org/tip/397dc6f7ca3c858dc95800f299357311ccf679e6
Author:Dinh Nguyen
AuthorDate:Mon, 22 Mar 2021 07:18:44 -05:00
pgaclk = to_socfpga_clk(hwclk);
- u32 div = 1;
+ u32 div;
div = ((readl(socfpgaclk->hw.reg) &
SWCTRLBTCLKSEL_MASK) >>
Acked-by: Dinh Nguyen
kfree(socfpga_clk);
return;
}
}
Acked-by: Dinh Nguyen
On 4/5/21 5:30 AM, Greg KH wrote:
On Sun, Apr 04, 2021 at 10:20:26AM -0500, Dinh Nguyen wrote:
On 4/4/21 9:08 AM, Greg KH wrote:
On Sun, Apr 04, 2021 at 07:46:09AM -0500, Dinh Nguyen wrote:
From: Krzysztof Kozlowski
The Stratix10 service layer and RCU drivers are useful only
On 4/4/21 9:08 AM, Greg KH wrote:
On Sun, Apr 04, 2021 at 07:46:09AM -0500, Dinh Nguyen wrote:
From: Krzysztof Kozlowski
The Stratix10 service layer and RCU drivers are useful only on
Stratix10, so on ARMv8. Compile testing the RCU driver on 32-bit ARM
fails:
drivers/firmware
ion = FIELD_GET(RSU_VERSION_MASK,
Fixes: 4483397b0353 ("ARM: socfpga: drop ARCH_SOCFPGA")
Signed-off-by: Krzysztof Kozlowski
Reported-by: kernel test robot
Acked-by: Richard Gong
Signed-off-by: Dinh Nguyen
---
v2: add Fixes tag
---
drivers/firmware/Kconfig | 2 +-
1 file changed, 1 in
ion = FIELD_GET(RSU_VERSION_MASK,
Signed-off-by: Krzysztof Kozlowski
Reported-by: kernel test robot
Acked-by: Richard Gong
Signed-off-by: Dinh Nguyen
---
drivers/firmware/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
in
Correct the Micrel phy documentation for the ksz9021 and ksz9031 phys
for how the phy skews are set.
Signed-off-by: Dinh Nguyen
---
.../bindings/net/micrel-ksz90x1.txt | 96 ++-
1 file changed, 94 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree
:
drivers/clocksource/dw_apb_timer_of.c:66 timer_get_base_and_rate() warn:
'*base' not released on lines: 56,64.
vim +/timer_clk +66 drivers/clocksource/dw_apb_timer_of.c
5d9814df0aec56 drivers/clocksource/dw_apb_timer_of.c Dinh Nguyen2020-12-05
17 static int __init timer_get_base_and_rate
Add calls to disable the clock and unmap the timer base address in case
of any failures.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 26 +-
1 file changed, 21 insertions(+), 5
v = val + 1;
else
div = (1 << val);
Acked-by: Dinh Nguyen
Add support for Intel's eASIC N5X platform in the arm64 defconfig.
Signed-off-by: Dinh Nguyen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d612f633b771..f1fffade222e 100644
--- a/arch/arm64
As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock
driver to use the clk_hw registration method.
Suggested-by: Stephen Boyd
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-agilex.c | 114 ++-
drivers/clk/socfpga/clk-gate-s10.c | 15
As recommended by Stephen Boyd, convert the cyclone5/arria5 clock driver
to use the clk_hw registration method.
Suggested-by: Stephen Boyd
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-gate.c | 11 +++
drivers/clk/socfpga/clk-periph.c | 8
drivers/clk/socfpga/clk
As recommended by Stephen Boyd, convert the Arria10 clock driver to use
the clk_hw registration method.
Suggested-by: Stephen Boyd
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-gate-a10.c | 8
drivers/clk/socfpga/clk-periph-a10.c | 11 ++-
drivers/clk/socfpga/clk
Add calls to disable the clock and unmap the timer base address in case
of any failures.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 26 +-
1 file changed, 21 insertions(+), 5
On 2/10/21 9:05 PM, Stephen Boyd wrote:
Quoting Dinh Nguyen (2021-01-05 11:29:56)
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the eASIC
N5X platform.
Signed-off-by: Dinh Nguyen
---
.../bindings/clock/intel,easic-n5x.yaml | 46 +++
1 file changed, 46 insertions
-by: Dinh Nguyen
---
v2: use "intel,easic-n5x-clkmgr" binding
correct the pll prepare function
Address Stephen's comments
Add a binding documentation
---
drivers/clk/socfpga/clk-agilex.c | 88 +++-
drivers/clk/socfpga/clk-periph-
On 1/20/21 3:30 AM, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/clk/socfpga/clk-pll-a10.c: In function ‘__socfpga_pll_init’:
drivers/clk/socfpga/clk-pll-a10.c:76:6: warning: variable ‘rc’ set but not
used [-Wunused-but-set-variable]
Cc: Dinh Nguyen
Cc
On 1/20/21 3:30 AM, Lee Jones wrote:
Fixes the following W=1 kernel build warning(s):
drivers/clk/socfpga/clk-pll.c: In function ‘__socfpga_pll_init’:
drivers/clk/socfpga/clk-pll.c:83:6: warning: variable ‘rc’ set but not used
[-Wunused-but-set-variable]
Cc: Dinh Nguyen
Cc: Michael
Hi Stephen/Mike,
Was wondering if you had a chance to review this patch?
Thanks,
Dinh
On 1/5/21 1:29 PM, Dinh Nguyen wrote:
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver
On 1/6/21 5:14 PM, Kees Cook wrote:
On Wed, Jan 06, 2021 at 08:44:58AM -0600, Dinh Nguyen wrote:
Hi Masahiro,
With v5.11-rc1 and commit("1e860048c53ee gcc-plugins: simplify GCC
plugin-dev capability test"), I get this error for my arm socfpga_defconfig
build. I have been building
Hi Masahiro,
With v5.11-rc1 and commit("1e860048c53ee gcc-plugins: simplify GCC
plugin-dev capability test"), I get this error for my arm
socfpga_defconfig build. I have been building the kernel the same way
for many years now. Do you know what I might be doing wrong?
$ make ARCH=arm
-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-agilex.c | 88 +++-
drivers/clk/socfpga/clk-periph-s10.c | 53 +
drivers/clk/socfpga/clk-pll-s10.c| 85 ++-
drivers/clk/socfpga/stratix10-clk.h | 15 +
4 files changed, 238
The Intel eASIC N5X platform shares the same register map as the Agilex
platform, thus, we can re-use the socfpga_agilex.dtsi as the base
DTSI.
Signed-off-by: Dinh Nguyen
---
arch/arm64/Kconfig.platforms | 5 ++
arch/arm64/boot/dts/intel/Makefile| 1 +
.../boot
On 11/9/20 3:07 AM, Jisheng Zhang wrote:
This is to remove similar errors as below:
OF: /.../gpio-port@0: could not find phandle
Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support")
explained the reason of above errors well and added the generic
"ngpios" property, let's use
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 5d9814df0aec56a638bbf20795abb4cfaf3cd331
Gitweb:
https://git.kernel.org/tip/5d9814df0aec56a638bbf20795abb4cfaf3cd331
Author:Dinh Nguyen
AuthorDate:Sat, 05 Dec 2020 04:52:23 -06:00
river hits
the panic "No clock nor clock-frequency property for" because it cannot
properly get the clock.
This patch adds the error handling needed for the timer driver so that
the kernel can continue booting instead of just hitting the panic.
Signed-off-by: Dinh Nguyen
---
v3: check
Hi Daniel,
On 12/5/20 2:50 AM, Daniel Lezcano wrote:
On 04/12/2020 23:39, Dinh Nguyen wrote:
On 12/4/20 2:00 PM, Daniel Lezcano wrote:
On 04/12/2020 16:36, Dinh Nguyen wrote:
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into
On 12/4/20 2:00 PM, Daniel Lezcano wrote:
On 04/12/2020 16:36, Dinh Nguyen wrote:
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel Stratix10 and Agilex, the clo
river hits
the panic "No clock nor clock-frequency property for" because it cannot
properly get the clock.
This patch adds the error handling needed for the timer driver so that
the kernel can continue booting instead of just hitting the panic.
Signed-off-by: Dinh Nguyen
---
v2: address
Gentle ping?
On 11/20/20 4:02 AM, Jisheng Zhang wrote:
On Thu, 19 Nov 2020 06:12:25 -0600
Dinh Nguyen wrote:
commit ("b0fc70ce1f02 arm64: berlin: Select DW_APB_TIMER_OF") added the
support for the dw_apb_timer into the arm64 defconfig. However, for some
platforms like the Intel
river hits
the panic "No clock nor clock-frequency property for %" because it cannot
properly get the clock.
This patch adds support for EPROBE_DEFER so the kernel can come back to
finish probing this timer driver after the clock driver is probed.
Signed-off-by: Dinh Nguyen
---
uot;;
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -531,7 +531,7 @@ portc: gpio-controller@0 {
> compatible = "snps,dw-apb-gpio-port";
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <27>;
> + ngpios = <27>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
uot;;
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
uot;;
> gpio-controller;
> #gpio-cells = <2>;
> - snps,nr-gpios = <24>;
> + ngpios = <24>;
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
>
Acked-by: Dinh Nguyen
In case of an error, call release_mem_region when an error happens
during allocation of resources. Also add error handling for the case
that reset_controller_register fails.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
v2: return ret value
In case of an error, call release_mem_region when an error happens
during allocation of resources. Also add error handling for the case
that reset_controller_register fails.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Dinh Nguyen
---
drivers/reset/reset-socfpga.c
Hi Markus,
Thanks for catching this.
There's a commit that is going through the clock tree that will fix this:
commit c2710fdf935bb1286e8eb6a6b44991bab1fe87af
Author: Dinh Nguyen
Date: Tue Jun 16 15:24:15 2020 -0500
dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
Add
Hi Serge,
On 7/31/20 1:48 AM, Serge Semin wrote:
> Hello Dinh,
> It must be something wrong with your timer2 and timer3 declared in the Arria10
> dts because the patch didn't change anything for the first two timers (timer0
> and
> timer1). It just permits to register all DW APB Timers found in
Thor Thayer is leaving Intel and will no longer be able to maintain the
EDAC for SoCFPGA, thus transfer maintainership to Dinh Nguyen.
Signed-off-by: Dinh Nguyen
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index f0569cf304ca
On 7/21/20 8:45 AM, Yu Kuai wrote:
> if of_find_device_by_node() succeed, socfpga_setup_ocram_self_refresh
> doesn't have a corresponding put_device(). Thus add a jump target to
> fix the exception handling for this function implementation.
>
> Fixes: 44fd8c7d4005 ("ARM: socfpga: support
On 7/17/20 10:46 AM, Arnd Bergmann wrote:
> On Fri, Jul 17, 2020 at 5:36 PM Dinh Nguyen wrote:
>> On 7/16/20 3:10 PM, Arnd Bergmann wrote:
>>> On Wed, Jul 15, 2020 at 9:14 PM Dinh Nguyen wrote:
>>>>
>>>> -BEGIN PGP SIGNED MESSAGE-
>>>
On 7/16/20 3:10 PM, Arnd Bergmann wrote:
> On Wed, Jul 15, 2020 at 9:14 PM Dinh Nguyen wrote:
>>
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA512
>>
>> Hi,
>>
>> I apologize for this! I have an updated branch that fixes these tags.
>&g
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
Hi,
I apologize for this! I have an updated branch that fixes these tags.
Let me know if I need to respin the pull request.
Thanks,
Dinh
On 7/13/20 4:57 PM, Stephen Rothwell wrote:
> Hi all,
>
> In commit
>
> 3e189a193471 ("ARM: dts: socfpga:
On 7/8/20 1:30 PM, Richard Gong wrote:
> Hi Dinh,
>
>
> On 7/8/20 12:08 PM, Dinh Nguyen wrote:
>> Hi
>>
>> On 7/7/20 11:14 AM, richard.g...@linux.intel.com wrote:
>>> From: Richard Gong
>>>
>>> When CTRL+C occurs during the proc
Hi
On 7/7/20 11:14 AM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> When CTRL+C occurs during the process of FPGA reconfiguration, the FPGA
> reconfiguration process stops and the user can't perform a new FPGA
> reconfiguration properly.
>
> Set FPGA complete task to be not
On 6/29/20 3:16 AM, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> intc@fffc1000: $nodename:0:
> 'intc@fffc1000' does not match '^interrupt-controller(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski
> ---
>
On 6/26/20 3:06 AM, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> l2-cache@f000: $nodename:0:
> 'l2-cache@f000' does not match
> '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> arch/arm/boot/dts/socfpga.dtsi
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
v4: no change
v3: allow for other failures
remove tab for rstc reset_control
v2: use _get_optional_exclusive
put IP back into reset
Add optional reset property.
Signed-off-by: Dinh Nguyen
---
v4: rebased to linux-next 20200529
v3: no change
v2: actually document the "resets" and "reset-names" optional properties
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 +
1 file changed, 5
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
v3: allow for other failures
remove tab for rstc reset_control
v2: use _get_optional_exclusive
put IP back into reset
Add optional reset property.
Signed-off-by: Dinh Nguyen
---
v2: actually document the "resets" and "reset-names" optional properties
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetr
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
v2: use _get_optional_exclusive
put IP back into reset if there was an error in probe function
---
drivers/spi/spi-dw-mmio.c | 13
Add optional reset property.
Signed-off-by: Dinh Nguyen
---
v2: actually document the "resets" and "reset-names" optional properties
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetr
Add optional reset property.
Signed-off-by: Dinh Nguyen
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
Add mechanism to get the reset control and deassert it in order to bring
the IP out of reset.
Signed-off-by: Liang Jin J
Signed-off-by: Dinh Nguyen
---
drivers/spi/spi-dw-mmio.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
Convert, where possible, the stratix10 clock driver to the new parent
data scheme by specifying the parent data for clocks that have multiple
parents.
Signed-off-by: Dinh Nguyen
---
v7: no change
v6: no change
v5: no change
v4: no change
v3: no change
v2: add fw_name
---
drivers/clk/socfpga/clk
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v7: Fix license to be "(GPL-2.0-only OR BSD-2-Clause)"
v6: fix build error
All the static clk_ops data structure need a const.
Signed-off-by: Dinh Nguyen
---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: no changes
v2: created
---
drivers/clk/socfpga/clk-pll-a10.c | 2 +-
drivers/clk/socfpga/clk-pll-s10.c | 4 ++--
drivers/clk/socfpga/clk-pll.c
The enable/disable clock ops are already defined in the standard clock
ops, so we don't need to assign them.
Signed-off-by: Dinh Nguyen
---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: no changes
v2: created
---
drivers/clk/socfpga/clk-pll-a10.c | 2 --
drivers/clk/socfpga
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by: Dinh Nguyen
---
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: Address Stephen Boyd's comments
v2: update to use clk_parent_data
On 10/17/19 3:15 PM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Enable Intel Stratix10 Remote System Update (RSU) driver
>
> The Intel Remote System Update (RSU) driver provides a way for customers
> to update the boot configuration of a Intel Stratix 10 SoC device with
>
On 10/17/19 2:34 PM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add service layer, fpga manager and fpga region to the device tree
> on Intel Agilex platform.
>
> Signed-off-by: Richard Gong
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 32
>
On 10/17/19 8:00 PM, Ley Foon Tan wrote:
> On Wed, 2019-10-16 at 02:40 -0700, Ooi, Joyce wrote:
>> This patch adds QSPI flash interface in device tree for Intel Agilex
>>
>> Signed-off-by: Ooi, Joyce
>> ---
>> v2: update the qspi_rootfs partition size
>> ---
>>
On 10/16/19 4:44 AM, Ooi, Joyce wrote:
> This patch updates the reg addresses for QSPI boot and QSPI rootfs in
> the device tree for Stratix10
>
> Signed-off-by: Ooi, Joyce
> ---
> v2: update the qspi_rootfs partition size
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 6
On 10/17/19 1:28 AM, Ooi, Joyce wrote:
> This patch adds JFFS2 FS support and remove QSPI Sector 4K size force in
> the default defconfig
>
> Signed-off-by: Ooi, Joyce
> ---
> v2: disable CONFIG_MTD_SPI_NOR_USE_4K_SECTORS using the correct syntax
> ---
> arch/arm64/configs/defconfig | 2 ++
>
Enable the Cadence QSPI controller driver that is on the Stratix10 and
Agilex platforms.
Signed-off-by: Dinh Nguyen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 8e05c39eab08..cd596df2edfc
The Intel SoCFPGA Agilex platform shares the same reset controller that
is on the Stratix10.
Signed-off-by: Dinh Nguyen
---
v2: rebase to v5.4-rc1
---
drivers/reset/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index
Please ignore this version. I need to rebase it to v5.4-rc1.
Sorry for the noise...
Dinh
On 10/14/19 10:08 AM, Dinh Nguyen wrote:
> The Intel SoCFPGA Agilex platform shares the same reset controller that
> is on the Stratix10.
>
> Signed-off-by: Dinh Nguyen
> ---
> drivers
The Intel SoCFPGA Agilex platform shares the same reset controller that
is on the Stratix10.
Signed-off-by: Dinh Nguyen
---
drivers/reset/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 21efb7d39d62..280e69fbf86d
On 10/2/19 12:32 PM, Russell King - ARM Linux admin wrote:
> On Wed, Oct 02, 2019 at 09:35:51AM -0500, Dinh Nguyen wrote:
>> With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
>> amba bus probe", the amba bus driver needs to be deferred probe be
On 10/2/19 12:32 PM, Russell King - ARM Linux admin wrote:
> On Wed, Oct 02, 2019 at 09:35:51AM -0500, Dinh Nguyen wrote:
>> With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
>> amba bus probe", the amba bus driver needs to be deferred probe be
e
resource.
Fixes: 79bdcb202a35 ("ARM: 8906/1: drivers/amba: add reset control to
amba bus probe")
Signed-off-by: Dinh Nguyen
---
v3: jump to defer_probe where the driver will unmap and pm_detach the
driver resource for the next probe attempt
v2: relea
uot;ARM: 8906/1: drivers/amba: add reset control to
amba bus probe")
Signed-off-by: Dinh Nguyen
---
v2: release the resource when of_reset_control_array_get_optional_shared()
returns EPROBE_DEFER
---
drivers/amba/bus.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
amba bus probe")
Signed-off-by: Dinh Nguyen
---
drivers/amba/bus.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index f39f075abff9..f246b847c991 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -535,6 +535,7 @@ int amba_device_add(str
The Intel SoCFPGA Agilex platform shares the same reset controller that
is on the Stratix10.
Signed-off-by: Dinh Nguyen
---
drivers/reset/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 21efb7d39d62..280e69fbf86d
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by: Dinh Nguyen
---
drivers/clk/Makefile| 1 +
drivers/clk/socfpga/Makefile| 2 +
drivers/clk/socfpga/clk-agilex.c| 332
From: Dinh Nguyen
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Signed-off-by: Dinh Nguyen
---
.../devicetree/bindings/clock/intc_agilex.txt | 20 ++
include/dt-bindings/clock
On 9/10/19 8:48 AM, Tim Sander wrote:
> Hi
>
> I have noticed that my SPF records where not in place after moving the server,
> so it seems the mail didn't go to the mailing list. Hopefully that's fixed
> now.
>
> Am Dienstag, 10. September 2019, 09:16:37 CEST schrieb Masahiro Yamada:
>> On
that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
Reviewed-by: Philipp Zabel
---
v7: added Philipp Zabel's Reviewed-by:
v6: remove the need to reset_control_get_count
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
On 8/27/19 2:25 PM, Valdis Kl?tnieks wrote:
> On Mon, 26 Aug 2019 10:42:52 -0500, Dinh Nguyen said:
>> The primecell controller on some SoCs, i.e. SoCFPGA, is held in
>> reset by default. Until recently, the DMA controller was
that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v6: remove the need to reset_control_get_count as
of_reset_control_array_get_optional_shared is already doing that
v5: use
that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v5: use of_reset_control_array_get_optional_shared()
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed
Hi Philipp,
On 8/26/19 3:57 AM, Philipp Zabel wrote:
> Hi Dinh, Linus,
>
> On Fri, 2019-08-23 at 10:42 -0500, Dinh Nguyen wrote:
>>
>> On 8/23/19 4:19 AM, Linus Walleij wrote:
>>> On Tue, Aug 20, 2019 at 4:58 PM Dinh Nguyen wrote:
>>>
>>>>
On 8/23/19 4:19 AM, Linus Walleij wrote:
> On Tue, Aug 20, 2019 at 4:58 PM Dinh Nguyen wrote:
>
>> @@ -401,6 +402,26 @@ static int amba_device_try_add(struct amba_device *dev,
>> struct resource *parent)
>> ret = amba_get_enable_pclk(dev);
Hello,
Even though this patch is a V4, I'm including more people in this review
cycle because I found that there was previous patch[1] that was discussed.
Thanks,
Dinh
[1] https://patchwork.kernel.org/patch/10845695/
Dinh Nguyen (1):
drivers/amba: add reset control to amba bus probe
that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed-by:
v3: add a reset_control_put()
add error handling
On 8/19/19 1:17 AM, Masahiro Yamada wrote:
> On Tue, Jun 25, 2019 at 12:39 AM Dinh Nguyen wrote:
>>
>>
>>
>> On 6/21/19 6:23 AM, Masahiro Yamada wrote:
>>> With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller
>>> and NAND c
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: sta...@vger.kernel.org
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-periph-s10.c | 2 +-
1 file changed, 1
that may have
multiple reset signals, the code will find all reset(s) specified and
de-assert them.
Signed-off-by: Dinh Nguyen
Reviewed-by: Rob Herring
---
v4: cleaned up indentation in loop
fix up a few checkpatch warnings
add Reviewed-by:
v3: add a reset_control_put()
add error handling
On 8/13/19 7:24 PM, Stephen Boyd wrote:
> This code is indented oddly, causing checkpatch to complain. Indent it
> properly.
>
> Cc: Dinh Nguyen
> Signed-off-by: Stephen Boyd
> ---
> drivers/clk/socfpga/clk-gate.c | 4 ++--
> 1 file changed, 2 insertions(+),
that may have multiple
reset signals, the code will find all reset(s) specified and de-assert them.
Signed-off-by: Dinh Nguyen
---
v3: add a reset_control_put()
add error handling for -EPROBE_DEFER
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba
that may have multiple
reset signals, the code will find all reset(s) specified and de-assert them.
Signed-off-by: Dinh Nguyen
---
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 13 +
1 file changed, 13 insertions(+)
diff --git
On 8/2/19 9:37 AM, Rob Herring wrote:
> On Thu, Aug 1, 2019 at 12:44 PM Dinh Nguyen wrote:
>>
>> From: Dinh Nguyen
>>
>> The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
>> default. Until recently, the DMA controller was brought out of
From: Dinh Nguyen
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals that
are not used are held in reset and are left to Linux
_hw *hwclk)
> u32 l4_src;
> u32 perpll_src;
You need this line here:
const char *name = clk_hw_get_name(hwclk);
Otherwise, it fails to build. With the above change:
Acked-by: Dinh Nguyen
Thanks,
Dinh
On 6/27/19 9:07 AM, Ong, Hean Loong wrote:
> Adding LED Triggers Timers for LED blinking support on ARM devices
>
> Signed-off-by: Ong, Hean Loong
> ---
> arch/arm64/configs/defconfig |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm64/configs/defconfig
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