On 7/29/20 12:45 PM, Dinh Nguyen wrote:
Thor Thayer is leaving Intel and will no longer be able to maintain the
EDAC for SoCFPGA, thus transfer maintainership to Dinh Nguyen.
Signed-off-by: Dinh Nguyen
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 7/27/20 4:46 AM, Ooi, Joyce wrote:
From: Joyce Ooi
This patch is to replace Thor Thayer as Altera Triple Speed Ethernet
maintainer as he is moving to a different role.
Signed-off-by: Joyce Ooi
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 7/8/20 2:23 AM, Ooi, Joyce wrote:
From: Dalon Westergreen
Add support for the ptp clock used with the tse, and update
the driver to support timestamping when enabled. We also
enable debugfs entries for the ptp clock to allow some user
control and interaction with the ptp clock.
Cc:
_tse_private *priv,
+struct tse_buffer *buffer);
u32 (*tx_completions)(struct altera_tse_private *priv);
void (*add_rx_desc)(struct altera_tse_private *priv,
struct tse_buffer *buffer);
Reviewed-by: Thor Thayer
/* __ALTERA_SGDMA_H__ */
Reviewed-by: Thor Thayer
tic inline
+void csrwr8(u8 val, void __iomem *mac, size_t offs)
+{
+ void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+ writeb(val, paddr);
+}
#endif /* __ALTERA_UTILS_H__*/
Reviewed-by: Thor Thayer
static const struct of_device_id altera_tse_ids[] = {
Reviewed-by: Thor Thayer
(*get_rx_status)(struct altera_tse_private *priv);
+ int (*init_dma)(struct altera_tse_private *priv);
+ void (*uninit_dma)(struct altera_tse_private *priv);
+ void (*start_rxdma)(struct altera_tse_private *priv);
};
/* This structure is private to each device.
Reviewed-by: Thor
. */
- priv->rx_ring_size = dma_rx_num;
- priv->tx_ring_size = dma_tx_num;
ret = alloc_init_skbufs(priv);
if (ret) {
netdev_err(dev, "DMA descriptors initialization failed\n");
Reviewed-by: Thor Thayer
_buffer(priv, buffer);
+ if (ret)
+ goto out;
skb_tx_timestamp(skb);
Reviewed-by: Thor Thayer
System Manager driver
3. Altera System Resource driver
Signed-off-by: Richard Gong
No ack from Thor?
:(
I was too slow... :)
Acked-by: Thor Thayer
= devm_clk_get(>dev, NULL);
if (IS_ERR(idev->i2c_clk)) {
Reviewed-by: Thor Thayer
Hi Moritz,
On 10/7/19 4:20 PM, Moritz Fischer wrote:
Hi Thor,
On Mon, Oct 07, 2019 at 01:06:51PM -0500, Thor Thayer wrote:
Hi Moritz,
On 9/27/19 1:23 PM, Moritz Fischer wrote:
Thor,
On Fri, Sep 27, 2019 at 09:32:11AM -0500, Thor Thayer wrote:
Hi Kedar & Moritz,
On 9/27/19 12:1
Hi Moritz,
On 9/27/19 1:23 PM, Moritz Fischer wrote:
Thor,
On Fri, Sep 27, 2019 at 09:32:11AM -0500, Thor Thayer wrote:
Hi Kedar & Moritz,
On 9/27/19 12:13 AM, Appana Durga Kedareswara Rao wrote:
Hi Alan,
Did you get a chance to send your framework changes to upstream?
No they wer
Hi Kedar & Moritz,
On 9/27/19 12:13 AM, Appana Durga Kedareswara Rao wrote:
Hi Alan,
Did you get a chance to send your framework changes to upstream?
@Moritz Fischer: If Alan couldn't send his patch series, Can we take this patch
series??
Please let me know your thoughts on this.
Regards,
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
The current Cadence QSPI driver sometimes caused a
"rcu_sched self-detected stall" while writing large files.
Stall Report:
'# mtd_debug write /dev/mtd1 0 48816464 blob.img
[ 1815.454227] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1815.459789] rcu: 0-.
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
Hi Moritz,
On 7/26/19 3:42 PM, Moritz Fischer wrote:
On Thu, Jul 25, 2019 at 10:16:48AM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers
From: Thor Thayer
ARM32 SoCFPGAs had separate IRQs for SDRAM. ARM64 SoCFPGAs
send all DBEs to SError so filtering by source is necessary.
The Stratix10 SDRAM ECC is a better match with the generic
Altera peripheral ECC framework because the linked list can
be searched to find the ECC block
Hi James,
On 7/25/19 7:46 AM, James Morse wrote:
Hi Thor,
On 12/07/2019 19:28, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
ARM32 SoCFPGAs had separate IRQs for SDRAM. ARM64 SoCFPGAs
send all DBEs to SError so filtering by source is necessary.
The Stratix10 SDRAM ECC is a better
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
Hi Moritz,
On 7/24/19 9:57 AM, Moritz Fischer wrote:
On Tue, Jul 23, 2019 at 09:40:51AM -0500, Thor Thayer wrote:
Hi Moritz,
On 7/21/19 7:59 PM, Moritz Fischer wrote:
Thor,
On Tue, Jul 16, 2019 at 05:48:06PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
In preparation
From: Thor Thayer
The current Cadence QSPI driver sometimes caused a
"rcu_sched self-detected stall" while writing large files.
Stall Report:
'# mtd_debug write /dev/mtd1 0 48816464 blob.img
[ 1815.454227] rcu: INFO: rcu_sched self-detected stall on CPU
[ 1815.459789] rcu: 0-.
Hi Moritz,
On 7/21/19 7:59 PM, Moritz Fischer wrote:
Thor,
On Tue, Jul 16, 2019 at 05:48:06PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based
Hi Moritz,
On 7/21/19 7:56 PM, Moritz Fischer wrote:
Hi Thor,
looks mostly good.
On Tue, Jul 16, 2019 at 05:48:07PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
v2 Remove inline function declaration
Reverse Christmas Tree format
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
v2 Remove
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
Hi Moritz,
On 7/14/19 1:55 PM, Moritz Fischer wrote:
Hi Thor,
On Thu, Jul 11, 2019 at 03:32:50PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function
On 7/14/19 1:46 PM, Moritz Fischer wrote:
Hi Thor,
On Thu, Jul 11, 2019 at 03:32:49PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts
Hi Moritz,
On 7/14/19 1:40 PM, Moritz Fischer wrote:
On Thu, Jul 11, 2019 at 03:32:48PM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register
From: Thor Thayer
ARM32 SoCFPGAs had separate IRQs for SDRAM. ARM64 SoCFPGAs
send all DBEs to SError so filtering by source is necessary.
The Stratix10 SDRAM ECC is a better match with the generic
Altera peripheral ECC framework because the linked list can
be searched to find the ECC block
From: Thor Thayer
Add Stratix10 specific functions that use a credit mechanism
to throttle data to the CvP FIFOs. Add a private structure
with function pointers for V1 vs V2 functions.
Signed-off-by: Thor Thayer
---
drivers/fpga/altera-cvp.c | 173
From: Thor Thayer
Newer Intel FPGAs have different Vendor Specific offsets than
legacy parts. Use PCI discovery to find the CvP registers.
Since the register positions remain the same, change the hard
coded address to a more flexible way of indexing registers
from the offset.
Adding new PCI read
From: Thor Thayer
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer
---
drivers
From: Thor Thayer
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements
21:37, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The Stratix10 peripheral FIFO memories can recover from double
bit errors with a warm reset instead of a cold reset.
Add the option of a warm reset for peripheral (USB, Ethernet)
memories.
CPU memories such as SDRAM and OCRAM require
my patch and bringing in additional expertise.
On 03/06/2019 21:37, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The Stratix10 peripheral FIFO memories can recover from double
bit errors with a warm reset instead of a cold reset.
Add the option of a warm reset for peripheral (USB
On 6/3/19 10:50 AM, Suzuki K Poulose wrote:
Use the new helper to find device by of_node.
Cc: Thor Thayer
Cc: Lee Jones
Signed-off-by: Suzuki K Poulose
Acked-by: Thor Thayer
From: Thor Thayer
The Stratix10 peripheral FIFO memories can recover from double
bit errors with a warm reset instead of a cold reset.
Add the option of a warm reset for peripheral (USB, Ethernet)
memories.
CPU memories such as SDRAM and OCRAM require a cold reset for
DBEs.
Filter on whether
From: Thor Thayer
Addition of SDMMC EDAC for Stratix10 which has IRQ
differences from Arria10. Update comment accordingly.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c
From: Thor Thayer
Add the Stratix10 SDMMC EDAC node.
Signed-off-by: Thor Thayer
---
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
b/arch/arm64/boot/dts/altera
From: Thor Thayer
This patch series adds EDAC support for the Stratix10 OCRAM
and SDMMC peripherals.
Thor Thayer (4):
EDAC, altera: Add Stratix10 OCRAM ECC support
arm64: dts: stratix10: Add OCRAM EDAC node
EDAC, altera: Add Stratix10 SDMMC support
arm64: dts: stratix10: Add SDMMC EDAC
From: Thor Thayer
Add the OCRAM ECC node with Stratix10 compatible string.
Signed-off-by: Thor Thayer
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
b/arch/arm64/boot/dts
From: Thor Thayer
Use the newer ECC error injection method for Arria10 and
Stratix10 OCRAM.
If OCRAM has already been initialized during the boot and
OCRAM ECC is enabled, ensure the Single Bit Error IRQ is
enabled.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 27
Hi Boris,
On 4/9/19 3:13 PM, Borislav Petkov wrote:
On Tue, Apr 09, 2019 at 02:11:58PM -0500, Thor Thayer wrote:
If possible, I'd like this series to go through the EDAC tree since future
patches will follow this format.
You know how that works - I need ACKs.
I have ACKs on patches 1 &am
Hi Boris,
On 4/4/19 9:36 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
This patch series makes the Stratix10 EDAC Bindings
specific to the Stratix10 ARM64 architecture.
Instead of using the Arria10 (ARM32) EDAC bindings for
Stratix10 (ARM64), create Stratix10 specific EDAC
From: Thor Thayer
Use the new Stratix10 binding format for EDAC nodes.
Signed-off-by: Thor Thayer
Acked-by: Dinh Nguyen
---
v2-3 No change
Resend adds Acked-by.
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 25 ---
1 file changed, 13 insertions(+), 12 deletions
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts.
Indicate the differences between the ARM64 and ARM32
EDAC architecture in the bindings.
Signed-off-by: Thor Thayer
Acked-by: Rob
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC to capture
the differences between the ARM64 and ARM32 architecture.
Signed-off-by: Thor Thayer
Reviewed-by: Rob Herring
---
v2-3 No change.
Resend adds Reviewed-by
---
.../devicetree/bindings/edac/socfpga-eccmgr.txt| 106
From: Thor Thayer
This patch series makes the Stratix10 EDAC Bindings
specific to the Stratix10 ARM64 architecture.
Instead of using the Arria10 (ARM32) EDAC bindings for
Stratix10 (ARM64), create Stratix10 specific EDAC bindings
to capture architecture differences between ARM32 and ARM64
On 4/2/19 3:55 AM, Borislav Petkov wrote:
On Fri, Mar 29, 2019 at 09:43:58AM -0500, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Reserve ECC Double Bit Error SMC call to alert U-Boot that
a DBE has occurred. Moving the call from local EDAC header
file to this common file
From: Thor Thayer
Use the global Stratix10 SMC defines instead of the local
S10 SMC defines.
Reviewed-by: Richard Gong
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 1 +
drivers/edac/altera_edac.h | 83 --
2 files changed, 1
From: Thor Thayer
Reserve ECC Double Bit Error SMC call to alert U-Boot that
a DBE has occurred. Moving the call from local EDAC header
file to this common file.
Reviewed-by: Richard Gong
Reviewed-by: Alan Tull
Signed-off-by: Thor Thayer
---
include/linux/firmware/intel/stratix10-smc.h | 19
From: Thor Thayer
The FIFO memory and ECC initialization doesn't need to be
done as a separate operation early in the startup.
Improve the Arria10 and Stratix10 peripheral FIFO init
by initializing memory and enabling ECC as part of the
device driver initialization.
Signed-off-by: Thor Thayer
From: Thor Thayer
Improve the Arria10 and Stratix10 error injection routine
by reading the data and changing just 1 bit before writing
back out. Previous routine would overwrite the first bytes
to 0 then change 1 bit but this method is less intrusive.
Signed-off-by: Thor Thayer
---
drivers
From: Thor Thayer
This patch series makes the Stratix10 EDAC Bindings
specific to the Stratix10 ARM64 architecture.
Instead of using the Arria10 (ARM32) EDAC bindings for
Stratix10 (ARM64), create Stratix10 specific EDAC bindings
to capture architecture differences between ARM32 and ARM64
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts.
Indicate the differences between the ARM64 and ARM32
EDAC architecture in the bindings.
Signed-off-by: Thor Thayer
Acked-by: Rob
From: Thor Thayer
Use the new Stratix10 binding format for EDAC nodes.
Signed-off-by: Thor Thayer
---
v2-3 No change
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 25 ---
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/altera
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC to capture
the differences between the ARM64 and ARM32 architecture.
Signed-off-by: Thor Thayer
---
v2-3 No change
---
.../devicetree/bindings/edac/socfpga-eccmgr.txt| 106 +
1 file changed, 106 insertions
Hi Rob,
On 3/13/19 2:20 PM, Rob Herring wrote:
On Tue, Mar 12, 2019 at 2:28 PM Thor Thayer wrote:
Hi Rob,
On 3/12/19 11:04 AM, Rob Herring wrote:
On Wed, Feb 27, 2019 at 11:27:22AM -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC
From: Thor Thayer
Stratix10 Double Bit Error Address was always read from
SDRAM Address register instead of each device's Address
register.
To determine which device had the DBE, cycle through
the EDAC devices comparing the DBE value to the db_irq
value. Once found, report the DBE Address from
Hi Rob,
On 3/12/19 11:04 AM, Rob Herring wrote:
On Wed, Feb 27, 2019 at 11:27:22AM -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC to capture
the differences between the ARM64 and ARM32 architecture.
What's the difference? Sounds like
Hi Rob,
On 3/12/19 11:00 AM, Rob Herring wrote:
On Wed, Feb 27, 2019 at 11:27:21AM -0600, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager compatible
v3 Use "altr,sys-mgr" as the non-specific comp
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required
From: Thor Thayer
Instead of using the Arria10 (ARM32) EDAC bindings for
Stratix10 (ARM64), create Stratix10 specific EDAC bindings
to capture architecture differences between ARM32 and ARM64.
This requires fixing the previous Stratix10 bindings.
Also add the peripheral bindings
From: Thor Thayer
Stratix10 Double Bit errors are configured as SErrors
so skip the Double Bit IRQ initialization if Stratix10.
Since all the ECC peripherals are handled in this routine,
the machine compatible device tree test is used here
instead of multiple ECC block device tree compatible
From: Thor Thayer
Fix Stratix10 ECC bindings to specify only the single
bit error. On Stratix10 double bit errors are handled
as SErrors instead of interrupts.
Indicate the differences between the ARM64 and ARM32
EDAC architecture in the bindings.
Signed-off-by: Thor Thayer
---
v2 No change
From: Thor Thayer
Use the new Stratix10 binding format for EDAC nodes.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 25 ---
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/altera
From: Thor Thayer
Add peripheral bindings for Stratix10 EDAC to capture
the differences between the ARM64 and ARM32 architecture.
Signed-off-by: Thor Thayer
---
v2 No change
---
.../devicetree/bindings/edac/socfpga-eccmgr.txt| 106 +
1 file changed, 106 insertions
From: Thor Thayer
Replace the Stratix10 Machine compatible check with
specific ECC block compatible tests.
Signed-off-by: Thor Thayer
---
v2 New patch
---
drivers/edac/altera_edac.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/edac
From: Thor Thayer
Most users want EDAC support so make it the default.
SOCFPGA SDRAM EDAC reporting was enabled by the parent EDAC
config (CONFIG_ALTERA_EDAC) since initial customers always
wanted SDRAM EDAC enabled.
There are cases where the SDRAM needs to be disabled while
the other block
From: Thor Thayer
Enable the different ECC blocks by default on Cyclone5
and Arria10.
Signed-off-by: Thor Thayer
---
v2 Rebase patch to the arm/defconfig on the arm-soc tree
---
arch/arm/configs/socfpga_defconfig | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm
From: Thor Thayer
The CONFIG_ALTERA_EDAC flag always enables the SDRAM
EDAC. On the newer architectures, there are cases where
the peripheral EDACs are enabled but SDRAM needs to be
disabled.
This change moves SDRAM functions so they can be contained
inside the conditional CONFIG.
Create new
On 2/25/19 11:36 AM, Dinh Nguyen wrote:
Hi Thor,
On 2/19/19 12:59 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
Enable the different ECC blocks by default on Cyclone5
and Arria10.
Signed-off-by: Thor Thayer
---
arch/arm/configs/socfpga_defconfig | 36
From: Thor Thayer
The CONFIG_ALTERA_EDAC flag always enables the SDRAM
EDAC. On the newer architectures, there are cases where
the peripheral EDACs are enabled but SDRAM needs to be
disabled.
This change moves SDRAM functions so they can be contained
inside the conditional CONFIG.
Create new
From: Thor Thayer
Enable the different ECC blocks by default on Cyclone5
and Arria10.
Signed-off-by: Thor Thayer
---
arch/arm/configs/socfpga_defconfig | 36 ++--
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
Most users want EDAC support so make it the default.
SOCFPGA SDRAM EDAC reporting was enabled by the parent EDAC
config (CONFIG_ALTERA_EDAC) since initial customers always
wanted SDRAM EDAC enabled.
There are cases where the SDRAM needs to be disabled while
the other block
From: Thor Thayer
Add System Manager driver by default for SOCFPGA ARM32 platforms.
Signed-off-by: Thor Thayer
---
v2-4 No change
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
The ARM64 System Manager requires a different method of reading
the System Manager than ARM32. A new System Manager driver was
created to steer ARM32 System Manager calls to regmap_mmio and
ARM64 System Manager calls to the new access method.
Convert from syscon to the shared
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager compatible
v3 Use "altr,sys-mgr" as the non-specific comp
From: Thor Thayer
Add MFD driver for SOCFPGA System Manager to handle
System Manager calls differently for ARM32 vs ARM64.
The SOCFPGA System Manager includes registers from several
SOC peripherals.
On ARM32, syscon handles this aggregated register grouping.
Implement System Manager calls
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
Reviewed-by: Rob Herring
---
v2 New compatible string and usage for Stratix10
v3 No change
v4 Add Reviewed-by from v2.
---
.../devicetree/bindings/arm/altera/socfpga-system.txt
From: Thor Thayer
Enable the Stratix10 System Manager by default.
Signed-off-by: Thor Thayer
---
v2-4 No change
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c8432e24207e..48a312126cf7
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required
-by: Thor Thayer
Hi Joyce,
On 2/12/19 10:24 AM, Ooi, Joyce wrote:
As there is restriction to access to EMAC System Manager registers in
the kernel for Intel Stratix10, the use of SMC calls are required and
added in dwmac-socfpga driver.
Signed-off-by: Ooi, Joyce
I have a pending patchset[1] that addresses
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
---
v2 New compatible string and usage for Stratix10
v3 No change
---
.../devicetree/bindings/arm/altera/socfpga-system.txt| 12
1 file changed, 12 insertions
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