> While we're discussing, do we really want to use the "core" and "atom"
> terms here? I thought cpu/cycles/ would be ok for the main (Big) CPU and
Yes absolutely.
> that we should come up with some short name for the "litle" CPUs.
There actually isn't a main CPU.
There's nothing "better"
On 3/18/2021 9:21 AM, Arnaldo Carvalho de Melo wrote:
Em Thu, Mar 18, 2021 at 01:16:37PM +0100, Jiri Olsa escreveu:
On Wed, Mar 17, 2021 at 10:42:45AM -0300, Arnaldo Carvalho de Melo wrote:
Em Wed, Mar 17, 2021 at 08:17:52PM +0800, Jin, Yao escreveu:
I'm OK to only support
Em Thu, Mar 18, 2021 at 01:16:37PM +0100, Jiri Olsa escreveu:
> On Wed, Mar 17, 2021 at 10:42:45AM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Wed, Mar 17, 2021 at 08:17:52PM +0800, Jin, Yao escreveu:
> > > I'm OK to only support 'cpu_core/cpu-cycles/' or 'cpu_atom/cpu-cycles/'.
> > > But
> > >
On Wed, Mar 17, 2021 at 10:42:45AM -0300, Arnaldo Carvalho de Melo wrote:
> Em Wed, Mar 17, 2021 at 08:17:52PM +0800, Jin, Yao escreveu:
> > Hi Jiri,
> >
> > On 3/17/2021 6:06 PM, Jiri Olsa wrote:
> > > On Wed, Mar 17, 2021 at 10:12:03AM +0800, Jin, Yao wrote:
> > > >
> > > >
> > > > On
On Wed, Mar 17, 2021 at 08:17:52PM +0800, Jin, Yao wrote:
SNIP
> > >
> > > For example,
> > >
> > > perf stat -e '{cpu_core/cycles/,cpu_core/instructions/}' -e
> > > '{cpu_atom/cycles/,cpu_atom/instructions/}'
> > >
> > > This usage is common and reasonable. So I think we may need to support
Em Wed, Mar 17, 2021 at 08:17:52PM +0800, Jin, Yao escreveu:
> Hi Jiri,
>
> On 3/17/2021 6:06 PM, Jiri Olsa wrote:
> > On Wed, Mar 17, 2021 at 10:12:03AM +0800, Jin, Yao wrote:
> > >
> > >
> > > On 3/16/2021 10:04 PM, Jiri Olsa wrote:
> > > > On Tue, Mar 16, 2021 at 09:49:42AM +0800, Jin, Yao
Hi Jiri,
On 3/17/2021 6:06 PM, Jiri Olsa wrote:
On Wed, Mar 17, 2021 at 10:12:03AM +0800, Jin, Yao wrote:
On 3/16/2021 10:04 PM, Jiri Olsa wrote:
On Tue, Mar 16, 2021 at 09:49:42AM +0800, Jin, Yao wrote:
SNIP
Performance counter stats for 'system wide':
136,655,302
On Wed, Mar 17, 2021 at 10:12:03AM +0800, Jin, Yao wrote:
>
>
> On 3/16/2021 10:04 PM, Jiri Olsa wrote:
> > On Tue, Mar 16, 2021 at 09:49:42AM +0800, Jin, Yao wrote:
> >
> > SNIP
> >
> > >
> > > Performance counter stats for 'system wide':
> > >
> > > 136,655,302
On 3/16/2021 10:04 PM, Jiri Olsa wrote:
On Tue, Mar 16, 2021 at 09:49:42AM +0800, Jin, Yao wrote:
SNIP
Performance counter stats for 'system wide':
136,655,302 cpu_core/branch-instructions/
1.003171561 seconds time elapsed
So we need special rules for both cycles
On Tue, Mar 16, 2021 at 09:49:42AM +0800, Jin, Yao wrote:
SNIP
>
> Performance counter stats for 'system wide':
>
>136,655,302 cpu_core/branch-instructions/
>
>1.003171561 seconds time elapsed
>
> So we need special rules for both cycles and branches.
>
> The worse
Hi Jiri,
On 3/16/2021 1:37 AM, Jiri Olsa wrote:
On Mon, Mar 15, 2021 at 10:28:12AM +0800, Jin, Yao wrote:
Hi Jiri,
On 3/13/2021 3:15 AM, Jiri Olsa wrote:
On Thu, Mar 11, 2021 at 03:07:26PM +0800, Jin Yao wrote:
On hybrid platform, some hardware events are only available
on a specific pmu.
On Mon, Mar 15, 2021 at 10:28:12AM +0800, Jin, Yao wrote:
> Hi Jiri,
>
> On 3/13/2021 3:15 AM, Jiri Olsa wrote:
> > On Thu, Mar 11, 2021 at 03:07:26PM +0800, Jin Yao wrote:
> > > On hybrid platform, some hardware events are only available
> > > on a specific pmu. For example,
Hi Jiri,
On 3/13/2021 3:15 AM, Jiri Olsa wrote:
On Thu, Mar 11, 2021 at 03:07:26PM +0800, Jin Yao wrote:
On hybrid platform, some hardware events are only available
on a specific pmu. For example, 'L1-dcache-load-misses' is only
available on 'cpu_core' pmu. And even for the event which can be
On Thu, Mar 11, 2021 at 03:07:26PM +0800, Jin Yao wrote:
> On hybrid platform, some hardware events are only available
> on a specific pmu. For example, 'L1-dcache-load-misses' is only
> available on 'cpu_core' pmu. And even for the event which can be
> available on both pmus, the user also may
On hybrid platform, some hardware events are only available
on a specific pmu. For example, 'L1-dcache-load-misses' is only
available on 'cpu_core' pmu. And even for the event which can be
available on both pmus, the user also may want to just enable
one event. So now following syntax is
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