On Mon, Feb 08, 2021, Andy Lutomirski wrote:
> On Mon, Feb 8, 2021 at 9:11 AM Sean Christopherson wrote:
> >
> > On Sun, Feb 07, 2021, Andy Lutomirski wrote:
> > >
>
> > > How much of the register state is revealed to the VMM when we do a
> > > TDVMCALL?
> > > Presumably we should fully
On Mon, Feb 8, 2021 at 9:11 AM Sean Christopherson wrote:
>
> On Sun, Feb 07, 2021, Andy Lutomirski wrote:
> >
> > How much of the register state is revealed to the VMM when we do a TDVMCALL?
> > Presumably we should fully sanitize all register state that shows up in
> > cleartext on the other
On Sun, Feb 07, 2021, Andy Lutomirski wrote:
>
> > On Feb 7, 2021, at 2:31 PM, Dave Hansen wrote:
> >
> > On 2/7/21 12:29 PM, Kirill A. Shutemov wrote:
> >>> Couldn't you just have one big helper that takes *all* the registers
> >>> that get used in any TDVMCALL and sets all the rcx bits? The
> On Feb 7, 2021, at 2:31 PM, Dave Hansen wrote:
>
> On 2/7/21 12:29 PM, Kirill A. Shutemov wrote:
>>> Couldn't you just have one big helper that takes *all* the registers
>>> that get used in any TDVMCALL and sets all the rcx bits? The users
>>> could just pass 0's for the things they don't
On 2/7/21 12:29 PM, Kirill A. Shutemov wrote:
>> Couldn't you just have one big helper that takes *all* the registers
>> that get used in any TDVMCALL and sets all the rcx bits? The users
>> could just pass 0's for the things they don't use.
>>
>> Then you've got the ugly inline asm in one place.
On Sun, Feb 07, 2021 at 08:01:50AM -0800, Dave Hansen wrote:
> On 2/7/21 6:13 AM, Kirill A. Shutemov wrote:
> >>> + /* Allow to pass R10, R11, R12, R13, R14 and R15 down to the VMM
> >>> */
> >>> + rcx = BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15);
> >>> +
> >>> +
On 2/7/21 6:13 AM, Kirill A. Shutemov wrote:
>>> + /* Allow to pass R10, R11, R12, R13, R14 and R15 down to the VMM */
>>> + rcx = BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15);
>>> +
>>> + asm volatile(TDCALL
>>> + : "=a"(ret), "=r"(r10),
On Fri, Feb 05, 2021 at 03:42:01PM -0800, Andy Lutomirski wrote:
> On Fri, Feb 5, 2021 at 3:39 PM Kuppuswamy Sathyanarayanan
> wrote:
> >
> > From: "Kirill A. Shutemov"
> >
> > TDX has three classes of CPUID leaves: some CPUID leaves
> > are always handled by the CPU, others are handled by the
From: "Kirill A. Shutemov"
TDX has three classes of CPUID leaves: some CPUID leaves
are always handled by the CPU, others are handled by the TDX module,
and some others are handled by the VMM. Since the VMM cannot directly
intercept the instruction these are reflected with a #VE exception
to the
On Fri, Feb 5, 2021 at 3:39 PM Kuppuswamy Sathyanarayanan
wrote:
>
> From: "Kirill A. Shutemov"
>
> TDX has three classes of CPUID leaves: some CPUID leaves
> are always handled by the CPU, others are handled by the TDX module,
> and some others are handled by the VMM. Since the VMM cannot
10 matches
Mail list logo
