From: Icenowy Zheng <icen...@aosc.xyz>
The H3 SoC have a bigger SID controller, which has its direct read
address at 0x200 position in the SID block, not 0x0.
Also, H3 SID controller has some silicon bug that makes the direct read
value wrong at cold boot, add code to workaround t
From: Icenowy Zheng <icen...@aosc.xyz>
Sometimes the SID device have more memory address space than the real
NVMEM size (for the registers used to read/write the SID).
Fetch the NVMEM size from device compatible, rather than the memory
address space's length, in order to prepare for addin
From: Icenowy Zheng <icen...@aosc.xyz>
As we have already made sunxi_sid driver support the SID controller on
H3/H5, enable it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Changes in v6:
- Rebased on current linux-next.
- Change H3 in commit message to H3/H5.
arch/arm/boot/
On Wed, 29 Mar 2017 18:42:43 +0800
Icenowy Zheng <icen...@aosc.io> wrote:
> From: Icenowy Zheng <icen...@aosc.xyz>
>
> SoCs after A31 has a clock controller module in the PRCM part.
>
> Support the clock controller module on H3/5 and A64 now.
>
> Signed-off-by
As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
driver, we will finally have two types of layer.
Abstract the layer type to void * and a ops struct, which contains the
only function used by crtc -- get the drm_plane struct of the layer.
Signed-off-by: Icenowy Zheng <i
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Changes in v3:
-
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
The paragraph of TCON is also refactored, for furtherly add TCONs in
A83T/H3/A64/H
ng -- more investigations
are needed to gain enough information for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Refactored patch in v3.
drivers/gpu/drm/sun4i/Kconfig | 10 +
drivers/gpu/drm/sun4i/Makefile | 4 +
drivers/gpu/drm/sun4i/sun8i_layer.c | 156
ilt. As we removed the codes in CRTC code that directly call the
layer code, we can now extract the layer part and combine it with the
backend part into a new module, sun4i-backend.ko.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Refactored patch in v3.
drivers/gpu/drm/sun4i/Kcon
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 inse
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.
Add device nodes for it as well as the TCON.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Changes in v3:
- Change the size of de2
Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.
Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Pat
From: Icenowy Zheng <icen...@aosc.xyz>
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as
Icenowy Zheng (11):
dt-bindings: add binding for the Allwinner DE2 CCU
clk: sunxi-ng: add support for DE2 CCU
dt-bindings: add bindings for DE2 on V3s SoC
drm/sun4i: abstruct the layer type
drm/sun4i: abstract a mixer type
drm/sun4i: add support for Allwinner DE2 mixers
drm/sun4i: Add
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
arch/arm/boot/dts/sun8i-
From: Icenowy Zheng <icen...@aosc.xyz>
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Changes in v2:
to the PRCM MFD should be made,
see [1] (Although this is only a sketch).
The r_pio device node is also added for A64, as the driver is already
merged, and its depends (r_ccu) is now met.
[1] https://github.com/wens/linux/commits/sunxi-ng-prcm
Icenowy Zheng (5):
dt-bindings: update device tree binding
From: Icenowy Zheng <icen...@aosc.xyz>
Many Allwinner SoCs after A31 have a CCU in PRCM block.
Give the ones on H3 and A64 compatible strings.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Changes in v3:
- Removed frequency info of iosc in this device tree binding document.
C
From: Icenowy Zheng <icen...@aosc.xyz>
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H3/5 and A64 now.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Changes in v3:
- Change osc32000 mux to iosc, as its frequency varies
From: Icenowy Zheng <icen...@aosc.xyz>
A64 SoC have a CCU (r_ccu) in PRCM block.
Add the device node for it.
The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
to the user manual, and has only 30% accuracy based on our experience
on older SoCs. The real mesaured
From: Icenowy Zheng <icen...@aosc.xyz>
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The mux 3 of R_CCU is still the internal oscillator, which is said to be
16MHz plus minus 30%, and get a measured
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
arch/arm64/boot/dts/allwinner/sun
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Update the binding document to cover H3.
Signed-off-by: Icenowy Zheng <icen...@aosc
to gpadc_data struct, to indicate whether this device
is a new-generation Allwinner thermal sensor.
The thermal sensors on A64 and H5 is like the one on H3, but with of
course different formula factors.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/iio/adc/sun4i-gpadc-iio.c
As we have gained the support for the thermal sensor in H3, we can now
add its device nodes to the device tree.
Add them to the H3 device tree.
The H5 thermal sensor has some differences, and will be added furtherly.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/su
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-March/495505.html
Icenowy Zheng (3):
dt-bindings: update the Allwinner GPADC device tree binding for H3
iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
ARM: sun8i: h3: add support for the thermal sensor in H3
.../
在 2017年04月03日 17:15, Maxime Ripard 写道:
On Sun, Apr 02, 2017 at 09:33:01PM +0800, Icenowy Zheng wrote:
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus
As we added USB0 route auto switching support for A64, add related
device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
pmu0 memory area for PHY).
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 +
The upper USB port of Pine64 board is connected to the SoC's USB0 port,
which can now switch from the MUSB controller to the EHCI/OHCI pair.
Enable the EHCI/OHCI pair in the Pine64 device tree.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-
Allwinner A64 SoC features a switchable PHY0 like the one in H3, which
can switch between a MUSB controller and a pair of OHCI/EHCI controller.
Enable PHY0 route auto switching for A64.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/phy/phy-sun4i-usb.c | 1 +
1 file chan
在 2017年04月05日 15:26, Maxime Ripard 写道:
On Wed, Apr 05, 2017 at 03:17:19PM +0800, Icenowy Zheng wrote:
在 2017年04月05日 15:15, Maxime Ripard 写道:
On Wed, Apr 05, 2017 at 02:45:17AM +0800, Icenowy Zheng wrote:
As we added USB0 route auto switching support for A64, add related
device tree parts
在 2017年04月05日 16:08, Maxime Ripard 写道:
On Wed, Apr 05, 2017 at 02:15:43PM +0800, Icenowy Zheng wrote:
2017年4月5日 14:13于 Maxime Ripard <maxime.rip...@free-electrons.com>写道：
On Wed, Apr 05, 2017 at 02:01:44AM +0800, Icenowy Zheng wrote:
Add support of AXP803 regulators in the Pine64
On Tue, 11 Apr 2017, Lee Jones wrote:
On Sat, 08 Apr 2017, Icenowy Zheng wrote:
AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB
bus.
Add a compatible for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
C
From: Icenowy Zheng <icen...@aosc.xyz>
Many Allwinner SoCs after A31 have a CCU in PRCM block.
Give the ones on H3 and A64 compatible strings.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4:
- Add Rob's ACK.
Change
to the PRCM MFD should be made,
see [1] (Although this is only a sketch).
The r_pio device node is also added for A64, as the driver is already
merged, and its depends (r_ccu) is now met.
[1] https://github.com/wens/linux/commits/sunxi-ng-prcm
Icenowy Zheng (5):
dt-bindings: update device tree binding
From: Icenowy Zheng <icen...@aosc.xyz>
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H3/5 and A64 now.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Changes in v4:
- Add missing twd items in *_ccu_clks.
Changes in
From: Icenowy Zheng <icen...@aosc.xyz>
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The mux 3 of R_CCU is still the internal oscillator, which is said to be
16MHz plus minus 30%, and get a measured
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
arch/arm64/boot/dts/allwinner/sun
From: Icenowy Zheng <icen...@aosc.xyz>
A64 SoC have a CCU (r_ccu) in PRCM block.
Add the device node for it.
The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
to the user manual, and has only 30% accuracy based on our experience
on older SoCs. The real mesaured
Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.
Add it and its pinmux.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/all
for other
AXPs.
PATCH 10 enabled the regulators on Pine64.
PATCH 11 enabled Wi-Fi support on Pine64, which required DLDO4 and ELDO1
regulators.
Icenowy Zheng (11):
arm64: allwinner: a64: enable RSB on A64
arm64: allwinner: a64: add NMI controller on A64
dt-bindings: add device tree binding
Allwinner A64 SoC features a NMI controller, which is usually connected
to the AXP PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/all
AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB
bus.
Add a compatible for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devi
AXP803 is a new PMIC chip produced by X-Powers, usually paired with A64
via RSB bus. The PMIC itself is like AXP288, but with RSB support and
dedicated VBUS and ACIN.
Add support for it in the axp20x mfd driver.
Currently only power key function is supported.
Signed-off-by: Icenowy Zheng <i
The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.
Add its device node.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/all
AXP803 have the most regulators in currently supported AXP PMICs.
Add info for the regulators in the dt-bindings document.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 27
1 file changed, 27 insertions(+)
AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.
Add support for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/regulator/axp20x-regulator.c | 135 +++
include/linux/mfd/axp20x.h
As axp20x-regulator now supports AXP803, add a cell for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/mfd/axp20x.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index e468e08d84db..9065be056b39 100644
--- a/drivers/mfd/ax
As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 150 ++
1 file change
The Wi-Fi modules of Pine64 is powered via DLDO4 and ELDO1 (the latter
one provides I/O voltage).
Add device node for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16
1 file changed, 16 insertions(+)
diff
Add support of AXP803 regulators in the Pine64 device tree, in order to
enable many future functionalities, e.g. Wi-Fi.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +
1 file changed, 109 insertions(+)
diff
is added to gpadc_data struct, to mark the difference
between the old GPADCs and THS's and the new THS's.
The thermal sensors on A64 and H5 is like the one on H3, but with of
course different formula factors.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Many new var
SUN8I", not "SUN8I_A23".
Add "_A23" after "SUN8I" on the register names.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Splited from RFC v1's 2/3.
drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
include/linux/mfd/sun4i-gpadc.h | 6 +++---
2 files change
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-March/495505.html
Icenowy Zheng (4):
dt-bindings: update the Allwinner GPADC device tree binding for H3
iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to
contain A23
iio: adc: sun4i-gpadc-iio: add support for H3 ther
As we have gained the support for the thermal sensor in H3, we can now
add its device nodes to the device tree.
Add them to the H3 device tree.
The H5 thermal sensor has some differences, and will be added furtherly.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/su
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Update the binding document to cover H3.
Signed-off-by: Icenowy Zheng <icen...@aosc
On Sun, 2 Apr 2017, Maxime Ripard wrote:
Hi,
On Wed, Mar 29, 2017 at 06:42:41PM +0800, Icenowy Zheng wrote:
Allwinner SoCs after sun6i-a31 nearly all have a R_CCU in PRCM part.
(V3s and R40 do not have it, as they have even no PRCM)
This patch adds support for the ones on H3/A64.
Some
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.
When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allw
The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
controller pair that can be connected to the PHY0.
Add the MMIO region for PHY node.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
1 file chang
The upper USB port of Pine64 board is connected to the SoC's USB0 port,
which can now switch from the MUSB controller to the EHCI/OHCI pair.
Enable the EHCI/OHCI pair in the Pine64 device tree.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-
.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..a0cee17fe44b
Some new Allwinner SoCs get supported in the kernel after the
compatibles are added to cpufreq-dt-platdev driver.
Add their compatible strings in the cpufreq-dt-platdev driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
1 file chan
The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.
Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.
Signed-off-by: Icenowy Zheng <i
first, so that the clock won't go to a frequency higher than
normal.
The interval between applying the first group of factors and the second
group is based on experiments results on an Orange Pi Zero board.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/sunxi-ng/ccu_nkmp.
the regulator node to Orange Pi Zero board's device
tree.
Icenowy Zheng (5):
clk: sunxi-ng: prevent NKMP clocks from temporarily get higher freq
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
cpufreq: dt: Add support for some new Allwinner SoCs
ARM: sun8i: h3: add operating
of this regulator and set the cpu's cpu-supply
property to it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/bo
于 2017年4月17日 GMT+08:00 上午4:57:40, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Tue, Apr 11, 2017 at 09:28:55PM +0800, icen...@aosc.io wrote:
>> 在 2017-04-11 17:13，Maxime Ripard 写道：
>> > On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
>> &
as GPIO (so it's with 2.0mm pitch, not 2.54mm as
other GPIO headers).
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Added explaination on 2.0mm pitch.
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16
1 file changed, 16 insertions(+)
diff --git
The R_CCU of H3/H5 currently wrongly used A64 R_CCU compatible.
Fix it by changing it to the correct H3 compatible.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts
AXP803 is a new PMIC chip produced by X-Powers, usually paired with A64
via RSB bus. The PMIC itself is like AXP288, but with RSB support and
dedicated VBUS and ACIN.
Add support for it in the axp20x mfd driver.
Currently only power key function is supported.
Signed-off-by: Icenowy Zheng <i
The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.
Add its device node.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/all
Allwinner A64 SoC features a NMI controller, which is usually connected
to the AXP PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v2:
- Added Chen-Yu's ACK.
arch/arm64/boot/dts/allwinner/sun50i-
one per line, so that inserting a new
compatible string will be directly a new line.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
New patch in v3.
Documentation/devicetree/bindings/mfd/axp20x.txt | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documen
AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB
bus.
Add a compatible for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v3:
- Make the compatible one-li
AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.
Add support for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Place AXP803 codes before AXP806/809 ones.
- Fixed some errors in regulator description.
- Reuse AXP803
AXP803 have the most regulators in currently supported AXP PMICs.
Add info for the regulators in the dt-bindings document.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v3:
- Added Rob's ACK.
Changes in v2:
- Place AXP803 regul
NanoPi NEO2 is a board with the same size factor with the original
NanoPi NEO by FriendlyELEC.
It has a H5 instead of H3 on NanoPi NEO, and the ethernet is upgraded to
1Gbps (with external RTL8211E PHY).
Add support for this board.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch
Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.
Add it and its pinmux.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v2:
- Removed bonus properties in pio node.
- Added Chen-Yu's ACK.
arch/arm64/boot/dts/allw
done for other
AXPs.
PATCH 11 enabled the regulators on Pine64.
PATCH 12 enabled Wi-Fi support on Pine64, which required DLDO4 and ELDO1
regulators.
Icenowy Zheng (12):
arm64: allwinner: a64: enable RSB on A64
arm64: allwinner: a64: add NMI controller on A64
dt-bindings: make AXP20X
As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 150 ++
1 file change
Add support of AXP803 regulators in the Pine64 device tree, in order to
enable many future functionalities, e.g. Wi-Fi.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +
1 file changed, 109 insertions(+)
diff
As axp20x-regulator now supports AXP803, add a cell for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Make the new cell one-liner.
drivers/mfd/axp20x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/ax
As we have USB0 controller switch available on A64, we should now enable
the EHCI0/OHCI0 controllers for Pine64.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/bo
Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.
Add their device tree nodes.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/all
Orange Pi Prime is a new Allwinner H5-based SBC by Xunlong.
It's like a Orange Pi Plus 2E with H3 replaced with H5, eMMC replaced
with onboard SPI NOR Flash and wireless card changed to Realtek
RTL8723BS (with Bluetooth functionality).
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
C
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.
Add device nodes for it as well as the TCON.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Dropped leading 0's in unit name.
Changes in v3:
- Change the size of
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/g
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.
Signed-off-by: Icenowy Zheng
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Fixed the inconsistence between mixer_div clocks'
in sun4i_crtc struct.
Doing these things makes the CRTC code independent to the type of layer
(the sun4i_layers_init function name is still hardcoded and will be
changed in the next patch), so that we can finally gain support for the
mixer in DE2, which will has different layers.
Signed-off-by: Icenowy Zheng
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Removed the refactor at TCON chapter.
Changes
d
be built. As we removed the codes in CRTC code that directly call the
layer code, we can now extract the layer part and combine it with the
backend part into a new module, sun4i-backend.ko.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Comments to tag the color corr
ng -- more investigations
are needed to gain enough information for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Killed some dead code according to Jernej.
drivers/gpu/drm/sun4i/Kconfig | 10 +
drivers/gpu/drm/sun4i/Makefile | 4 +
drive
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Dropped the leading 0 in clock@100 .
Chang
Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.
Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Icenowy Zheng (11):
dt-bindings: add binding for the Allwinner DE2 CCU
clk: sunxi-ng: add support for DE2 CCU
dt-bindings: add bindings for DE2 on V3s SoC
drm/sun4i: return only planes for layers created
drm/sun4i: abstract a engine type
drm/sun4i: add support for Allwinner DE2 mixers
drm
A new usbid of UTV007 is found in a newly bought device.
The usbid is 1f71:3301.
The ID on the chip is:
UTV007
A89029.1
1520L18K1
Both video and audio is tested with the modified usbtv driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Lubomir Rintel <lkund...@v3.sk>
ng -- more investigations
are needed to gain enough information for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v5:
- Changed some code alignment.
- Request real 32-bit DMA (prepare for 64-bit SoCs).
Changes in v4:
- Killed some dead code according to Jernej.
drive
in sun4i_crtc struct.
Doing these things makes the CRTC code independent to the type of layer
(the sun4i_layers_init function name is still hardcoded and will be
changed in the next patch), so that we can finally gain support for the
mixer in DE2, which will has different layers.
Signed-off-by: Icenowy Zheng
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