On Tue, Jul 23, 2024 at 5:58 AM Charlie Jenkins wrote:
>
> The D1/D1s SoCs support xtheadvector so it can be included in the
> devicetree. Also include vlenb for the cpu.
>
> Signed-off-by: Charlie Jenkins
> Reviewed-by: Conor Dooley
Acked-by: Chen-Yu Tsai
Please take this
On Thu, Jun 20, 2024 at 7:57 AM Charlie Jenkins wrote:
>
> The D1/D1s SoCs support xtheadvector so it can be included in the
> devicetree. Also include vlenb for the cpu.
>
> Signed-off-by: Charlie Jenkins
> Reviewed-by: Conor Dooley
Acked-by: Chen-Yu Tsai
If the RISC-V m
Hi Sagi,
On 2023-12-12 at 12:46:23 -0800, Sagi Shahar wrote:
> From: Erdem Aktas
>
> Adding a test to verify TDX lifecycle by creating a TD and running a
> dummy TDG.VP.VMCALL inside it.
>
> Signed-off-by: Erdem Aktas
> Signed-off-by: Ryan Afranji
> Signed-off-by: Sagi Shahar
> Co-developed
