On Thu, Sep 12, 2024 at 11:50:18AM +0100, Will Deacon wrote:
> Hi Dave,
>
> On Wed, Sep 11, 2024 at 08:33:54AM -0700, Dave Hansen wrote:
> > On 9/11/24 08:01, Kevin Brodsky wrote:
> > > On 22/08/2024 17:10, Joey Gouly wrote:
> > >> @@ -371,6 +382,9 @@ int copy
On Wed, Sep 04, 2024 at 05:17:58PM +0100, Will Deacon wrote:
> On Wed, Sep 04, 2024 at 01:55:03PM +0100, Joey Gouly wrote:
> > On Wed, Sep 04, 2024 at 12:43:02PM +0100, Will Deacon wrote:
> > > Right, there's quite a lot I need to do:
> > >
> > > - Uncorr
On Wed, Sep 04, 2024 at 12:43:02PM +0100, Will Deacon wrote:
> On Wed, Sep 04, 2024 at 12:32:21PM +0100, Joey Gouly wrote:
> > On Wed, Sep 04, 2024 at 11:22:54AM +0100, Will Deacon wrote:
> > > On Tue, Sep 03, 2024 at 03:54:13PM +0100, Joey Gouly wrote:
> > > > On M
On Wed, Sep 04, 2024 at 11:22:54AM +0100, Will Deacon wrote:
> On Tue, Sep 03, 2024 at 03:54:13PM +0100, Joey Gouly wrote:
> > On Mon, Sep 02, 2024 at 08:08:08PM +0100, Catalin Marinas wrote:
> > > On Tue, Aug 27, 2024 at 12:38:04PM +0100, Will Deacon wrote:
> > > >
On Tue, Sep 03, 2024 at 03:50:46PM +0100, Joey Gouly wrote:
> On Thu, Aug 29, 2024 at 06:55:07PM +0100, Mark Brown wrote:
> > On Thu, Aug 22, 2024 at 04:10:59PM +0100, Joey Gouly wrote:
> >
> > > +static bool fault_from_pkey(unsigned long esr, struct vm
gt; On Fri, Aug 23, 2024 at 05:41:06PM +0100, Catalin Marinas wrote:
> > > > > On Fri, Aug 23, 2024 at 03:45:32PM +0100, Will Deacon wrote:
> > > > > > On Thu, Aug 22, 2024 at 04:10:49PM +0100, Joey Gouly wrote:
> > > > > > > +static void per
On Thu, Aug 29, 2024 at 06:55:07PM +0100, Mark Brown wrote:
> On Thu, Aug 22, 2024 at 04:10:59PM +0100, Joey Gouly wrote:
>
> > +static bool fault_from_pkey(unsigned long esr, struct vm_area_struct *vma,
> > + unsigned int mm_flags)
> > +{
&g
On Fri, Aug 30, 2024 at 12:23:33PM +0100, Marc Zyngier wrote:
> On Fri, 30 Aug 2024 10:25:27 +0100,
> Will Deacon wrote:
> >
> > On Thu, Aug 22, 2024 at 04:10:51PM +0100, Joey Gouly wrote:
> > > To allow using newer instructions that current assemblers don't know
Add a regset for POE containing POR_EL0.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Mark Brown
Reviewed-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
---
arch/arm64/kernel/ptrace.c | 46 ++
include/uapi/linux/elf.h
Check that when POE is enabled, the POR_EL0 register is accessible.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
Reviewed-by: Mark Brown
---
tools/testing/selftests/arm64/abi/hwcap.c | 14 ++
1 file changed, 14 insertions(+)
diff
Add new system registers:
- POR_EL1
- POR_EL0
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Shuah Khan
Reviewed-by: Mark Brown
---
tools/testing/selftests/kvm/aarch64/get-reg-list.c | 14 ++
1 file changed, 14
s to the uc_mcontext is abstracted, as arm64 has a different structure.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Acked-by: Dave Hansen
---
.../arm64/signal/testcases/testcases.h| 3 +
tools
Ensure that we get signal context for POR_EL0 if and only if POE is present
on the system.
Copied from the TPIDR2 test.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
Reviewed-by: Mark Brown
Acked-by: Shuah Khan
---
.../testing/selftests/arm64
Teach the signal frame parsing about the new POE frame, avoids warning when it
is generated.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
Reviewed-by: Mark Brown
---
tools/testing/selftests/arm64/signal/testcases/testcases.c | 4
1 file
This indicates if the system supports POE. This is a CPUCAP_BOOT_CPU_FEATURE
as the boot CPU will enable POE if it has it, so secondary CPUs must also
have this feature.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Acked-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
arm64's fpregs are not at a constant offset from sigcontext. Since this is
not an important part of the test, don't print the fpregs pointer on arm64.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar
Put this function in the header so that it can be used by other tests, without
needing to link to testcases.c.
This will be used by selftest/mm/protection_keys.c
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar
Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Acked-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
---
arch/arm64/include/asm/el2_setup.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion
Now that PKEYs support has been implemented, enable it for CPUs that
support S1POE.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Acked-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
---
arch/arm64/include/asm/pkeys.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Now that support for POE and Protection Keys has been implemented, add a
config to allow users to actually enable it.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Anshuman Khandual
Acked-by: Catalin Marinas
---
arch/arm64/Kconfig | 23 +++
1
plied' encodings in PIRE0_EL1, so that PIE and
POE can coexist.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/pgtable-prot.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git arch/arm64/include/a
VM_PKEY_BIT[012] will use VM_HIGH_ARCH_[012], move the MTE VM flags to
accommodate this.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Acked-by: Catalin Marinas
---
include/linux/mm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git include/linux/mm.h
Add PKEY support to signals, by saving and restoring POR_EL0 from the
stackframe.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Mark Brown
Acked-by: Szabolcs Nagy
Reviewed-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
---
arch/arm64/include/uapi/asm
Implement the PKEYS interface, using the Permission Overlay Extension.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/mmu.h | 1 +
arch/arm64/include/asm/mmu_context.h | 46 +++-
arch/arm64/include/asm
We do not want take POE into account when clearing the MTE tags.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
---
arch/arm64/include/asm/pgtable.h | 11 +++
1 file changed, 7 insertions(+), 4 deletions
When a PTE is modified, the POIndex must be masked off so that it can be
modified.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
---
arch/arm64/include/asm/pgtable.h | 3 ++-
1 file changed, 2 insertions(+), 1
If a memory fault occurs that is due to an overlay/pkey fault, report that to
userspace with a SEGV_PKUERR.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/traps.h | 1 +
arch/arm64/kernel/traps.c | 6
arch
Modify arch_calc_vm_prot_bits() and vm_get_page_prot() such that the pkey
value is set in the vm_flags and then into the pgprot value.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/mman.h | 10 +-
arch/arm64/mm/mmap.c | 11
The 3-bit POIndex is stored in the PTE at bits 60..62.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Acked-by: Catalin Marinas
---
arch/arm64/include/asm/pgtable-hwdef.h | 10 ++
1 file changed, 10 insertions(+)
diff --git arch/arm64/include/asm/pgtable-hwdef.h
arch
POR_EL0 is a register that can be modified by userspace directly,
so it must be context switched.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Catalin Marinas
---
arch/arm64/include/asm/cpufeature.h | 6 ++
arch/arm64/include/asm/processor.h | 1 +
arch
Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to
check if the CPU supports the feature.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Catalin Marinas
Reviewed-by: Anshuman Khandual
---
Documentation/arch/arm64/elf_hwcaps.rst | 2
Add the missing sanitisation of ID_AA64MMFR3_EL1, making sure we
solely expose S1POE and TCRX (we currently don't support anything
else).
[joey: Took Marc's patch for S1PIE, and changed it for S1POE]
Signed-off-by: Marc Zyngier
Signed-off-by: Joey Gouly
---
arch/arm64/kvm/sys_
the IPA regardless of S1
permissions.
Signed-off-by: Joey Gouly
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Marc Zyngier
---
arch/arm64/kvm/hyp/include/hyp/fault.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git arch/arm64/kvm/hyp
To allow using newer instructions that current assemblers don't know about,
replace the `at` instruction with the underlying SYS instruction.
Signed-off-by: Joey Gouly
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Marc Zyngier
---
arch/arm64/includ
Define the new system registers that POE introduces and context switch them.
Signed-off-by: Joey Gouly
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_host.h | 4
arch/arm64/include/asm
The new config option specifies how many bits are in each PKEY.
Signed-off-by: Joey Gouly
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: Borislav Petkov
Cc: Dave Hansen
Cc: H. Peter Anvin
Cc: x...@kernel.org
Acked-by: Dave Hansen
---
arch/x86/Kconfig | 4
1 file changed, 4 insertions
Use the new CONFIG_ARCH_PKEY_BITS to simplify setting these bits
for different architectures.
Signed-off-by: Joey Gouly
Cc: Andrew Morton
Cc: linux-fsde...@vger.kernel.org
Cc: linux...@kvack.org
Acked-by: Dave Hansen
Reviewed-by: Anshuman Khandual
---
fs/proc/task_mmu.c | 2 ++
include
The new config option specifies how many bits are in each PKEY.
Signed-off-by: Joey Gouly
Cc: Michael Ellerman
Cc: Nicholas Piggin
Cc: Christophe Leroy
Cc: "Aneesh Kumar K.V"
Cc: "Naveen N. Rao"
Cc: linuxppc-...@lists.ozlabs.org
Acked-by: Michael Ellerman
---
arch
6-kvm-arm64-get-reg-list-v2-0-1d3fbc7b6...@kernel.org/
Joey Gouly (30):
powerpc/mm: add ARCH_PKEY_BITS to Kconfig
x86/mm: add ARCH_PKEY_BITS to Kconfig
mm: use ARCH_PKEY_BITS to define VM_PKEY_BITN
arm64: disable trapping of POR_EL0 to EL2
arm64: cpufeature: add Permission Overlay Exte
list: add Permission
> Indirection registers")
> Signed-off-by: Mark Brown
Argh!
Thanks for spotting that.
Reviewed-by: Joey Gouly
> ---
> tools/testing/selftests/kvm/aarch64/get-reg-list.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
ocess and only
> restore THP number from parent process.
>
> Fixes: c23ea61726d5 ("selftests/mm: protection_keys: save/restore
> nr_hugepages settings")
> Tested-by: Joey Gouly
> Signed-off-by: Muhammad Usama Anjum
> ---
> tools/testing/selftests/mm/protec
On Wed, Mar 13, 2024 at 11:12:58PM +0500, Muhammad Usama Anjum wrote:
> On 3/13/24 7:58 PM, Joey Gouly wrote:
> > Hi Muhammad,
> >
> > On Thu, Jan 25, 2024 at 08:46:07PM +0500, Muhammad Usama Anjum wrote:
> >> Save and restore nr_hugepages before changing it durin
Hi Muhammad,
On Thu, Jan 25, 2024 at 08:46:07PM +0500, Muhammad Usama Anjum wrote:
> Save and restore nr_hugepages before changing it during the test. A test
> should not change system wide settings.
>
> Fixes: 5f23f6d082a9 ("x86/pkeys: Add self-tests")
> Signed-off-by: Muhammad Usama Anjum
> --
On Mon, Dec 11, 2023 at 06:49:37PM +, Catalin Marinas wrote:
> On Fri, Nov 24, 2023 at 04:34:59PM +0000, Joey Gouly wrote:
> > @@ -211,11 +212,24 @@ init_new_context(struct task_struct *tsk, struct
> > mm_struct *mm)
> > {
> > atomic64_set(&mm->contex
Hi,
On Mon, Dec 11, 2023 at 06:18:17PM +, Catalin Marinas wrote:
> On Fri, Nov 24, 2023 at 04:34:57PM +0000, Joey Gouly wrote:
> > @@ -497,6 +498,23 @@ static void do_bad_area(unsigned long far, unsigned
> > long esr,
> > #define VM_FAULT_BADMAP((__forc
Hi,
Thanks to you and Mark for the comments so far!
On Thu, Dec 07, 2023 at 03:25:17PM +, Catalin Marinas wrote:
> On Fri, Nov 24, 2023 at 04:34:56PM +0000, Joey Gouly wrote:
> > diff --git a/arch/arm64/include/asm/pkeys.h b/arch/arm64/include/asm/pkeys.h
> > new file mode 1
Hi Marc,
On Mon, Dec 04, 2023 at 11:03:24AM +, Marc Zyngier wrote:
> Hi Joey,
>
> On Fri, 24 Nov 2023 16:34:45 +0000,
> Joey Gouly wrote:
> >
> > Hello everyone,
> >
> > This series implements the Permission Overlay Extension introduced in 2022
>
Add new system registers:
- POR_EL1
- POR_EL0
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Shuah Khan
---
tools/testing/selftests/kvm/aarch64/get-reg-list.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tools
Teach the signal frame parsing about the new POE frame, avoids warning when it
is generated.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
Reviewed-by: Mark Brown
---
tools/testing/selftests/arm64/signal/testcases/testcases.c | 4
1 file
s to the uc_mcontext is abstracted, as arm64 has a different structure.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Acked-by: Dave Hansen
---
.../arm64/signal/testcases/testcases.h| 3 +
tools
Ensure that we get signal context for POR_EL0 if and only if POE is present
on the system.
Copied from the TPIDR2 test.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
---
.../testing/selftests/arm64/signal/.gitignore | 1 +
.../arm64/signal
Check that when POE is enabled, the POR_EL0 register is accessible.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
---
tools/testing/selftests/arm64/abi/hwcap.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tools/testing
arm64's fpregs are not at a constant offset from sigcontext. Since this is
not an important part of the test, don't print the fpregs pointer on arm64.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar
Put this function in the header so that it can be used by other tests, without
needing to link to testcases.c.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
---
.../arm64/signal/testcases/testcases.c
Now that PKEYs support has been implemented, enable it for CPUs that
support S1POE.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pkeys.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/pkeys.h b/arch/arm64
Add a regset for POE containing POR_EL0.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/kernel/ptrace.c | 46 ++
include/uapi/linux/elf.h | 1 +
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/kernel/ptrace.c b
Add PKEY support to signals, by saving and restoring POR_EL0 from the
stackframe.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Mark Brown
---
arch/arm64/include/uapi/asm/sigcontext.h | 7
arch/arm64/kernel/signal.c | 51
Set the EL0/userspace indirection encodings to be the overlay enabled
variants of the permissions.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pgtable-prot.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64
Implement the PKEYS interface, using the Permission Overlay Extension.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/mmu.h | 2 +
arch/arm64/include/asm/mmu_context.h | 32 -
arch/arm64/include/asm/pgtable.h | 23
These functions will be extended to support pkeys.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/mmu_context.h | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/mmu_context.h
b/arch
If a memory fault occurs that is due to an overlay/pkey fault, report that to
userspace with a SEGV_PKUERR.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/traps.h | 1 +
arch/arm64/kernel/traps.c | 12 --
arch/arm64/mm/fault.c
Enable the ARCH_HAS_PKEYS config, but provide dummy
functions for the entire interface.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/Kconfig | 2 ++
arch/arm64/include/asm/pkeys.h | 54 ++
arch/arm64/mm/mmu.c
Define the VM_PKEY_BIT* values for arm64, and convert them into the arm64
specific pgprot values.
Move the current values for x86 and PPC into arch/*.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/mman.h | 8 +++-
arch/arm64/include/asm
When a PTE is modified, the POIndex must be masked off so that it can be
modified.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pgtable.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch
The 3-bit POIndex is stored in the PTE at bits 60..62.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pgtable-hwdef.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
b/arch/arm64/include/asm
Define the new system registers that POE introduces and context switch them.
Signed-off-by: Joey Gouly
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/kvm_arm.h | 4 ++--
arch/arm64/include/asm/kvm_host.h | 4
arch
POR_EL0 is a register that can be modified by userspace directly,
so it must be context switched.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/cpufeature.h | 6 ++
arch/arm64/include/asm/processor.h | 1 +
arch/arm64/include/asm/sysreg.h
Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to
check if the CPU supports the feature.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
Documentation/arch/arm64/elf_hwcaps.rst | 3 +++
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64
Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/el2_setup.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/el2_setup.h
b/arch/arm64
Add E0POE bit that traps accesses to POR_EL0 from EL0.
Updated according to DDI0601 2023-03.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Mark Brown
---
arch/arm64/tools/sysreg | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64
This indicates if the system supports POE. This is a CPUCAP_BOOT_CPU_FEATURE
as the boot CPU will enable POE if it has it, so secondary CPUs must also
have this feature.
Add a new config option: ARM64_POE
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/Kconfig
...@arm.com/
[3] Documentation/core-api/protection-keys.rst
Joey Gouly (25):
arm64/sysreg: add system register POR_EL{0,1}
arm64/sysreg: update CPACR_EL1 register
arm64: cpufeature: add Permission Overlay Extension cpucap
arm64: disable trapping of POR_EL0 to EL2
arm64: context switch P
Add POR_EL{0,1} according to DDI0601 2023-03.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Mark Brown
---
arch/arm64/include/asm/sysreg.h | 13 +
arch/arm64/tools/sysreg | 12
2 files changed, 25 insertions(+)
diff --git a/arch
Add new system registers:
- POR_EL1
- POR_EL0
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Shuah Khan
---
tools/testing/selftests/kvm/aarch64/get-reg-list.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tools
Ensure that we get signal context for POR_EL0 if and only if POE is present
on the system.
Copied from the TPIDR2 test.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
---
.../testing/selftests/arm64/signal/.gitignore | 1 +
.../arm64/signal
Teach the signal frame parsing about the new POE frame, avoids warning when it
is generated.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
---
tools/testing/selftests/arm64/signal/testcases/testcases.c | 4
1 file changed, 4 insertions
s to the uc_mcontext is abstracted, as arm64 has a different structure.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
Acked-by: Dave Hansen
---
.../arm64/signal/testcases/testcases.h| 3 +
tools
Check that when POE is enabled, the POR_EL0 register is accessible.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Mark Brown
Cc: Shuah Khan
---
tools/testing/selftests/arm64/abi/hwcap.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/tools/testing
arm64's fpregs are not at a constant offset from sigcontext. Since this is
not an important part of the test, don't print the fpregs pointer on arm64.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar
Put this function in the header so that it can be used by other tests, without
needing to link to testcases.c.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Andrew Morton
Cc: Shuah Khan
Cc: Dave Hansen
Cc: Aneesh Kumar K.V
---
.../arm64/signal/testcases/testcases.c
Set the EL0/userspace indirection encodings to be the overlay enabled
variants of the permissions.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pgtable-prot.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64
Now that PKEYs support has been implemented, enable it for CPUs that
support S1POE.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pkeys.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/pkeys.h b/arch/arm64
Add PKEY support to signals, by saving and restoring POR_EL0 from the
stackframe.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/uapi/asm/sigcontext.h | 7
arch/arm64/kernel/signal.c | 51
2 files changed, 58
Implement the PKEYS interface, using the Permission Overlay Extension.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/mmu.h | 2 +
arch/arm64/include/asm/mmu_context.h | 32 -
arch/arm64/include/asm/pgtable.h | 23
These functions will be extended to support pkeys.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/mmu_context.h | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/mmu_context.h
b/arch
If a memory fault occurs that is due to an overlay/pkey fault, report that to
userspace with a SEGV_PKUERR.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/traps.h | 1 +
arch/arm64/kernel/traps.c | 12 --
arch/arm64/mm/fault.c
Enable the ARCH_HAS_PKEYS config, but provide dummy
functions for the entire interface.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/Kconfig | 2 ++
arch/arm64/include/asm/pkeys.h | 54 ++
arch/arm64/mm/mmu.c
When a PTE is modified, the POIndex must be masked off so that it can be
modified.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pgtable.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch
Define the VM_PKEY_BIT* values for arm64, and convert them into the arm64
specific pgprot values.
Move the current values for x86 and PPC into arch/*.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/mman.h | 8 +++-
arch/arm64/include/asm
The 3-bit POIndex is stored in the PTE at bits 60..62.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/pgtable-hwdef.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
b/arch/arm64/include/asm
Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to
check if the CPU supports the feature.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
Documentation/arch/arm64/elf_hwcaps.rst | 3 +++
arch/arm64/include/asm/hwcap.h | 1 +
arch/arm64
Define the new system registers that POE introduces and context switch them.
Signed-off-by: Joey Gouly
Cc: Marc Zyngier
Cc: Oliver Upton
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/kvm_arm.h | 4 ++--
arch/arm64/include/asm/kvm_host.h | 4
arch
POR_EL0 is a register that can be modified by userspace directly,
so it must be context switched.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/cpufeature.h | 6 ++
arch/arm64/include/asm/processor.h | 1 +
arch/arm64/include/asm/sysreg.h
Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/include/asm/el2_setup.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/el2_setup.h
b/arch/arm64
This indicates if the system supports POE. This is a CPUCAP_BOOT_CPU_FEATURE
as the boot CPU will enable POE if it has it, so secondary CPUs must also
have this feature.
Add a new config option: ARM64_POE
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
---
arch/arm64/Kconfig
Add E0POE bit that traps accesses to POR_EL0 from EL0.
Updated according to DDI0601 2023-03.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Mark Brown
---
arch/arm64/tools/sysreg | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64
92850.1940729-7-mark.rutl...@arm.com/#t
[5] test_ptrace_modifies_pkru asserts for me on a Ubuntu 5.4 kernel, but does
so before my changes as well
Joey Gouly (24):
arm64/sysreg: add system register POR_EL{0,1}
arm64/sysreg: update CPACR_EL1 register
arm64: cpufeature: add Permission Overlay E
Add POR_EL{0,1} according to DDI0601 2023-03.
Signed-off-by: Joey Gouly
Cc: Catalin Marinas
Cc: Will Deacon
Reviewed-by: Mark Brown
---
arch/arm64/include/asm/sysreg.h | 13 +
arch/arm64/tools/sysreg | 12
2 files changed, 25 insertions(+)
diff --git a/arch
Hi Mark,
On Mon, Oct 09, 2023 at 03:49:29PM +0100, Mark Brown wrote:
> On Thu, Oct 05, 2023 at 03:34:29PM +0100, Mark Brown wrote:
> > On Wed, Sep 27, 2023 at 03:01:18PM +0100, Joey Gouly wrote:
> > > Add PKEY support to signals, by saving and restoring POR_EL0 from the
Hi Mark,
On Thu, Oct 05, 2023 at 03:34:29PM +0100, Mark Brown wrote:
> On Wed, Sep 27, 2023 at 03:01:18PM +0100, Joey Gouly wrote:
> > Add PKEY support to signals, by saving and restoring POR_EL0 from the
> > stackframe.
>
> It'd be nice to have at least a basic t
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