On Wed, Feb 05, 2014 at 01:16:53PM +, Robert Longbottom wrote:
> On 28 Jan 2014, at 02:02 AM, Daniel Glöckner wrote:
> > When we cycle through all combinations in one minute, there are about
> > a hundred PCI cycles per combination left for the chip to be granted
> > access to the bus. I expec
On 28 Jan 2014, at 02:02 AM, Daniel Glöckner wrote:
> On Mon, Jan 27, 2014 at 08:55:00PM +, Robert Longbottom wrote:
>>> As for the CPLD, there is not much we can do. I count 23 GPIOs going
>>> to that chip. And we don't know if some of these are outputs of the
>>> CPLD, making it a bit ris
On Mon, Jan 27, 2014 at 08:55:00PM +, Robert Longbottom wrote:
> >As for the CPLD, there is not much we can do. I count 23 GPIOs going
> >to that chip. And we don't know if some of these are outputs of the
> >CPLD, making it a bit risky to just randomly drive values on those
> >pins.
>
> Is th
On 27/01/14 03:20, Daniel Glöckner wrote:
On Sun, Jan 26, 2014 at 04:23:06PM +, Robert Longbottom wrote:
000 00D7 DSTATUS
114 32734000 RISC_STRT_ADD
120 32734000 RISC_COUNT
Video is present and locked but the RISC counter is stuck at the start
address. My best guess is that the CPLD is
On Sun, Jan 26, 2014 at 04:23:06PM +, Robert Longbottom wrote:
> 000 00D7 DSTATUS
> 114 32734000 RISC_STRT_ADD
> 120 32734000 RISC_COUNT
Video is present and locked but the RISC counter is stuck at the start
address. My best guess is that the CPLD is not forwarding the REQ signal
to the PC
On 26/01/14 12:55, Daniel Glöckner wrote:
On Sun, Jan 26, 2014 at 11:21:31AM +, Robert Longbottom wrote:
0F0 00F9 PLL_F_LO
0F4 00DC PLL_F_HI
0F8 008E PLL_XCI
The PLL is enabled and configured for a 28.63636MHz input clock.
With the default board config these registers are not t
On Sun, Jan 26, 2014 at 11:21:31AM +, Robert Longbottom wrote:
> 0F0 00F9 PLL_F_LO
> 0F4 00DC PLL_F_HI
> 0F8 008E PLL_XCI
The PLL is enabled and configured for a 28.63636MHz input clock.
With the default board config these registers are not touched
at all, so this must be a remnant
On 25/01/14 15:23, Daniel Glöckner wrote:
On Thu, Jan 23, 2014 at 02:29:19PM +, Robert Longbottom wrote:
Jan 23 14:24:48 quad kernel: [154562.493224] bits: FMTCHG* VSYNC
HSYNC OFLOW FBUS NUML => 625
Jan 23 14:24:49 quad kernel: [154562.994015] bttv: 0: timeout:
drop=0 irq=1868/1868, risc=1
On Thu, Jan 23, 2014 at 02:29:19PM +, Robert Longbottom wrote:
> Jan 23 14:24:48 quad kernel: [154562.493224] bits: FMTCHG* VSYNC
> HSYNC OFLOW FBUS NUML => 625
> Jan 23 14:24:49 quad kernel: [154562.994015] bttv: 0: timeout:
> drop=0 irq=1868/1868, risc=146da000, bits: VSYNC HSYNC OFLOW
> Ja
On Wed, Jan 22, 2014 at 06:15:44PM +, Robert Longbottom wrote:
> On 22/01/14 13:50, Daniel Glöckner wrote:
> >This is strange. There are 7 different IRQs assigned to that card but
> >PCI slots only have 4. According to the pictures each 878A gets one of
> >these. The .0 and .1 functions of a 87
On Wed, Jan 22, 2014 at 01:09:20PM +, Robert Longbottom wrote:
> > - The unlabled chip is probably a CPLD/FGPA. It filters the PCI REQ#
> >lines from the 878As and has access to the GNT# and INT# lines,
> >as well as to the GPIOs you mentioned. The bypass caps have a layout
> >that
On 22/01/14 11:53, Daniel Glöckner wrote:
On Tue, Jan 21, 2014 at 08:59:55PM +, Robert Longbottom wrote:
On 21/01/2014 19:49, Robert Longbottom wrote:
Here are some high-res pictures of both sides of the card. Scanned at
600dpi (300dpi the tracks were very close). Good idea to scan it by
On Tue, Jan 21, 2014 at 08:59:55PM +, Robert Longbottom wrote:
> On 21/01/2014 19:49, Robert Longbottom wrote:
> >Here are some high-res pictures of both sides of the card. Scanned at
> >600dpi (300dpi the tracks were very close). Good idea to scan it by the
> >way, I like that, much better r
On 21/01/2014 19:49, Robert Longbottom wrote:
On 21/01/2014 10:19, Daniel Glöckner wrote:
On Tue, Jan 21, 2014 at 09:27:38AM +, Robert Longbottom wrote:
On 20 Jan 2014, at 10:55 PM, Andy Walls wrote:
Robert Longbottom wrote:
Chips on card:
>
Can you upload high resolution pictures of
On 21/01/2014 10:19, Daniel Glöckner wrote:
On Tue, Jan 21, 2014 at 09:27:38AM +, Robert Longbottom wrote:
On 20 Jan 2014, at 10:55 PM, Andy Walls wrote:
Robert Longbottom wrote:
Chips on card:
>
Can you upload high resolution pictures of both sides of the card
somewhere? Something whe
On Tue, Jan 21, 2014 at 09:27:38AM +, Robert Longbottom wrote:
> On 20 Jan 2014, at 10:55 PM, Andy Walls wrote:
> > Robert Longbottom wrote:
> >> Chips on card:
> >> 1x SMD IC with no markings at all
> >> Couple of 74HCTnnn chips
> >> 1x Atmel 520
Can you upload high resolution pictures of
On 20 Jan 2014, at 10:55 PM, Andy Walls wrote:
> Robert Longbottom wrote:
>>
>> Hi,
>>
>> I've just bought one of these cards which is based on the Conexant
>> Fusion 878A chip thinking it would just work under Linux being
>> bttv-based. Unfortunately (for me) it's not and it is just picked
Robert Longbottom wrote:
>
>Hi,
>
>I've just bought one of these cards which is based on the Conexant
>Fusion 878A chip thinking it would just work under Linux being
>bttv-based. Unfortunately (for me) it's not and it is just picked up
>as
>a generic unknown card by the bttv driver.
>
>Does anyon
Hi,
I've just bought one of these cards which is based on the Conexant
Fusion 878A chip thinking it would just work under Linux being
bttv-based. Unfortunately (for me) it's not and it is just picked up as
a generic unknown card by the bttv driver.
Does anyone have one of these that is working
19 matches
Mail list logo
