Hi Arindam,
On Wed, Apr 27, 2011 at 12:49 AM, Nath, Arindam arindam.n...@amd.com wrote:
Hi Andrei,
Is there any more change to your V4 than the ones we discussed yesterday? I
did the mod we discussed, but seems like the driver only sends CMD23 now, not
Auto CMD23.
Two things V4 does,
Guess I will have to hand modify my code based on your V4 patches again, I
don't think your patches are based on top of mine.
Thanks,
Arindam
-Original Message-
From: Andrei Warkentin [mailto:andr...@motorola.com]
Sent: Wednesday, April 27, 2011 11:30 AM
To: Nath, Arindam
Cc:
On Wed, Apr 27, 2011 at 1:02 AM, Nath, Arindam arindam.n...@amd.com wrote:
Guess I will have to hand modify my code based on your V4 patches again, I
don't think your patches are based on top of mine.
Thanks,
Arindam
Just verify these blobs look similar -
+ else if
On 26/04/11 16:19, Arnd Bergmann wrote:
On Saturday 23 April 2011, John Stultz wrote:
From: David Dingdavid.j.d...@motorola.com
CC: Chris Ballc...@laptop.org
CC: Arnd Bergmanna...@arndb.de
CC: Dima Zavind...@android.com
Signed-off-by: Bentao Zoubz...@motorola.com
Signed-off-by: David
On Wed, Apr 27, 2011 at 3:16 AM, Adrian Hunter adrian.hun...@nokia.com wrote:
On 26/04/11 16:19, Arnd Bergmann wrote:
On Saturday 23 April 2011, John Stultz wrote:
From: David Dingdavid.j.d...@motorola.com
CC: Chris Ballc...@laptop.org
CC: Arnd Bergmanna...@arndb.de
CC: Dima
On Fri, Apr 22, 2011 at 01:13:28PM -0700, Philip Rakity wrote:
The PXA168, PXA910, and MMP2 SoC have the ability to adjust the SD/MMC
clock. This feature is useful and required depending on the board
design. Add infrastructure to support SD clock tuning.
It just adds fields to a structure
On Wed, Apr 20, 2011 at 5:30 AM, Arindam Nath arindam.n...@amd.com wrote:
Host Controller v3.00 adds another Capabilities register. Apart
from other things, this new register indicates whether the Host
Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec
doesn't mention about
Hi Zhangfei,
[...]
Hi, Arindam
The uhs card works OK,
However after use uhs card, the io voltage keeps 1.8v, and
mmc_send_app_op_cond will return error, so no chance to go back to
3.3v.
The result is hs card can not be detected after using uhs card.
Also some hs card have timeout issue
From: Ben Dooks ben-li...@fluff.org
It seems that under certain circumstances that the sdhci_tasklet_finish()
call can be entered with mrq-cmd set to NULL, causing the system to crash
with a NULL pointer de-reference.
Unable to handle kernel NULL pointer dereference at virtual address
From: Dimitris Papastamos d...@opensource.wolfsonmicro.com
It seems that under certain circumstances the sdhci_tasklet_finish()
call can be entered with mrq set to NULL, causing the system to crash
with a NULL pointer de-reference.
Seen on S3C6410 system.
Signed-off-by: Dimitris Papastamos
Begin forwarded message:
From: Philip Rakity prak...@marvell.com
Date: April 22, 2011 1:18:33 PM PDT
To: linux-mmc@vger.kernel.org linux-mmc@vger.kernel.org
Cc: Zhangfei Gao zg...@marvell.com
Subject: [PATCH] sdhci: sdhci-pxa.c: Add post reset processing for chip
specific registers
On Wed, Apr 27, 2011 at 8:23 AM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
I've had this pair of patches sitting in my tree for a while now (I
believe they were previously posted) providing stability improvements in
sdhci on my systems. Having looked through the code I believe but
Hi,
On Wed, Apr 27 2011, Andrei Warkentin wrote:
On Wed, Apr 27, 2011 at 8:23 AM, Mark Brown
broo...@opensource.wolfsonmicro.com wrote:
I've had this pair of patches sitting in my tree for a while now (I
believe they were previously posted) providing stability improvements in
sdhci on my
On Wed, Apr 27, 2011 at 04:41:27PM -0400, Chris Ball wrote:
No, I think Mark's saying there's a race of:
* the successful completion interrupt fires, and
* the host timer fires to signify timeout due to *lack* of an interrupt
(via sdhci_timeout_timer()). i.e., the completion interrupt
Hi Mark,
On Wed, Apr 27 2011, Mark Brown wrote:
Ben Dooks (1):
MMC: SDHCI: Check mrq-cmd in sdhci_tasklet_finish
Dimitris Papastamos (1):
MMC: SDHCI: Check mrq != NULL in sdhci_tasklet_finish
Thanks. I've merged Ben's patch for .39, and also:
From: Chris Ball c...@laptop.org
Hi Philip,
2011/4/26 Philip Rakity prak...@marvell.com:
Barry,
How are interrupts from SDIO devices handled ? SDIO devices use one of the
pins to signal a interrupt to the host when data is availabe.
Good question. in fact, it is impossible to support both sharing all
data bus and sdio
2011/4/28 Barry Song 21cn...@gmail.com:
Hi Philip,
2011/4/26 Philip Rakity prak...@marvell.com:
Barry,
How are interrupts from SDIO devices handled ? SDIO devices use one of the
pins to signal a interrupt to the host when data is availabe.
Good question. in fact, it is impossible to
I have also reviewed Arindam's SD3.0 patches and looks good to me. Although
I haven't tested those yet.
Regards,
Subhash
-Original Message-
From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
ow...@vger.kernel.org] On Behalf Of Philip Rakity
Sent: Tuesday, April 26, 2011 7:51 PM
On Wed, Apr 27, 2011 at 6:17 AM, Nath, Arindam arindam.n...@amd.com wrote:
Hi Zhangfei,
[...]
Hi, Arindam
The uhs card works OK,
However after use uhs card, the io voltage keeps 1.8v, and
mmc_send_app_op_cond will return error, so no chance to go back to
3.3v.
The result is hs card can
On Wed, Apr 20, 2011 at 5:30 AM, Arindam Nath arindam.n...@amd.com wrote:
According to the Host Controller spec v3.00, setting Preset Value Enable
in the Host Control2 register lets SDCLK Frequency Select, Clock Generator
Select and Driver Strength Select to be set automatically by the Host
Hi Zhangfei,
-Original Message-
From: zhangfei gao [mailto:zhangfei@gmail.com]
Sent: Thursday, April 28, 2011 8:48 AM
To: Nath, Arindam
Cc: c...@laptop.org; linux-mmc@vger.kernel.org; prak...@marvell.com;
subha...@codeaurora.org; Su, Henry; Lu, Aaron; anath@gmail.com
Hi Zhangfei,
-Original Message-
From: zhangfei gao [mailto:zhangfei@gmail.com]
Sent: Thursday, April 28, 2011 10:47 AM
To: Nath, Arindam
Cc: c...@laptop.org; linux-mmc@vger.kernel.org; prak...@marvell.com;
subha...@codeaurora.org; Su, Henry; Lu, Aaron; anath@gmail.com
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