From: yongd
In the current code logic, sdhci_add_host() will enable the polling
method (set MMC_CAP_NEEDS_POLL) for a removable card (MMC_CAP_
NONREMOVABLE is not set) whose host's internal card detection method
is disabled for some reason (SDHCI_QUIRK_BROKEN_CARD_DETECTION is set).
However, thi
On Mon, Sep 24, 2012 at 09:22:22AM +0200, Sascha Hauer wrote:
> The first patch is a generic sdhci driver cleanup change, the others
> are i.MX specific, adding 8bit bus support and fix version register
> readout.
>
> Sascha
>
>
> S
On Mon, Sep 24, 2012 at 09:22:24AM +0200, Sascha Hauer wrote:
> The i.MX ESDHC controller version register is a mess:
>
> - i.MX25 has a v1 controller which identifies itself as v2
> - i.MX6Q has a v3 controller which identifies itself as v4
> - i.MX35,51,53 have v2 controllers which identify them
On Tue, Sep 25, 2012 at 11:35:14AM +0900, Jaehoon Chung wrote:
> On 09/24/2012 04:22 PM, Sascha Hauer wrote:
> > /*
> > * If your platform has 8-bit width support but is not a v3 controller,
> > * or if it requires special setup code, you should implement that in
> > -* platform_8
On 09/24/2012 04:22 PM, Sascha Hauer wrote:
> The 8bit in the function name is misleading. When set, it will be
> used to set the bus width, regardless of whether 8bit or another
> bus width is requested, so change the function name to
> platform_bus_width.
>
> Signed-off-by: Sascha Hauer
> ---
>
> Hi,
>
> On Fri, Sep 21 2012, r66...@freescale.com wrote:
> > --- a/drivers/mmc/host/sdhci-of-esdhc.c
> > +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> > @@ -143,6 +143,35 @@ static void esdhc_of_resume(struct sdhci_host
> > *host) } #endif
> >
> > +static const
2012/9/24 Philip Rakity :
>
> On Sep 24, 2012, at 1:15 AM, Kevin Liu wrote:
>
>> From: Kevin Liu
>>
>> Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since
>> SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base
>> clock value. It return a fixed pre-set value like 200 on
>> some sdhci-px
On Sep 24, 2012, at 1:15 AM, Kevin Liu wrote:
> From: Kevin Liu
>
> Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since
> SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base
> clock value. It return a fixed pre-set value like 200 on
> some sdhci-pxav3 based platforms like MMP3 while
On Sep 24, 2012, at 1:15 AM, Kevin Liu wrote:
> From: Kevin Liu
>
> regulator_get() returns NULL when CONFIG_REGULATOR not defined,
> which should not print out the warning.
>
> Signed-off-by: Bin Wang
> Signed-off-by: Kevin Liu
> ---
> drivers/mmc/host/sdhci.c | 18 --
> 1
On Mon, Sep 24, 2012 at 8:17 AM, Arnd Bergmann wrote:
>
>> static inline void mmc_delay(unsigned int ms)
>> {
>> msleep(ms);
>> }
>
> That would be my preferred choice, unless someone has specific issues with
> this.
If we're going to do that, then just get rid of mmc_delay and replace
On Sep 23, 2012, at 10:13 PM, Huang Changming-R66093 wrote:
>
>
> Best Regards
> Jerry Huang
>
>
>> -Original Message-
>> From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
>> ow...@vger.kernel.org] On Behalf Of Huang Changming-R66093
>> Sent: Monday, September 24, 2012 10:37 AM
On Monday 24 September 2012, Chunhe Lan wrote:
> OK. As you have mentioned, it would been modified to such:
>
> static inline void mmc_delay(unsigned int ms)
> {
> if (ms < 1000 / HZ) {
> cond_resched();
> msleep(ms);
> } else {
>
On Mon, Sep 24, 2012 at 11:26:55AM +, Hebbar, Gururaja wrote:
> On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> > On Fri, Sep 21, 2012 at 08:27:07AM +, Hebbar, Gururaja wrote:
> > > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > > This series adds DMA Engine support for
On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> On Fri, Sep 21, 2012 at 08:27:07AM +, Hebbar, Gururaja wrote:
> > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > This series adds DMA Engine support for AM33xx, which uses
> > > an EDMA DMAC. The EDMA DMAC has been previously
On 21 September 2012 05:07, Kevin Liu wrote:
> From: Kevin Liu
>
> If host support asynchronous interrupt and sdio device has enabled it,
> then enable/disable asynchronous interrupt on host when enable/disable
> sdio irq.
>
> Signed-off-by: Kevin Liu
> ---
> drivers/mmc/host/sdhci.c | 15 +++
On 21 September 2012 05:07, Kevin Liu wrote:
> From: Kevin Liu
>
> Enable asynchronous interrupt on device by default if both host
> and device support it and clock gating is allowed.
>
> If asynchronous interrupt is enabled, then no need to switch bus
> width to 1bit before suspend.
>
> Signed-o
From: Kevin Liu
Preset value support was added by 4d55c5a1.
But preset value is enabled after setting clock finished,
which means the clock is still set by driver firstly and
then switch to preset value at this point. So the
driver setting beforehand is useless and unnecessary.
What's more, driv
From: Kevin Liu
Both of MMC_TIMING_LEGACY and MMC_TIMING_UHS_SDR12 are defined
to 0. And ios->timing is set to MMC_TIMING_LEGACY during power up.
But set_ios can't distinguish these two timing if host support
spec 3.0. Just adjust timing values to be different can resolve
this issue without any o
From: Kevin Liu
regulator_get() returns NULL when CONFIG_REGULATOR not defined,
which should not print out the warning.
Signed-off-by: Bin Wang
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/driv
From: Kevin Liu
Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since
SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base
clock value. It return a fixed pre-set value like 200 on
some sdhci-pxav3 based platforms like MMP3 while return 0
on the other sdhci-pxav3 based platforms.
So we ena
From: Kevin Liu
The clock rate set to the sdh controller may not exactly as requested
by the mmc core, this patch make the clock rate saved in the mmc_ios
and sdhci_host updated with the actual setting as in the controller. Thus
"/sys/kernel/debug/mmcx/ios" and card detect prints can show the cor
From: Kevin Liu
With preset value enabled, there are two continuous times
of sd clock disable/enable. They can be combined into one
to save time and make code cleaner.
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 29 +
1 files changed, 9 insertions(+),
From: Kevin Liu
Use voltage range as below rather than a specific value
3.3v: (3.2v, 3.4v)
3.0v: (2.9v, 3.1v)
1.8v: (1.65v, 1.95v)
Signed-off-by: Jialing Fu
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff
From: Kevin Liu
Commands without data transfer like cmd5/cmd7 will use previous
transfer mode setting, which may lead to error since some bits
may have been set unexpectedly.
For example, cmd5 following cmd18/cmd25 will have timeout error
since audo cmd23 has been enabled.
Signed-off-by: Jialing
This patchset does as follows:
[PATCH v2 1/8] mmc: sdhci: fix transfer mode setting bug for cmds w/o data
transfer
[PATCH v2 2/8] mmc: sdhci: set regulator min/max voltage according to spec
[PATCH v2 3/8] mmc: sdhci: refine code for sd clock disable/enable in set ios
[PATCH v2 4/8] mmc: sdhci: ke
The 8bit in the function name is misleading. When set, it will be
used to set the bus width, regardless of whether 8bit or another
bus width is requested, so change the function name to
platform_bus_width.
Signed-off-by: Sascha Hauer
---
drivers/mmc/host/sdhci-pci.c |4 ++--
drivers/mmc/ho
The first patch is a generic sdhci driver cleanup change, the others
are i.MX specific, adding 8bit bus support and fix version register
readout.
Sascha
Sascha Hauer (3):
mmc: sdhci: rename platform_8bit_width to platform_bus_
The i.MX ESDHC controller version register is a mess:
- i.MX25 has a v1 controller which identifies itself as v2
- i.MX6Q has a v3 controller which identifies itself as v4
- i.MX35,51,53 have v2 controllers which identify themselves correctly
Additionally on i.MX the register is located at offset
The i.MX esdhc has a nonstandard bit layout for the SDHCI_HOST_CONTROL
register. To support 8bit bus width on i.MX populate the platform_bus_width
callback. This is tested on an i.MX25, but should according to the datasheets
work on the other i.MX using this hardware aswell. The i.MX6, while having
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