On Wed, Sep 26, 2012 at 7:38 PM, Kevin Liu wrote:
> From: Kevin Liu
>
> The clock rate set to the sdh controller may not exactly as requested
> by the mmc core, this patch make the clock rate saved in the mmc_ios
> and sdhci_host updated with the actual setting as in the controller. Thus
> "/sys/
On Wed, Sep 26, 2012 at 7:38 PM, Kevin Liu wrote:
> From: Kevin Liu
>
> Commands without data transfer like cmd5/cmd7 will use previous
> transfer mode setting, which may lead to error since some bits
> may have been set unexpectedly.
> For example, cmd5 following cmd18/cmd25 will have timeout er
On Tue, Sep 25, 2012 at 02:13:10AM -0700, Yong Ding wrote:
[...]
> So, in all, u are right if with my current patch, some host drivers need
> some improvement to add MMC_CAP_NEEDS_POLL when it is actually needed.
> But I think this shall be the right way to follow. Or, we might enable
> polling for
2012/9/26 Girish K S :
> On 26 September 2012 20:38, Kevin Liu wrote:
>> From: Kevin Liu
>>
>> Host controller must enable 1.8v signal for UHS modes.
>> Otherwise UHS modes won't take effect.
>> But mmc core does NOT switch to 1.8v for DDR50 mode.
>> So enable the 1.8v signal for mmc DDR50 mode i
Looks good
Reviewed By:- Girish K S
On 26 September 2012 15:02, wrote:
> From: Jerry Huang
>
> CMD23 causes lots of errors in kernel on some freescale SoCs
> (P1020, P1021, P1022, P1024, P1025 and P4080) when MMC card used,
> which is because these controllers does not support CMD23,
> even on
On Wed, Sep 26, 2012 at 08:26:19AM +, Hebbar, Gururaja wrote:
> On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> > On Fri, Sep 21, 2012 at 08:27:07AM +, Hebbar, Gururaja wrote:
> > > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > > This series adds DMA Engine support for
Reviewed By: Girish K S
On 26 September 2012 20:38, Kevin Liu wrote:
> From: Kevin Liu
>
> Both of MMC_TIMING_LEGACY and MMC_TIMING_UHS_SDR12 are defined
> to 0. And ios->timing is set to MMC_TIMING_LEGACY during power up.
> But set_ios can't distinguish these two timing if host support
> spec
On 26 September 2012 20:38, Kevin Liu wrote:
> From: Kevin Liu
>
> Host controller must enable 1.8v signal for UHS modes.
> Otherwise UHS modes won't take effect.
> But mmc core does NOT switch to 1.8v for DDR50 mode.
> So enable the 1.8v signal for mmc DDR50 mode in host
> driver.
>
> Signed-off
Reviewed By: Girish K S
On 26 September 2012 20:38, Kevin Liu wrote:
> From: Kevin Liu
>
> Commands without data transfer like cmd5/cmd7 will use previous
> transfer mode setting, which may lead to error since some bits
> may have been set unexpectedly.
> For example, cmd5 following cmd18/cmd25
From: Kevin Liu
Because sdhci can do the same thing so no need to implement this.
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci-pxav3.c | 39 ---
1 files changed, 0 insertions(+), 39 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers
From: Kevin Liu
Host controller must enable 1.8v signal for UHS modes.
Otherwise UHS modes won't take effect.
But mmc core does NOT switch to 1.8v for DDR50 mode.
So enable the 1.8v signal for mmc DDR50 mode in host
driver.
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c |9 -
From: Kevin Liu
Add the function since MMC 1.8v signal voltage switch don't need
the same switch sequence requirements as SD/SDIO.
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 46 +-
1 files changed, 45 insertions(+), 1 deletions(-)
dif
From: Kevin Liu
Mmc does NOT have special sequence requirements for 1.8v
signal voltage setting compared to sd and sdio.
Add a new 1.8v flag for mmc so as to use the same
start_signal_voltage_switch interface.
Signed-off-by: Kevin Liu
---
drivers/mmc/core/mmc.c |3 ++-
include/linux/mmc/
From: Kevin Liu
Signed-off-by: Bin Wang
Signed-off-by: Philip Rakity
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci-pxav3.c | 25 +
include/linux/platform_data/pxa_sdhci.h |2 ++
2 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/driver
From: Kevin Liu
Some soc/platform need specific handling for signal voltage
switch. For example, mmp2/mmp3 need to set the AIB IO domain
control register accordingly.
Signed-off-by: Bin Wang
Signed-off-by: Philip Rakity
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 17 +++
From: Kevin Liu
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci-pxav3.c |2 ++
include/linux/platform_data/pxa_sdhci.h |2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 75cc79b..04db9f
From: Kevin Liu
Preset value support was added by 4d55c5a1.
But preset value is enabled after setting clock finished,
which means the clock is still set by driver firstly and
then switch to preset value at this point. So the
driver setting beforehand is useless and unnecessary.
What's more, driv
From: Kevin Liu
Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since
SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base
clock value. It return a fixed pre-set value like 200 on
some sdhci-pxav3 based platforms like MMP3 while return 0
on the other sdhci-pxav3 based platforms.
So we ena
From: Kevin Liu
Both of MMC_TIMING_LEGACY and MMC_TIMING_UHS_SDR12 are defined
to 0. And ios->timing is set to MMC_TIMING_LEGACY during power up.
But set_ios can't distinguish these two timing if host support
spec 3.0. Just adjust timing values to be different can resolve
this issue without any o
From: Kevin Liu
regulator_get() returns NULL when CONFIG_REGULATOR not defined,
which should not print out the warning.
Reviewed-by: Philip Rakity
Signed-off-by: Bin Wang
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 18 --
1 files changed, 12 insertions(+), 6 del
From: Kevin Liu
The clock rate set to the sdh controller may not exactly as requested
by the mmc core, this patch make the clock rate saved in the mmc_ios
and sdhci_host updated with the actual setting as in the controller. Thus
"/sys/kernel/debug/mmcx/ios" and card detect prints can show the cor
From: Kevin Liu
With preset value enabled, there are two continuous times
of sd clock disable/enable. They can be combined into one
to save time and make code cleaner.
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 29 +
1 files changed, 9 insertions(+),
From: Kevin Liu
Use voltage range as below rather than a specific value
3.3v: (3.2v, 3.4v)
3.0v: (2.9v, 3.1v)
1.8v: (1.65v, 1.95v)
Signed-off-by: Jialing Fu
Signed-off-by: Kevin Liu
---
drivers/mmc/host/sdhci.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff
From: Kevin Liu
Commands without data transfer like cmd5/cmd7 will use previous
transfer mode setting, which may lead to error since some bits
may have been set unexpectedly.
For example, cmd5 following cmd18/cmd25 will have timeout error
since audo cmd23 has been enabled.
Signed-off-by: Jialing
This patchset does as follows:
[PATCH v4 01/15] mmc: sdhci: fix transfer mode setting bug for cmds w/o data
transfer
[PATCH v4 02/15] mmc: sdhci: set regulator min/max voltage according to spec
[PATCH v4 03/15] mmc: sdhci: refine code for sd clock disable/enable in set ios
[PATCH v4 04/15] mmc: s
On Wed, Sep 12, 2012 at 17:32:38, Hebbar, Gururaja wrote:
> On Wed, Sep 12, 2012 at 14:19:51, S, Venkatraman wrote:
> > On Tue, Sep 4, 2012 at 6:39 PM, Hebbar, Gururaja
> > wrote:
> > > HSMMC IP on AM33xx need a special setting to handle High-speed cards.
> > > Other platforms like TI81xx, OMAP4
On Tue, Sep 25, 2012 at 11:19 AM, Ulf Hansson wrote:
> I am not sure how long we should wait for eMMC 4.5 to be tested. Until
> testing is resolved the eMMC 4.3 and onwards are having a broken
> suspend sequence using SLEEP, which I think is really bad.
To me this sounds like a case for even add
Hi Kobayashi,
On Tue, Sep 25 2012, Tetsuyuki Kobayashi wrote:
> (09/19/2012 11:50 AM), Tetsuyuki Kobayashi wrote:
>> (2012/08/22 15:49), Guennadi Liakhovetski wrote:
>>> On some systems, e.g., kzm9g, MMCIF interfaces can produce spurious
>>> interrupts without any active request. To prevent the Oo
Hi Philip,
2012/9/25 Philip Rakity :
>
>
> On Sep 25, 2012, at 12:30 AM, Ulf Hansson wrote:
>
>> Hi Johan,
>>
>> An overall comment; would it be possible to include this patch as a
>> piece of patch 1/2 "mmc: core: Proper signal voltage switch".
>> They seems like quite tight connected.
>>
>> Any
On Fri, Sep 21, 2012 at 23:52:11, Porter, Matt wrote:
> On Fri, Sep 21, 2012 at 08:27:07AM +, Hebbar, Gururaja wrote:
> > On Thu, Sep 20, 2012 at 20:13:33, Porter, Matt wrote:
> > > This series adds DMA Engine support for AM33xx, which uses
> > > an EDMA DMAC. The EDMA DMAC has been previously
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