This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's have different versions of DWMMC controller.
So dwmmc device nodes moved from Exynos5 SOC's common dts file to
SOC specific dts file.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source.
Changes since V1: none
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by
The intent was to test if a flag was set. In the current code the
conditions are always true.
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com
---
Static checker stuff. Untested.
diff --git a/drivers/mmc/host/sdhci-bcm-kona.c
b/drivers/mmc/host/sdhci-bcm-kona.c
index 87175f9..9ffac0b
Acked-by: Sonic Zhang sonic.zh...@analog.com
-Original Message-
From: Jingoo Han [mailto:jg1@samsung.com]
Sent: Wednesday, August 21, 2013 1:56 PM
To: 'Chris Ball'
Cc: linux-mmc@vger.kernel.org; Zhang, Sonic; 'Jingoo Han'
Subject: [PATCH RESEND] mmc: mmc_spi: use spi_get_drvdata() and
On Wed, 21 Aug 2013, wei_w...@realsil.com.cn wrote:
From: Wei WANG wei_w...@realsil.com.cn
The default phase can meet most cards' requirement, but it is not the
optimal one. In some extreme situation, the rx phase point produced by
the following tuning process will drift quite a distance.
--- Original Message ---
Sender : yuvaraj...@gmail.comyuvaraj...@gmail.com
Date : Aug 21, 2013 12:07 (GMT+05:30)
Title : [PATCH V2 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
From: Yuvaraj Kumar C D
Exynos5 series SOC's have different versions of DWMMC controller.
So dwmmc
Am 21.08.2013 10:24, schrieb Dan Carpenter:
The intent was to test if a flag was set. In the current code the
conditions are always true.
I guess that it worked before ...
That leaves the Question: are the tests needed at all ?
re,
wh
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com
On Wed, Aug 21, 2013 at 10:57:57AM +0200, walter harms wrote:
Am 21.08.2013 10:24, schrieb Dan Carpenter:
The intent was to test if a flag was set. In the current code the
conditions are always true.
I guess that it worked before ...
That leaves the Question: are the tests needed at
On 20 August 2013 16:07, Alim Akhtar alim.akh...@gmail.com wrote:
Hi Yuvaraj
On Mon, Aug 19, 2013 at 12:06 PM, Yuvaraj Kumar C D
yuvaraj...@gmail.com wrote:
Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch
Hi Seungwon Jeon,
On Monday 20 August 2013, Prabu Thangamuthu wrote:
Hi Seungwon Jeon,
On Tue, August 20, 2013, Seungwon Jeon wrote:
On Tue, August 20, 2013, Prabu Thangamuthu wrote:
Hi Arnd, Seungwon Jeon,
On Tue, August 20, 2013, Seungwon Jeon wrote:
Hi Prabu,
On Tue,
Synopsys DW_MMC IP core supports Internal DMA Controller with 64-bit address
mode from IP version 2.70a onwards.
Updated the driver to support IDMAC 64-bit addressing mode.
Tested the features in DW_MMC IP core v2.70a and v2.40a with HAPS-51 setup and
driver is working fine.
Signed-off-by:
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:05:33 Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Is this patch a v3 of
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:13:53 Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
What are the
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:07:38 yuvaraj...@gmail.com wrote:
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should
When card is in cpu polling mode to detect card present. Card detecting
task will be scheduled about once every second. When card is busy in large
file transfer, detecting task will be hang and call trace will be prompt.
In this case, when card is busy assume that card is present and just return
On Wed, Aug 21, 2013 at 4:04 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:07:38 yuvaraj...@gmail.com wrote:
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a
Hi Doug,
Do you have any update for this series?
Please let me know.
Thanks,
Seungwon Jeon
On Sat, August 10, 2013, Doug Anderson wrote:
This series of patches addresses some suspend/resume problems with
dw_mmc on exynos platforms, espeically exynos5420. Since
suspend/resume is not fully
On Wed, Aug 21, 2013 at 3:40 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:05:33 Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible
While speed mode is changed, CMD13 cannot be guaranteed.
According to the spec., it is not recommended to use CMD13
to check the busy completion of the timing change.
If CMD13 is used in this case, CRC error must be ignored.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
From 029a839ddf6f13a1e1a8bf4d4bc32b67712593ec Mon Sep 17 00:00:00 2001
From: Seungwon Jeon tgih@samsung.com
Date: Wed, 21 Aug 2013 17:30:02 +0900
Subject: [PATCH 3/3] mmc: fix the remove of blk on suspend
As mmc_cleanup_queue() is moved, NULL pointer access to card of
mmc_queue is happened
Currently there is no mmc_power_off() when resume failed.
Somehow, state from mmc_power_on() will be kept. This change
makes a pair with its use in case of failure.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/core/mmc.c |3 +++
drivers/mmc/core/sd.c |3 +++
These patches were V3 versions of below patches.
1.[PATCH 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
http://www.spinics.net/lists/linux-samsung-soc/msg21602.html
2.[PATCH 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source to SOC specific device tree source.
Changes since V2:
1.remove from
Exynos's host has divider logic before 'cclk_in' to controller core.
It means that actual clock rate of ciu clock comes from this divider
value. So, source clock should be adjusted along with 'ciu_div' which
indicates the host's divider ratio. Setting clock rate basically fits
the required speed.
This patch set includes the tuning scheme for high speed mode such as HS200.
Specially, the support of HS200 mode is introduced with exynos's host
And also, it addresses the some error handling and code clean-up.
Seungwon Jeon (14):
mmc: dw_mmc: add support tuning scheme
mmc: dw_mmc:
As host controller can support eMMC's HS200 mode at
1.8V or 1.2V, these capability will be added.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
.../devicetree/bindings/mmc/synopsis-dw-mshc.txt |5 +
drivers/mmc/host/dw_mmc.c |6 ++
2 files
For the speed modes HS200 and SDR104, tuning is needed
to determine the correct sampling point. Actual tuning
procedure is provided by specific host controller driver.
This patch defines the tuning command and tuning data.
Additionally, 'struct dw_mci_slot' is moved to header file
to consider the
Implements variable delay tuning. In this change,
exynos host can determine the correct sampling point
for the HS200 and SDR104 speed mode.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/host/dw_mmc-exynos.c | 124 ++
1 files changed, 124
Both f_max and f_min will be informed for core layer to request
valid clock rate. But current setting from 'host-bus_hz' may
not represent the max/min frequency properly. Even if host can
actually support high speed than bus_hz, core layer will not
request clock rate over bus_hz. Basically,
This change helps to choose msize, rx_watermark and
tx_watermak depending on block size for IDMAC mode.
For SDIO block size can be variable, so if these values
are set incorrectly, card clock may stop.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/host/dw_mmc.c | 74
From 1b6f8985c0e77ac0022f86d80408cbc7b5b01ae1 Mon Sep 17 00:00:00 2001
From: Seungwon Jeon tgih@samsung.com
Date: Tue, 13 Aug 2013 16:03:18 +0900
Subject: [PATCH 08/14] mmc: dw_mmc: control card read threshold
Card Read Threshold should be ensured that the card clock does
not stop in the
Even if response error is detected in case data command,
data transfer is continued. It means that data can live
in FIFO. Current handling just breaks out the request
when seeing the command error. This causes kernel panic
in dw_mci_read_data_pio [host-data = NULL]. And also,
FIFO should be
Main change corresponds to dw_mci_command_complete.
And EBE is divided into read and write.
Some minor changes make the code readability
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/host/dw_mmc.c | 147 ++---
1 files changed, 84
In error cases, DTO interrupt may or may not be generated depending
on remained data. Stop/Abort command ensures DTO generation for that
situation. Currently if 'stop' field of data is empty, there is no
stop/abort command. So, it could hang waiting DTO. This change rein-
forces these cases.
First, compiling warning along with previous change is removed.
[drivers/mmc/host/dw_mmc.c:1890:7: warning: unused variable 'ctrl']
And with the recommendation in manual, IDMAC software reset is followed
by dma-reset of the CTRL register in order to terminate the transfer.
Signed-off-by: Seungwon
In IDMAC mode EVENT_XFER_COMPLETE is set when RI/TI of last descriptor
is done. So if errors are happened in the middle of data transfers,
'dw_mci_stop_dma' during error handing can be called and eventually
prevents this flag to be set.
This results in permanent wait for EVENT_XFER_COMPLETE in
There are three resets in CTRL register.
FIFO reset is especially used in several points with the
same routine. It could be replaced with one function and
the others may be applied similarly if needed.
So, mci_wait_reset is modified to allow various bit field
of reset
Signed-off-by: Seungwon Jeon
'supports-highspeed' is not one of the quirks but is a capability.
So, it's removed from quirks.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
drivers/mmc/host/dw_mmc.c |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c
Hi Dan,
Good catch. This fix is already in the ARM: mmc: fix NONREMOVABLE test in
sdhci-bcm-kona patch that is part of the git pull request sent to armsoc
yesterday:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-August/193422.html
Thanks,
Csd
-Original Message-
From:
On Wed, Aug 21, 2013 at 6:49 AM, Seungwon Jeon tgih@samsung.com wrote:
Implements variable delay tuning. In this change,
exynos host can determine the correct sampling point
for the HS200 and SDR104 speed mode.
Signed-off-by: Seungwon Jeon tgih@samsung.com
---
Seungwon,
On Wed, Aug 21, 2013 at 4:48 AM, Seungwon Jeon tgih@samsung.com wrote:
Hi Doug,
Do you have any update for this series?
Please let me know.
Thank you for the ping. The changes requested looked big enough that
I knew I was going to have to devote some time to looking this all
On Wed, Aug 21, 2013 at 6:49 AM, Seungwon Jeon tgih@samsung.com wrote:
Exynos's host has divider logic before 'cclk_in' to controller core.
It means that actual clock rate of ciu clock comes from this divider
value. So, source clock should be adjusted along with 'ciu_div' which
indicates
On Wednesday 21 August 2013 12:22 AM, Hein Tibosch wrote:
Hi,
[ added some people from TI ]
On 8/7/2013 6:05 PM, majianpeng wrote:
V2:
clean up code.
V1:
www.mail-archive.com/linux-omap@vger.../msg93239.html‎
We found a problem when we removed a working sd card that the
On Fri, 2013-08-16 at 16:36 -0600, Stephen Warren wrote:
On 08/14/2013 10:48 AM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Add bindings for SD/MMC for SOCFPGA.
diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
On Mon, Aug 12, 2013 at 4:45 PM, Grant Grundler grund...@chromium.org wrote:
I've been working on an task mmcqd/0:84 blocked for more than 120
seconds panic for the past month or so in the chromeos-3.4 kernel
tree. Stack trace below. Feel free to tell me fixed in v3.x. :)
I've added this
Seungwon,
On Mon, Aug 12, 2013 at 12:14 AM, Seungwon Jeon tgih@samsung.com wrote:
On Sat, August 10, 2013, Doug Anderson wrote:
Seungwon and Jaehoon,
On Fri, Aug 9, 2013 at 6:32 AM, Seungwon Jeon tgih@samsung.com wrote:
On Wed, August 07, 2013, Doug Anderson wrote:
The dw_mmc
On Thursday, August 22, 2013, Grant Grundler wrote:
On Wed, Aug 21, 2013 at 6:49 AM, Seungwon Jeon tgih@samsung.com wrote:
Exynos's host has divider logic before 'cclk_in' to controller core.
It means that actual clock rate of ciu clock comes from this divider
value. So, source clock
On Wed, August 21, 2013, Grant Grundler
On Wed, Aug 21, 2013 at 6:49 AM, Seungwon Jeon tgih@samsung.com wrote:
Implements variable delay tuning. In this change,
exynos host can determine the correct sampling point
for the HS200 and SDR104 speed mode.
Signed-off-by: Seungwon Jeon
51 matches
Mail list logo
