-Original Message-
From: Barry Song [mailto:21cn...@gmail.com]
Sent: Thursday, August 21, 2014 6:09 PM
To: Romain Izard
Cc: linux-mmc@vger.kernel.org; Minda Chen; DL-SHA-WorkGroupLinux
Subject: Re: [PATCH v2] mmc: sdhci-sirf: fix 8bit width enable by overwriting
set_bus_width
-Original Message-
From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
Sent: Monday, August 18, 2014 7:58 PM
To: Barry Song
Cc: Chris Ball; linux-mmc; linux-arm-ker...@lists.infradead.org; DL-SHA-
WorkGroupLinux; Minda Chen; Barry Song
Subject: Re: [PATCH] mmc: core: sd: check card
From: Shinobu Uehara shinobu.uehara...@renesas.com
In some controllers, when performing a multiple block read of
one or two blocks, depending on the timing with which the
response register is read, the response value may not
be read properly.
MMC_CAP2_NO_MULTI_READ flags disable all multiple
From: Kuninori Morimoto kuninori.morimoto...@renesas.com
Basically, SD_BUF0 Tx/Rx addresses are same
in normal TMIO controller,
but, it is different on Renesas R-Car SDHI controller
if it uses DMAC
(Rx address needs to add 0x2000 to Tx address)
This patch adds new .dma_rx_offset and cares it
From: Shinobu Uehara shinobu.uehara...@renesas.com
Next card access will be always
error if it didn't clear error status
Tested-by: Nguyen Xuan Nui nx-...@jinso.co.jp
Tested-by: Hiep Cao Minh cm-h...@jinso.co.jp
Signed-off-by: Shinobu Uehara shinobu.uehara...@renesas.com
Signed-off-by: Kuninori
From: Shinobu Uehara shinobu.uehara...@renesas.com
Renesas SDHI has Multiple Block Transfer Mode settings
on SD_CMD register which controls CMD12 automatically.
This patch cares it, because
CMD12 is not needed when CMD53 (= SD_IO_RW_EXTENDED)
[Kuninori Morimoto: tidyuped for upstreaming
From: Shinobu Uehara shinobu.uehara...@renesas.com
Renesas R-Car SDHI should set reserved bits
on CTL_SDIO_STATUS register when writing.
This patch adds new TMIO_MMC_SDIO_STATUS_QUIRK flags
for this purpose
[Kuninori Morimoto: tidyuped for upstreaming
enabled this flags for
From: Kuninori Morimoto kuninori.morimoto...@renesas.com
This patch adds new TMIO_MMC_HAVE_CTL_DMA_REG flag,
and remove Renesas specific #ifdef from tmio driver
Tested-by: Nguyen Xuan Nui nx-...@jinso.co.jp
Tested-by: Hiep Cao Minh cm-h...@jinso.co.jp
Signed-off-by: Kuninori Morimoto
From: Kuninori Morimoto kuninori.morimoto...@renesas.com
TMIO clock is set via tmio_mmc_set_clock() - tmio_mmc_clk_start(),
and SCLKEN bit will be set on tmio_mmc_clk_start().
It is not needed on tmio_mmc_set_clock() function.
The required clock setting will not be able to set
in some clocks
From: Shinobu Uehara shinobu.uehara...@renesas.com
Some controllers need to check SD bus status when writing data.
Then, it checks ILL_FUNC bit on SD_INFO2 register,
and this method is controlled via TMIO_MMC_HAS_IDLE_WAIT flags.
Same method is required on tmio_mmc_data_irq() which will
be called
From: Kuninori Morimoto kuninori.morimoto...@renesas.com
This patch ensures that the clock has been stopped before
it calls tmio_mmc_set_clock().
The clock settings might be failed without this patch
Tested-by: Nguyen Xuan Nui nx-...@jinso.co.jp
Tested-by: Hiep Cao Minh cm-h...@jinso.co.jp
On 22 August 2014 08:55, Barry Song barry.s...@csr.com wrote:
-Original Message-
From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
Sent: Monday, August 18, 2014 7:58 PM
To: Barry Song
Cc: Chris Ball; linux-mmc; linux-arm-ker...@lists.infradead.org; DL-SHA-
WorkGroupLinux; Minda Chen;
On 22 August 2014 10:36, Kuninori Morimoto
kuninori.morimoto...@gmail.com wrote:
From: Shinobu Uehara shinobu.uehara...@renesas.com
In some controllers, when performing a multiple block read of
one or two blocks, depending on the timing with which the
response register is read, the response
This patch makes use of mmc_regulator_get_supply() to handle
the vmmc and vqmmc regulators.Also it moves the code handling
the these regulators to dw_mci_set_ios().It turned on the vmmc
and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off
during MMC_POWER_OFF.
Signed-off-by: Yuvaraj
This series adds UHS support for dw_mmc driver.
Patch[1] reworks the handling of vmmc and vqmmc regulators by mmc core
regulator API's.
Patch[2] was taken from chrome tree originally developed by Doug Anderson.
Comments recieved for this patch to remove extra state machine for CMD11
handling is
From: Doug Anderson diand...@chromium.org
For UHS cards we need the ability to switch voltages from 3.3V to
1.8V. Add support to the dw_mmc driver to handle this. Note that
dw_mmc needs a little bit of extra code since the interface needs a
special bit programmed to the CMD register while CMD11
Exynos 5250 and 5420 based boards uses built-in CD# line for card
detection.But unfortunately CD# line is on the same voltage rails
as of I/O voltage rails. When we cut off vqmmc,the consequent card
detection will break in these boards.
These hosts (obviously) need to keep vqmmc (and thus vmmc)
On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
Exynos 5250 and 5420 based boards uses built-in CD# line for card
detection.But unfortunately CD# line is on the same voltage rails
as of I/O voltage rails. When we cut off vqmmc,the consequent card
detection will break in
On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
From: Doug Anderson diand...@chromium.org
For UHS cards we need the ability to switch voltages from 3.3V to
1.8V. Add support to the dw_mmc driver to handle this. Note that
dw_mmc needs a little bit of extra code since
On Fri, Aug 22, 2014 at 8:31 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
Exynos 5250 and 5420 based boards uses built-in CD# line for card
detection.But unfortunately CD# line is on the same voltage rails
as of I/O
Ulf,
On Fri, Aug 22, 2014 at 8:35 AM, Ulf Hansson ulf.hans...@linaro.org wrote:
On 22 August 2014 15:47, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
From: Doug Anderson diand...@chromium.org
For UHS cards we need the ability to switch voltages from 3.3V to
1.8V. Add support to the dw_mmc
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