On Mon, Jul 20, 2015 at 05:23:36PM +0200, Hans de Goede wrote:
> Hi,
>
> On 20-07-15 10:00, Maxime Ripard wrote:
> >Hi,
> >
> >On Fri, Jul 10, 2015 at 05:14:44PM +0200, Hans de Goede wrote:
> >>Some sdio wifi modules have not been working reliable with the sun
s command.
>
> This commit fixes this, thereby fixing the wifi reliability issues on
> the Cubietruck and other sunxi boards using sdio wifi.
>
> Reported-by: Eugene K
> Suggested-by: Eugene K
> Cc: Eugene K
You should use the "real" name here, and not some shortening.
M
.
> + const char *ing = oclk_en ? "enabling" : "disabling";
> +
> + if ((msecs > 150) || (oclk_en && (msecs > 50)))
> + dev_warn(mmc_dev(host->mmc),
> + "%s oclk took %ims", ing, ms
; Signed-off-by: Hans de Goede
Applied, thanks!
Maxime
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Hi Mike,
On Sat, Sep 27, 2014 at 05:17:32PM -0700, Mike Turquette wrote:
> Quoting Maxime Ripard (2014-09-11 13:18:17)
> > The current phase API doesn't look into the actual hardware to get the phase
> > value, but will rather get it from a variable only set by the se
arent_freq) * (parent_freq / divider)
If we simplify by removing the parent_freq, we end up with
phase = 360 * reg / divider, which makes it rather trivial to
calculate.
Maxime
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Hi Mike,
On Thu, Sep 25, 2014 at 05:42:18PM -0700, Mike Turquette wrote:
> Quoting Maxime Ripard (2014-09-22 04:31:33)
> > Mike,
> >
> > On Thu, Sep 11, 2014 at 10:18:14PM +0200, Maxime Ripard wrote:
> > > Hi everyone,
> > >
> > > Here is an a
Mike,
On Thu, Sep 11, 2014 at 10:18:14PM +0200, Maxime Ripard wrote:
> Hi everyone,
>
> Here is an attempt at improving the MMC clock support in the Allwinner
> SoCs.
>
> Until now, the MMC clocks were having a custom phase function that was
> directly setting an obscu
;sample",
> > + "output";
>
> Just a stylish nitpick. All the other resources in these files
> are listed inline if possible, not one phandle/value per line.
Look at the PIO interrupts, every USB PHY resources, etc. ;)
Maxime
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Move the MBUS clock to the module clocks file. It's pretty trivial, but still
requires to enable the clocks to make sure it won't get disabled.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-mod0.c | 12 +
drivers/clk/sunxi/clk-su
Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-mod0.c | 82 +++
drivers/clk
.
- Fixed a few typos here and there
- Added a patch to include of.h from clk-provider.h
Maxime Ripard (11):
clk: Include of.h in clock-provider.h
clk: Add a function to retrieve phase
clk: sunxi: factors: Invert the probing logic
clk: sunxi: Introduce mbus compatible
ARM: sunxi: dt
Add the sample and output clocks for the MMC phase support.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun4i-a10.dtsi | 104 +++---
arch/arm/boot/dts/sun5i-a10s.dtsi | 79 ++---
arch/arm/boot/dts/sun5i-a13.dtsi | 80
ic in smaller files, and led to a huge file
having all the clocks.
Introduce an intermediate probing function, so that factor clocks will be able
to directly be called by CLK_OF_DECLARE, which will in turn ease the split into
several files.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-fact
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.
Introduce a new compatible, to differentiate it from the other module clocks.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi
will not match what
the hardware has been programmed to by the bootloader or what phase is
programmed out of reset.
Add a new get_phase function for the drivers to implement so that we can get
this value.
Signed-off-by: Maxime Ripard
---
drivers/clk/clk.c| 10 ++
include/
framework
via the .set_phase call back in struct clk_ops.
Signed-off-by: Mike Turquette
Signed-off-by: Maxime Ripard
---
drivers/clk/clk.c| 85 +---
include/linux/clk-private.h | 1 +
include/linux/clk-provider.h | 5 +++
include/linux/clk.h
Now that we have proper support to use the generic phase API in our clock
driver, switch the MMC driver to use it.
Signed-off-by: Maxime Ripard
Acked-by: Ulf Hansson
---
.../devicetree/bindings/mmc/sunxi-mmc.txt | 8 +--
drivers/mmc/host/sunxi-mmc.c | 72
Now that we don't have any user left for our custom phase function, we can
safely remove this hack from the code.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 37 -
include/linux/clk/sunxi.h | 22 --
2 files ch
CLK_OF_DECLARE relies on OF_DECLARE_1 that is defined in of.h. Fixes build
errors when one use CLK_OF_DECLARE but doesn't include of.h
Signed-off-by: Maxime Ripard
---
include/linux/clk-provider.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/clk-provider.h b/include/
Now that we have a compatible of its own for the mbus clock, switch to it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
arch/arm/boot/dts/sun5i-a13.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
drivers/clk/sunxi/clk-mod0.c | 189 ++
2 files changed, 191 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock
On Mon, Sep 01, 2014 at 01:27:28PM +0200, Hans de Goede wrote:
> Hi,
>
> On 09/01/2014 12:20 PM, Maxime Ripard wrote:
> > Hi,
> >
> > On Sun, Aug 31, 2014 at 12:15:50PM +0200, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 08/30/2014 10:03 PM, Ma
Hi,
On Mon, Sep 01, 2014 at 12:00:54PM -0700, Mike Turquette wrote:
> Quoting Maxime Ripard (2014-08-30 13:03:02)
> > The current phase API doesn't look into the actual hardware to get the phase
> > value, but will rather get it from a variable only set by the se
Hi,
On Mon, Sep 01, 2014 at 02:39:45PM -0700, Mike Turquette wrote:
> Quoting Maxime Ripard (2014-08-30 13:03:09)
> > The MMC clock we thought we had until now are actually not one but three
> > different clocks.
> >
> > The main one is unchanged, and will have three
Hi,
On Sun, Aug 31, 2014 at 12:15:50PM +0200, Hans de Goede wrote:
> Hi,
>
> On 08/30/2014 10:03 PM, Maxime Ripard wrote:
> > The current phase API doesn't look into the actual hardware to get the phase
> > value, but will rather get it from a variable only set by
framework
via the .set_phase call back in struct clk_ops.
Signed-off-by: Mike Turquette
Signed-off-by: Maxime Ripard
---
drivers/clk/clk.c| 85 +---
include/linux/clk-private.h | 1 +
include/linux/clk-provider.h | 5 +++
include/linux/clk.h
: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
drivers/clk/sunxi/clk-mod0.c | 189 ++
2 files changed, 191 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock
Add the sample and output clocks for the MMC phase support.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun4i-a10.dtsi | 104 +++---
arch/arm/boot/dts/sun5i-a10s.dtsi | 79 ++---
arch/arm/boot/dts/sun5i-a13.dtsi | 80
Move the MBUS clock to the module clocks file. It's pretty trivial, but still
requires to enable the clocks to make sure it won't get disabled.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-mod0.c | 12 +
drivers/clk/sunxi/clk-su
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.
Introduce a new compatible, to differentiate it from the other module clocks.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi
Now that we don't have any user left for our custom phase function, we can
safely remove this hack from the code.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 37 -
include/linux/clk/sunxi.h | 22 --
2 files ch
Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-mod0.c | 82 +++
drivers/clk
ic in smaller files, and led to a huge file
having all the clocks.
Introduce an intermediate probing function, so that factor clocks will be able
to directly be called by CLK_OF_DECLARE, which will in turn ease the split into
several files.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-fact
will not match what
the hardware has been programmed to by the bootloader or what phase is
programmed out of reset.
Add a new get_phase function for the drivers to implement so that we can get
this value.
Signed-off-by: Maxime Ripard
---
drivers/clk/clk.c| 17 ++---
in
Now that we have a compatible of its own for the mbus clock, switch to it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
arch/arm/boot/dts/sun5i-a13.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
CLK_OF_DECLARE relies on OF_DECLARE_1 that is defined in of.h. Fixes build
errors when one use CLK_OF_DECLARE but doesn't include of.h
Signed-off-by: Maxime Ripard
---
include/linux/clk-provider.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/clk-provider.h b/include/
Now that we have proper support to use the generic phase API in our clock
driver, switch the MMC driver to use it.
Signed-off-by: Maxime Ripard
Acked-by: Ulf Hansson
---
.../devicetree/bindings/mmc/sunxi-mmc.txt | 8 +--
drivers/mmc/host/sunxi-mmc.c | 72
Tomeu, and should be based on this
whenever it will be merged.
- Fixed a few typos here and there
- Added a patch to include of.h from clk-provider.h
Maxime Ripard (11):
clk: Include of.h in clock-provider.h
clk: Add a function to retrieve phase
clk: sunxi: factors: Invert the
On Mon, Aug 25, 2014 at 10:17:37PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Thu, Jul 17, 2014 at 5:08 PM, Maxime Ripard
> wrote:
> > Even though the mbus clock is a regular module clock, given its nature, it
> > needs to be enabled all the time.
> >
>
Hi Hans,
On Sat, Jul 19, 2014 at 12:47:38PM +0200, Hans de Goede wrote:
> Hi,
>
> On 07/17/2014 11:08 AM, Maxime Ripard wrote:
> >Hi everyone,
> >
> >Here is an attempt at improving the MMC clock support in the Allwinner
> >SoCs.
> >
> >Until n
Now that we don't have any user left for our custom phase function, we can
safely remove this hack from the code.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-sunxi.c | 37 -
include/linux/clk/sunxi.h | 22 --
2 files ch
Move the MBUS clock to the module clocks file. It's pretty trivial, but still
requires to enable the clocks to make sure it won't get disabled.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-mod0.c | 12 +
drivers/clk/sunxi/clk-su
ic in smaller files, and led to a huge file
having all the clocks.
Introduce an intermediate probing function, so that factor clocks will be able
to directly be called by CLK_OF_DECLARE, which will in turn ease the split into
several files.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-fact
framework
via the .set_phase call back in struct clk_ops.
Signed-off-by: Mike Turquette
Signed-off-by: Maxime Ripard
---
drivers/clk/clk.c| 84 +---
include/linux/clk-private.h | 1 +
include/linux/clk-provider.h | 5 +++
include/linux/clk.h
Add the sample and output clocks for the MMC phase support.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun4i-a10.dtsi | 104 +++---
arch/arm/boot/dts/sun5i-a10s.dtsi | 79 ++---
arch/arm/boot/dts/sun5i-a13.dtsi | 80
solve
that by adding two new properties in the DT to setup the rate
constraints we might have on a clock.
Thanks,
Maxime
Maxime Ripard (13):
clk: Introduce new frequency boundaries properties
clk: sunxi: factors: Implement clock min and max frequencies
ARM: sunxi: sun5i: Enforce max frequency
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.
Introduce a new compatible, to differentiate it from the other module clocks.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi
Now that we have a compatible of its own for the mbus clock, switch to it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +-
arch/arm/boot/dts/sun5i-a13.dtsi | 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git
will not match what
the hardware has been programmed to by the bootloader or what phase is
programmed out of reset.
Add a new get_phase function for the drivers to implement so that we can get
this value.
Signed-off-by: Maxime Ripard
---
drivers/clk/clk.c| 17 ++---
in
Now that we have proper support to use the generic phase API in our clock
driver, switch the MMC driver to use it.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/mmc/sunxi-mmc.txt | 8 +--
drivers/mmc/host/sunxi-mmc.c | 72 +++---
2
: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi.txt | 2 +
drivers/clk/sunxi/clk-mod0.c | 189 ++
2 files changed, 191 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock
Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-mod0.c | 82 +++
drivers/clk
PLL6 out of reset is running at 2.4GHz, which is outside of its operating
boundaries.
Enforce its maximum frequency as set in the datasheet to make sure we stays
within these bounds.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
1 file changed, 1 insertion(+)
diff
Introduce the properties clock-min-frequency and clock-max frequency to be able
to set constraints on the range of frequency usable by the clock, even though
the hardware might be able to program frequencies outside of thes bounds.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree
never cross these boundaries.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-factors.c | 28
drivers/clk/sunxi/clk-factors.h | 2 ++
2 files changed, 30 insertions(+)
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index
On Sat, May 31, 2014 at 11:13:05AM +0200, Hans de Goede wrote:
> Hi,
>
> On 05/28/2014 12:33 PM, Maxime Ripard wrote:
> >On Wed, May 28, 2014 at 11:51:52AM +0200, Hans de Goede wrote:
> >>Hi,
> >>
> >>On 05/28/2014 11:36 AM, Maxime Ripard wrote:
>
On Wed, May 28, 2014 at 11:51:52AM +0200, Hans de Goede wrote:
> Hi,
>
> On 05/28/2014 11:36 AM, Maxime Ripard wrote:
> > On Tue, May 27, 2014 at 04:18:29PM +0200, Linus Walleij wrote:
> >> On Mon, May 26, 2014 at 9:47 AM, Hans de Goede wrote:
> >>
> >
On Tue, May 27, 2014 at 06:14:31PM +0200, Tomasz Figa wrote:
> On 27.05.2014 10:07, Maxime Ripard wrote:
> > On Mon, May 26, 2014 at 09:47:57AM +0200, Hans de Goede wrote:
> >> From: Chen-Yu Tsai
> >>
> >> The sunxi pinctrl irq chip driver does not suppor
On Tue, May 27, 2014 at 11:01:03AM +0200, Hans de Goede wrote:
> Hi,
>
> On 05/27/2014 10:09 AM, Maxime Ripard wrote:
> > On Mon, May 26, 2014 at 09:47:58AM +0200, Hans de Goede wrote:
> >> With level triggered interrupt mask / unmask will get called for each
> >&
> up the muxing in the pinctrl driver side?
Because the function it has to be muxed to is neither gpio_in or
gpio_out, and it's not even considered a gpio. It really is just
another muxing function, like i2c or mmc.
Maxime
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l_irq_unmask,
> .irq_set_type = sunxi_pinctrl_irq_set_type,
> + .name = "sunxi-pio",
> + .flags = IRQCHIP_SKIP_SET_WAKE,
I'd rather see the name set to dev_name() or something like that. This
will not work that great with multiple pin controller su
ly
> done only once for each irq.
*This* is the bad idea. Nothing prevents you from calling
gpio_get_value whenever you just got your interrupt, that will change
the muxing, and never change it back, effectively breaking the
interrupts.
Maxime
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Embedded Linux
s us to map the
> interrupts directly from the device tree.
Can you be a bit more precise on this?
What is the issue that this patch fix?
Maxime
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ime's sunxi-dts tree.
I just merged the last 5 patches.
Thanks!
Maxime
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the host is not identical to mmc-dw, it deals with
> sending stop commands in hardware which makes it significantly different
> from the mmc-dw devices.
>
> HdG: Various cleanups and fixes.
>
> Signed-off-by: David Lanzendörfer
> Signed-off-by: Hans de Goede
Acked-by: Maxime R
regulator-max-microvolt = <330>;
> + status = "disabled";
> + };
I think you can rather define this as vcc-3.3v or something alike,
that would always be enabled. That would allow to reuse this in some
other nodes as well, you won't need to en
seen sofar use 3.3V which seems sensible since that is
> what the spec says you must supply to SDSC cards. I agree that if a board
> differs from the standard 3.3V, a fixed regulator node specifying the
> voltage should be added.
I think we introduced the sunxi-regulators DTSI just for this :)
I'd really like to start stabilizing a bit the DT and at least
consider being able to use an older DT on a newer kernel. If we take
such approach, I'm afraid it will break at some point.
Maxime
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hen convert to the
clk_set_phase proposal whenever we will have the details of the phase
values?
Thanks,
Maxime
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Hi Emilio,
On Fri, May 02, 2014 at 05:57:15PM +0200, Hans de Goede wrote:
> From: Emilio López
>
> This commit implements .determine_rate, so that our factor clocks can be
> reparented when needed.
>
> Signed-off-by: Emilio López
> Signed-off-by: Hans de Goede
> Acked
> The WiFi module supports out-of-band interrupt signaling via GPIO,
> but this is not supported in this patch.
>
> Signed-off-by: Hans de Goede
Applied with Chen-Yu SoB.
Maxime
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On Mon, May 05, 2014 at 12:20:56PM +0800, Chen-Yu Tsai wrote:
> On Mon, May 5, 2014 at 12:02 PM, Maxime Ripard
> wrote:
> > On Fri, May 02, 2014 at 05:57:29PM +0200, Hans de Goede wrote:
> >> From: Chen-Yu Tsai
> >>
> >> The CubieTruck has an AMPAK
> The WiFi module supports out-of-band interrupt signaling via GPIO,
> but this is not supported in this patch.
>
> Signed-off-by: Hans de Goede
It doesn't have Chen-Yu SoB. Chen-Yu, are you fine with adding it?
No need to respin the set, I'll add it when applying if i
e mmc tree.
>
> All the other patches are devicetree patches hooking things up, and should
> go upstream through Maxime's sunxi-dt tree.
Applied patches 4 to 14.
Thanks!
Maxime
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On Sat, Apr 26, 2014 at 12:16:16PM +0200, Hans de Goede wrote:
> This adds pin-muxing info for the mmc controller / port combinations which
> are known to be used on actual boards.
>
> Signed-off-by: Hans de Goede
Applied, thanks!
Maxime
--
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Em
t5";
> };
>
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
And this is not misleading but wrong. The MMC clocks have the phase
control f
> + mmc0_cd_pin_a: mmc0_cd_pin@0 {
> + allwinner,pins = "PH1";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <0>;
> + allwin
inner,sun5i-a13-mmc"
> + - reg : mmc controller base registers
> + - clocks : a list with 2 phandle + clock specifier pairs
> + - clock-names : must contain "ahb" and "mod"
Again, this is not a module0 clock, so the clock name is misleading.
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On Sat, Apr 26, 2014 at 12:16:12PM +0200, Hans de Goede wrote:
> This adds pin-muxing info for the mmc controller / port combinations which
> are known to be used on actual boards.
>
> Signed-off-by: Hans de Goede
Applied, thanks!
Maxime
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Em
On Sat, Apr 26, 2014 at 12:16:05PM +0200, Hans de Goede wrote:
> From: Emilio López
>
> This commit implements .determine_rate, so that our factor clocks can be
> reparented when needed.
>
> Signed-off-by: Emilio López
> Signed-off-by: Hans de Goede
Acked-by: Maxime Ri
enforce
a given frequency for that card_ext_clock, or the fact that it has
several SDIO cards connected to them, each with different
clocks/reset/regulator lines.
While all of this would easily be solved by representing all this as a
bus, like it should, with subdevices grabbing their own clocks and
having whatever property they need.
Maxime
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es hooking things up, and should
> go upstream through Maxime's sunxi-dt tree.
Apart from the ever-controversial phase control thing, and the minor
comments I had here and there, this looks good, thanks!
Maxime
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On Tue, Apr 22, 2014 at 01:01:34PM +0200, Hans de Goede wrote:
> Tested on a Mele A1000G Quad.
>
> Signed-off-by: Hans de Goede
This patch can be merged with the previous one.
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Maxime Ripard, Free Electrons
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clocks = <&ahb1_gates 8>, <&mmc0_clk>;
> + clock-names = "ahb", "mod";
> + resets = <&ahb1_rst 8>;
> + reset-names = "ahb";
> + interrupts = <0 60 4>;
> +
;
> + clock-names = "ahb", "mod";
> + interrupts = <32>;
> + status = "disabled";
> + };
> +
> + mmc2: mmc@01c11000 {
> + compati
ol, while we do here.
You should introduce a new compatible.
(and change the clock-names content accordingly)
Maxime
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Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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distros from shipping with
> sunxi
> support ootb. So I would really prefer to just get this merged as is for now,
> changing it later should be easy, and merging an interim solution will make
> some more time for doing the generic clk phase control method properly.
While I'd be inclined to agree, it will be up to Mike.
Mike?
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Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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On Wed, Mar 19, 2014 at 04:39:45PM -0700, Mike Turquette wrote:
> Quoting Maxime Ripard (2014-02-18 06:05:16)
> > On Mon, Feb 17, 2014 at 11:02:15AM +0100, David Lanzendörfer wrote:
> > > From: Emilio López
> > >
> > > This commit implements .determine_ra
her.
> I can throw in a line for refering to the mmc slot gpio lib docs.
Yes, that would be great :)
> > Isn't the cd-gpios property requested too?
> I can refer to the docs there as well if you like... :-)
That would be great too :)
Thanks!
Maxime
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Maxime Ripard, Free Electrons
gt;>
> >> Nope, we only need this to get the data on sunxi_mmc_remove,
> >> everywhere else the data is found through the mmc-host struct.
> >
> > Still, if anyone makes a following patch using the platform_device
> > for some reason, we will have a race condition, without any way to
> > notice it.
> >
> > Plus, you're doing all the other bits of initialization of your
> > structures much earlier, why not be consistent and having all of
> > them at the same place?
>
> Most platform drivers I've worked on do platform_set_drvdata as late
> as possible, so that the drvdata does not get set and never cleared
> in error paths.
You don't actually have to clear it, and some frameworks actually
require you to call dev_set_drvdata before registration, so that
statement looks quite odd to me.
Thanks!
Maxime
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Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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On Tue, Feb 18, 2014 at 04:10:38PM +0100, Hans de Goede wrote:
> Hi,
>
> On 02/18/2014 03:22 PM, Maxime Ripard wrote:
> >On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
> >>Signed-off-by: David Lanzendörfer
> >>Signed-off-by: Hans de Goede
Hi Hans,
On Tue, Feb 18, 2014 at 09:49:21PM +0100, Hans de Goede wrote:
> Hi,
>
> On 02/18/2014 04:37 PM, Maxime Ripard wrote:
>
>
>
> >>+
> >>+ for (i = 0; i < data->sg_len; i++) {
> >>+ pdes[i
;&mmc0_clk>;
> + clock-names = "ahb", "mod";
You never talked about the clock-names property, and which clocks were
supposed to be provided.
> + interrupts = <0 32 4>;
> + bus-width = <4>;
And you never talked about bus-width either.
> + status = "disabled";
> +};
>
Isn't the cd-gpios property requested too?
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Maxime Ripard, Free Electrons
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efine SDXC_END_BIT_ERROR BIT(15)
> +#define SDXC_SDIO_INTERRUPT BIT(16)
> +#define SDXC_CARD_INSERT BIT(30)
> +#define SDXC_CARD_REMOVE BIT(31)
> +#define SDXC_INTERRUPT_ERROR_BIT (SDXC_RESP_ERROR |
> SDXC_RESP_CRC_ERROR | \
pio: pinctrl@01c20800 {
> compatible = "allwinner,sun7i-a20-pinctrl";
> reg = <0x01c20800 0x400>;
> @@ -432,6 +472,27 @@
> allwinner,drive = <0>;
> allwinner,pull = <0>;
On Mon, Feb 17, 2014 at 11:02:28AM +0100, David Lanzendörfer wrote:
> From: Hans de Goede
>
> Signed-off-by: Hans de Goede
Again, your SoB is missing, and that can be squashed with the previous
patch.
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Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
ht
ework road, some documentation on what are the
arguments it takes and what it's supposed to return would be great.
Thanks!
Maxime
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Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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ed it, you can add my Acked-by
Maxime
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Maxime Ripard, Free Electrons
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http://free-electrons.com
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anges you made. Otherwise we have no way
of knowing what have been fixed and what didn't
Looking forward for the next iteration!
Thanks,
Maxime
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Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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On Mon, Dec 16, 2013 at 12:59:31PM +0100, Michal Suchanek wrote:
> On 16 December 2013 11:05, Maxime Ripard
> wrote:
> > On Sun, Dec 15, 2013 at 11:01:17PM +0100, Michal Suchanek wrote:
> >> On 15 December 2013 14:44, Maxime Ripard
> >> wrote:
> >> >>
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