On 15 February 2015 at 16:43, Barry Song 21cn...@gmail.com wrote:
From: weijun yang york.y...@csr.com
For the original tuning code, delay value is set to SD Bus Clock Delay
Register (SD_CLK_DELAY_SETTING) as (val | (Val 7) | (val 16)),
which means CLK_DELAY_IN1, CLK_DELAY_IN2 and
ping Ulf
2015-02-15 23:43 GMT+08:00 Barry Song 21cn...@gmail.com:
From: weijun yang york.y...@csr.com
For the original tuning code, delay value is set to SD Bus Clock Delay
Register (SD_CLK_DELAY_SETTING) as (val | (Val 7) | (val 16)),
which means CLK_DELAY_IN1, CLK_DELAY_IN2 and
From: weijun yang york.y...@csr.com
For the original tuning code, delay value is set to SD Bus Clock Delay
Register (SD_CLK_DELAY_SETTING) as (val | (Val 7) | (val 16)),
which means CLK_DELAY_IN1, CLK_DELAY_IN2 and CLK_DELAY_OUT are the
same and with 128 steps. This is doubtful. In CSR design
